CN112817645A - BIOS starting method, device, equipment and readable storage medium - Google Patents
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- CN112817645A CN112817645A CN202110105772.1A CN202110105772A CN112817645A CN 112817645 A CN112817645 A CN 112817645A CN 202110105772 A CN202110105772 A CN 202110105772A CN 112817645 A CN112817645 A CN 112817645A
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- 238000004590 computer program Methods 0.000 claims description 12
- 238000004364 calculation method Methods 0.000 claims description 7
- 230000000694 effects Effects 0.000 abstract description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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Abstract
The application discloses a BIOS starting method, a BIOS starting device, BIOS equipment and a readable storage medium. The method disclosed by the application is applied to the FPGA and comprises the following steps: if the BIOS is electrified, acquiring the control right of the SPI memory from the BMC so as to read partial data in the target data from the SPI memory; the target data is all data required for starting the BIOS; returning the control right to the BMC, and calculating a check value of partial data; and checking the check value, and if the check value passes, loading the target data in the SPI memory by using the BMC so as to start the BIOS. According to the method and the device, the effectiveness and the usability of the BIOS can be detected when the BIOS is powered on, so that the operation fault caused by the unavailability of the BIOS after the server is started can be avoided. Accordingly, the BIOS starting device, the device and the readable storage medium provided by the present application also have the technical effects described above.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a BIOS starting method, device, apparatus, and readable storage medium.
Background
At present, in the process of powering on a server, the power-on sequence of a Basic Input/Output System (BIOS) in the server can be controlled, but the validity and availability of the BIOS are not judged, and hidden troubles are left for the safe operation of the server. Therefore, how to check the validity and availability of the BIOS when the BIOS is powered on is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present application is directed to a BIOS booting method, apparatus, device and readable storage medium for checking BIOS validity and availability. The specific scheme is as follows:
in a first aspect, the present application provides a BIOS starting method, applied to an FPGA, including:
if the BIOS is electrified, acquiring the control right of the SPI memory from the BMC so as to read partial data in the target data from the SPI memory; the target data is all data required for starting the BIOS;
returning the control right to the BMC, and calculating a check value of the partial data;
and checking the check value, and if the check value passes, loading the target data in the SPI memory by using the BMC so as to start the BIOS.
Preferably, the reading of part of the target data from the SPI memory includes:
reading the first N bits of data in the target data from the SPI memory, wherein N is a 16-ary number and is not less than 0x 2000.
Preferably, the reading of part of the target data from the SPI memory includes:
and reading the last N bits of data in the target data from the SPI memory, wherein N is a 16-system number and is not less than 0x 2000.
Preferably, the reading of part of the target data from the SPI memory includes:
and reading the data from the X bit to the X + N bit in the target data from the SPI memory, wherein X and N are 16-ary numbers and N is not less than 0X 2000.
Preferably, the calculating the check value of the partial data includes:
the MD5 value of the partial data is calculated.
Preferably, the checking the check value includes:
judging whether the MD5 value is consistent with a preset MD5 value in the FPGA; the preset MD5 value is obtained through calculation based on the partial data and is stored in the FPGA;
if yes, the check is passed; otherwise, the check fails.
Preferably, if the BIOS is upgraded, the partial data is kept unchanged.
In a second aspect, the present application provides a BIOS starting apparatus, applied to an FPGA, including:
the reading module is used for acquiring the control right of the SPI memory from the BMC if the BIOS is electrified so as to read partial data in target data from the SPI memory; the target data is all data required for starting the BIOS;
the calculation module is used for returning the control right to the BMC and calculating a check value of the partial data;
and the starting module is used for checking the check value, and if the check value passes, the target data in the SPI memory is loaded by using the BMC so as to start the BIOS.
In a third aspect, the present application provides an electronic device, comprising:
a memory for storing a computer program;
and the processor is used for executing the computer program to realize the BIOS starting method disclosed in the foregoing.
In a fourth aspect, the present application provides a readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the BIOS startup method disclosed above.
According to the scheme, the BIOS starting method is applied to the FPGA and comprises the following steps: if the BIOS is electrified, acquiring the control right of the SPI memory from the BMC so as to read partial data in the target data from the SPI memory; the target data is all data required for starting the BIOS; returning the control right to the BMC, and calculating a check value of the partial data; and checking the check value, and if the check value passes, loading the target data in the SPI memory by using the BMC so as to start the BIOS.
Therefore, the FPGA is used for controlling the power-on process of the BIOS, if the BIOS is powered on, the FPGA acquires the control right of the SPI memory from the BMC so that after part of data in all data needed for starting the BIOS is read from the SPI memory, the control right is returned to the BMC, then a check value of the part of data is calculated and checked, if the check value passes, the data needed for starting the BIOS is normal, namely the BIOS is effective and available, and therefore the BMC is used for loading target data in the SPI memory so as to start the BIOS. According to the method and the device, the effectiveness and the usability of the BIOS can be detected when the BIOS is powered on, so that the operation fault caused by the unavailability of the BIOS after the server is started can be avoided.
Accordingly, the BIOS starting device, the device and the readable storage medium provided by the present application also have the technical effects described above.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a BIOS boot method disclosed herein;
FIG. 2 is a flow chart of another BIOS boot method disclosed herein;
FIG. 3 is a schematic diagram of a BIOS boot device according to the present disclosure;
fig. 4 is a schematic diagram of an electronic device disclosed in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, in the process of powering on a server, the power-on sequence of a Basic Input/Output System (BIOS) in the server can be controlled, but the validity and availability of the BIOS are not judged, and hidden troubles are left for the safe operation of the server. Therefore, the BIOS starting scheme is provided, the effectiveness and the availability of the BIOS can be detected when the BIOS is powered on, and therefore the running fault caused by the fact that the BIOS is unavailable after a server is started can be avoided.
Referring to fig. 1, an embodiment of the present application discloses a BIOS starting method, which is applied to an FPGA (Field Programmable Gate Array), and includes:
and S101, if the BIOS is electrified, acquiring the control right of the SPI memory from the BMC so as to read partial data in the target data from the SPI memory.
The target data is all data required for starting the BIOS, that is, various codes that the BIOS needs to run for starting, and various data related to the codes. The present embodiment takes out a part thereof to be used as check data.
The SPI (Serial Peripheral Interface) memory is an SPI FLASH in which all data required to start the BIOS is stored.
The partial data in the target data may be selected and determined in various ways, for example, any one of the three ways listed below.
The first method is as follows: reading partial data in the target data from the SPI memory, and the method comprises the following steps: and reading the first N bits of data in the target data from the SPI memory, wherein N is a 16-system number and is not less than 0x 2000. Namely: starting from the header of the target data, the first N bits of data are selected.
The first method is as follows: reading partial data in the target data from the SPI memory, and the method comprises the following steps: and reading the last N bits of data in the target data from the SPI memory, wherein N is a 16-system number and is not less than 0x 2000. Namely: the last N bits of data are selected from the inverse of the tail of the target data.
The first method is as follows: reading partial data in the target data from the SPI memory, and the method comprises the following steps: and reading the data from the X bit to the X + N bit in the target data from the SPI memory, wherein X and N are 16-ary numbers and N is not less than 0X 2000. Namely: x bits to X + N bits of data at the intermediate position in the target data are selected.
It should be noted that the selected partial data needs to have a sufficient data size, so the present embodiment uses N to guarantee the data size of the partial data.
And S102, returning the control right to the BMC, and calculating a check value of partial data.
S103, checking the check value, and if the check value passes, loading the target data in the SPI memory by using the BMC to start the BIOS.
In this embodiment, the FPGA is used to control a power-on process of the BIOS, if the BIOS is powered on, the FPGA acquires a control right of the SPI memory from the BMC, so that after a part of data in all data required for starting the BIOS is read from the SPI memory, the control right is returned to the BMC, a check value of the part of data is calculated and checked, and if the check value passes, it is indicated that the data required for starting the BIOS is normal, that is, the BIOS is valid and usable, so that target data in the SPI memory is loaded by using a BMC (Baseboard Management Controller), thereby starting the BIOS.
The check value of the partial data may use its MD5(Message-Digest algorithm 5) value.
In one embodiment, calculating a check value for a portion of data includes: MD5 values for the partial data are calculated. In one embodiment, the verifying the verification value includes: judging whether the MD5 value is consistent with a preset MD5 value in the FPGA; the preset MD5 value is obtained based on partial data calculation and is stored in the FPGA; if yes, the check is passed; otherwise, the check fails. Namely: and storing the MD5 value of the corresponding partial data in the FPGA when the BIOS is shipped from a factory, and noting the selection condition of the partial data.
In one embodiment, if the BIOS is upgraded, a portion of the data is kept unchanged so that the availability and validity of the BIOS may continue to be checked based on the portion of the data.
It can be seen that in the embodiment of the present application, the FPGA is used to control the power-on process of the BIOS, if the BIOS is powered on, the FPGA acquires the control right of the SPI memory from the BMC, so that after part of data in all data required for starting the BIOS is read from the SPI memory, the control right is returned to the BMC, then a check value of the part of data is calculated, and the check value is checked, if the check value passes, it is indicated that the data required for starting the BIOS is normal, that is, the BIOS is valid and available, so that the target data in the SPI memory is loaded by using the BMC, thereby starting the BIOS, and thus, an operation failure caused by unavailability of the BIOS after the server is started can be avoided.
Referring to fig. 2, the embodiment of the present application discloses another BIOS starting method, which embeds MD5 values of 0-0x2000 bits of data in an SPI FLASH into an FPGA when a BIOS is shipped. And then after the mainboard of the server is powered on, the FPGA powers on each chip on the mainboard, when the BIOS is powered on, the FPGA firstly takes the control right of the SPI FLASH to read the data of 0-0x2000 bit in the SPI FLASH, then the MD5 value of the partial data is calculated, and the MD5 value is compared with the MD5 value in the FPGA. If the two are consistent, the verification is passed, and the BIOS is powered on. Otherwise, if the verification fails, outputting a prompt message that the BIOS has errors so that a technician can check the BIOS.
In this embodiment, the BIOS is started based on the FPGA, and the specific process includes:
in step 1, when leaving factory, setting the MD5 value of 0-0x2000 bit data of BIOS in SPI FLASH into FPGA;
in step 2, after the mainboard of the server is powered on, the FPGA enables each chip on the mainboard to enter a standby state;
in step 3, when the BIOS is powered on, the FPGA first takes the control right of the SPI FLASH to read the data of 0-0x2000 bits in the SPI FLASH; after reading the data, switching the controller of the SPI FLASH to the BMC;
in step 4, calculating an MD5 value of the data by using an MD5 algorithm, and comparing the MD5 value with an MD5 value in the FPGA;
in step 5, after the verification is passed, the BIOS is powered on, and the Aspped chip of the BMC loads BIOS starting data in the SPI FLASH to complete the starting of the BIOS.
In order to solve the problem that the value of MD5 changes after the BIOS is shipped, the data of 0 to 0x2000 may be kept fixed and not changed due to the upgrade, considering that the BIOS is upgraded after being shipped from the factory.
In the embodiment, the FPGA is used for controlling the power-on process of the BIOS, if the BIOS is powered on, the FPGA acquires the control right of the SPI memory from the BMC so as to read partial data in all data required for starting the BIOS in the SPI memory, then the control right is returned to the BMC, then a check value of the partial data is calculated and checked, if the check value passes, the data required for starting the BIOS is normal, namely the BIOS is effective and available, therefore, target data in the SPI memory is loaded by using the BMC so as to start the BIOS, and operation faults caused by the unavailability of the BIOS after the server is started can be avoided.
In the following, a BIOS starting device provided by the embodiments of the present application is introduced, and a BIOS starting device described below and a BIOS starting method described above may be referred to each other.
Referring to fig. 3, an embodiment of the present application discloses a BIOS starting apparatus, which is applied to an FPGA, and includes:
the reading module 301 is configured to, if the BIOS is powered on, obtain a control right of the SPI memory from the BMC, so as to read a part of data in the target data from the SPI memory; the target data is all data required for starting the BIOS;
a calculating module 302, configured to return the control right to the BMC, and calculate a check value of part of the data;
and the starting module 303 is configured to check the check value, and if the check value passes, load the target data in the SPI memory by using the BMC to start the BIOS.
In an embodiment, the reading module is specifically configured to:
and reading the first N bits of data in the target data from the SPI memory, wherein N is a 16-system number and is not less than 0x 2000.
In an embodiment, the reading module is specifically configured to:
and reading the last N bits of data in the target data from the SPI memory, wherein N is a 16-system number and is not less than 0x 2000.
In an embodiment, the reading module is specifically configured to:
and reading the data from the X bit to the X + N bit in the target data from the SPI memory, wherein X and N are 16-ary numbers and N is not less than 0X 2000.
In one embodiment, the calculation module is specifically configured to:
MD5 values for the partial data are calculated.
In a specific embodiment, the starting module is specifically configured to:
judging whether the MD5 value is consistent with a preset MD5 value in the FPGA; the preset MD5 value is obtained based on partial data calculation and is stored in the FPGA; if yes, the check is passed; otherwise, the check fails.
In one embodiment, if the BIOS is upgraded, a portion of the data is kept unchanged.
For more specific working processes of each module and unit in this embodiment, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not described here again.
Therefore, the embodiment provides a BIOS starting device, which can detect the validity and availability of a BIOS when the BIOS is powered on, so as to avoid an operation failure caused by unavailability of the BIOS after a server is started.
In the following, an electronic device provided by the embodiments of the present application is introduced, and a BIOS starting method and apparatus described below and described above may be referred to each other.
Referring to fig. 4, an embodiment of the present application discloses an electronic device, including:
a memory 401 for storing a computer program;
a processor 402 for executing said computer program for implementing the method disclosed in any of the embodiments described above.
In the following, a readable storage medium provided by an embodiment of the present application is introduced, and a readable storage medium described below and a BIOS starting method, apparatus, and device described above may be referred to each other.
A readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the BIOS startup method disclosed in the foregoing embodiments. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, which are not described herein again.
References in this application to "first," "second," "third," "fourth," etc., if any, are intended to distinguish between similar elements and not necessarily to describe a particular order or sequence. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, or apparatus.
It should be noted that the descriptions in this application referring to "first", "second", etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of readable storage medium known in the art.
The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A BIOS starting method is applied to an FPGA and comprises the following steps:
if the BIOS is electrified, acquiring the control right of the SPI memory from the BMC so as to read partial data in the target data from the SPI memory; the target data is all data required for starting the BIOS;
returning the control right to the BMC, and calculating a check value of the partial data;
and checking the check value, and if the check value passes, loading the target data in the SPI memory by using the BMC so as to start the BIOS.
2. The BIOS start-up method of claim 1 wherein the reading of the partial data of the target data from the SPI memory comprises:
reading the first N bits of data in the target data from the SPI memory, wherein N is a 16-ary number and is not less than 0x 2000.
3. The BIOS start-up method of claim 1 wherein the reading of the partial data of the target data from the SPI memory comprises:
and reading the last N bits of data in the target data from the SPI memory, wherein N is a 16-system number and is not less than 0x 2000.
4. The BIOS start-up method of claim 1 wherein the reading of the partial data of the target data from the SPI memory comprises:
and reading the data from the X bit to the X + N bit in the target data from the SPI memory, wherein X and N are 16-ary numbers and N is not less than 0X 2000.
5. The BIOS boot method of claim 1, wherein the calculating the check value of the portion of data comprises:
the MD5 value of the partial data is calculated.
6. The BIOS start-up method of claim 5 wherein the verifying the check value comprises:
judging whether the MD5 value is consistent with a preset MD5 value in the FPGA; the preset MD5 value is obtained through calculation based on the partial data and is stored in the FPGA;
if yes, the check is passed; otherwise, the check fails.
7. The BIOS startup method according to any one of claims 1 to 6, wherein if the BIOS is upgraded, the partial data is kept unchanged.
8. A BIOS starting device is applied to FPGA and comprises:
the reading module is used for acquiring the control right of the SPI memory from the BMC if the BIOS is electrified so as to read partial data in target data from the SPI memory; the target data is all data required for starting the BIOS;
the calculation module is used for returning the control right to the BMC and calculating a check value of the partial data;
and the starting module is used for checking the check value, and if the check value passes, the target data in the SPI memory is loaded by using the BMC so as to start the BIOS.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the BIOS startup method of any one of claims 1 to 7.
10. A readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the BIOS startup method of any one of claims 1 to 7.
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Cited By (1)
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| CN113765827A (en) * | 2021-07-21 | 2021-12-07 | 苏州浪潮智能科技有限公司 | Switch firmware protection system |
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| CN110109715A (en) * | 2019-05-08 | 2019-08-09 | 苏州浪潮智能科技有限公司 | A kind of system and method for server security starting |
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