CN111783162A

CN111783162A - Data protection implementation method and device and computer equipment

Info

Publication number: CN111783162A
Application number: CN202010622280.5A
Authority: CN
Inventors: 陈融; 董彦生; 何士贵
Original assignee: Lenovo Beijing Ltd
Current assignee: Lenovo Beijing Ltd
Priority date: 2020-06-30
Filing date: 2020-06-30
Publication date: 2020-10-16

Abstract

The application provides a method, a device and a computer device for realizing data protection, which are used for the computer device with a mainboard controller working in a hardware sequencing mode, to address the limitation of its platform on the number of SPI ROM commands sent by the motherboard controller, the OTP operation on the second firmware storage space can be reliably realized, the application can adjust the first working parameter in the first firmware storage space of the computer device to the target working parameter, so that the mainboard controller is switched to work in a software sequencing mode, and can send all write protection starting instructions for realizing OTP operation to the firmware of the computer equipment, by responding to the write protection starting instruction, the OTP operation on the second firmware storage space is executed, the operations of changing and clearing data in the second firmware storage space after the computer leaves the factory are avoided, and the safety and reliability of the data in the second firmware storage space are improved.

Description

Data protection implementation method and device and computer equipment

Technical Field

The present application relates to the field of computer security applications, and in particular, to a method and an apparatus for implementing data protection, and a computer device.

Background

The main function of BIOS (Basic Input and Output System, which may be referred to as firmware) is to provide the bottom layer and most direct hardware setting and control for computer equipment, and important data of BIOS is burned in a Read-Only Memory (ROM) of an electrically erasable ROM on a motherboard for storage.

In order to implement write protection of important BIOS data, the prior art generally uses a write protection pin in a ROM chip, and specifically, by pulling up a voltage of the write protection pin, an input instruction can only read the important BIOS data, and is not allowed to be erased or rewritten, thereby preventing the important BIOS data from being damaged.

However, in practical applications, in the existing data protection implementation manner for pulling up the voltage of the write protection pin of the ROM chip, the voltage of the write protection pin is easily pulled down by configuring a voltage change circuit, which results in invalid write protection state of the ROM chip, and further, important data of the BIOS is tampered at will, and the security of the computer system cannot be guaranteed.

Disclosure of Invention

In view of the above, in order to implement permanent write protection on important data in a computer device, in one aspect, the present application provides a data protection implementation method, where the method includes:

acquiring a target working parameter, and adjusting the first working parameter of a first firmware storage space of computer equipment to the target working parameter so as to enable a mainboard controller of the computer equipment to work in a hardware sequencing mode by switching to a software sequencing mode;

receiving a write protection starting instruction sent by the mainboard controller in the software sorting mode;

and responding to the write-protection starting instruction, and executing write-once protection operation aiming at a second firmware storage space of the computer equipment.

Optionally, before the performing the write-once protection operation for the second firmware storage space of the computer device, the method further includes:

in response to a partition request for a firmware storage space of the computer device, partitioning the firmware storage space into a first firmware storage space and a second firmware storage space;

acquiring data to be protected, and writing the data to be protected into the second firmware storage space;

and in the application running process of the computer equipment, responding to a data writing request aiming at the first firmware storage space and forbidding responding to a data writing request aiming at the second firmware storage space.

Optionally, the obtaining the target operating parameter and adjusting the first operating parameter of the first firmware storage space of the computer device to the target operating parameter include:

acquiring a first target state parameter of a first register and a second target state parameter of a second register of a first firmware storage space of computer equipment;

and updating the first state parameter of the first register to the first target state parameter, and updating the second state parameter of the second register to the second target state parameter.

Optionally, the method further includes:

verifying whether a write-once protection operation for the second firmware storage space is successful;

if the first firmware storage space is successful, restoring the current target working parameter of the first firmware storage space to the first working parameter so as to enable the mainboard controller to work in the software sorting mode by switching to the hardware sorting mode;

and responding to a data reading request aiming at the second firmware storage space, and reading the requested data stored in the second firmware storage space.

In another aspect, the present application further provides a method for implementing data protection, where the method includes:

determining that a first working parameter of a first firmware storage space of a computer equipment firmware is adjusted to be a target working parameter, and switching from a hardware sorting mode to a software sorting mode to work;

acquiring a write protection starting instruction for starting write protection operation once;

sending the write-protection start instruction to the firmware so that the firmware executes a write-once protection operation for a second firmware storage space of the firmware in response to the write-protection start instruction.

Optionally, the method further includes:

reading a mainboard type identifier recorded by an external interface memory, wherein the mainboard type identifier is written into the external interface memory by adopting a write-once protection mode in the mainboard configuration process of computer equipment;

responding to a mainboard configuration request, and realizing mainboard configuration of the computer equipment according to a mainboard configuration specification corresponding to the mainboard type identifier; or the like, or, alternatively,

responding to a mainboard configuration detection request, detecting that the mainboard type identifier is a target identifier, and detecting mainboard configuration information of the computer equipment according to a mainboard configuration specification corresponding to the target identifier.

Optionally, the method further includes:

and sending the write protection starting instruction to a microcontroller of the computer equipment, so that the microcontroller responds to the write protection starting instruction, executes one-time write protection operation aiming at the external interface memory, and writes the mainboard type identifier into the external interface memory.

In another aspect, the present application further provides an apparatus for implementing data protection, where the apparatus includes:

the reference adjusting module is used for acquiring a target working parameter, and adjusting the first working parameter of a first firmware storage space of the computer equipment to the target working parameter so as to enable a mainboard controller of the computer equipment to work in a hardware sequencing mode by switching to a software sequencing mode;

a write protection instruction receiving module, configured to receive a write protection start instruction sent by the motherboard controller in the software sequencing mode;

and the write protection execution module is used for responding to the write protection starting instruction and executing write protection operation of the second firmware storage space of the computer equipment.

the sequencing mode switching module is used for determining that a first working parameter of a first firmware storage space of the firmware of the computer equipment is a target working parameter and switching the hardware sequencing mode to the software sequencing mode to work;

a write-protection starting instruction obtaining module for obtaining a write-protection starting instruction for starting write-once protection operation;

and the write protection starting instruction sending module is used for sending the write protection starting instruction to the firmware so that the firmware responds to the write protection starting instruction and executes write protection operation aiming at a second firmware storage space of the firmware.

In yet another aspect, the present application further proposes a computer device, comprising:

a main board;

firmware and a motherboard controller disposed in the motherboard, wherein:

the firmware is used for loading and executing a pre-stored first program so as to realize the steps of the data protection realization method described from the perspective of the computer equipment firmware;

the mainboard controller is used for loading and executing a pre-stored second program so as to realize the steps of the data protection realization method described in the angle of the mainboard controller of the computer equipment.

Therefore, the application provides a method, an apparatus and a computer device for implementing data protection, in order to improve the safety and reliability of a second firmware storage space for storing important information in the computer device, and avoid that data stored in the second firmware storage space is changed and cleared after leaving the factory, an OTP mode is adopted to implement write protection of the data stored in the second firmware storage space, so that for a computer device whose motherboard controller operates in a hardware sorting mode, in order to solve the limitation of the platform sending SPI ROM instruction number to the motherboard controller, and reliably implement OTP operation of the second firmware storage space, the application proposes to switch the operating mode of the motherboard controller to a software sorting mode, specifically, a first operating parameter in a first firmware storage space of the computer device, namely a key parameter affecting the operation of the hardware sorting mode, the method comprises the steps of adjusting the parameters to be target working parameters, namely key parameters for ensuring the working of a software sorting mode, so that the mainboard controller is switched to work in the software sorting mode, and the computer equipment firmware can receive all write protection starting instructions for realizing OTP operation sent by the mainboard controller, so that the OTP operation on the storage space of the second firmware is executed by responding to the write protection starting instructions, the operations of changing and clearing data in the storage space of the second firmware after the computer leaves a factory are avoided, and the safety and reliability of the data in the storage space of the second firmware are improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.

Fig. 1 is a flow chart illustrating an alternative example of a data protection implementation method proposed in the present application;

FIG. 2 is a diagram illustrating a partition of a firmware storage space suitable for the data protection implementation method proposed in the present application;

FIG. 3 is a flow diagram illustrating yet another alternative example of a data protection implementation method presented herein;

FIG. 4 is a hardware diagram of a computer device for implementing the data protection implementation method proposed in the present application;

FIG. 5 is a flow chart diagram illustrating yet another alternative example of a data protection implementation method presented herein;

FIG. 6 is a flow chart illustrating yet another alternative example of a data protection implementation method proposed in the present application;

FIG. 7 is a flow chart diagram illustrating yet another alternative example of a data protection implementation method presented herein;

FIG. 8 is a diagram illustrating a hardware structure of a computer device for implementing the data protection implementation method proposed in the present application;

fig. 9 is a schematic structural diagram illustrating an alternative example of the data protection implementation apparatus proposed in the present application;

fig. 10 is a schematic structural diagram showing still another alternative example of the data protection implementing apparatus proposed by the present application;

fig. 11 is a schematic structural diagram illustrating yet another alternative example of the data protection implementing apparatus proposed in the present application;

fig. 12 is a schematic diagram illustrating an alternative structure of a computer device for implementing the data protection implementation method proposed in the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

It should be noted that, for convenience of description, only the portions related to the related invention are shown in the drawings. The embodiments and features of the embodiments in the present application may be combined with each other without conflict.

It should be understood that "system", "apparatus", "unit" and/or "module" as used herein is a method for distinguishing different components, elements, parts or assemblies at different levels. However, other words may be substituted by other expressions if they accomplish the same purpose.

As used in this application and the appended claims, the terms "a," "an," "the," and/or "the" are not intended to be inclusive in the singular, but rather are intended to be inclusive in the plural unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that steps and elements are included which are explicitly identified, that the steps and elements do not form an exclusive list, and that a method or apparatus may include other steps or elements. An element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.

In the description of the embodiments herein, "/" means "or" unless otherwise specified, for example, a/B may mean a or B; "and/or" herein is merely an association describing an associated object, and means that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present application, "a plurality" means two or more than two. The terms "first", "second" and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

Additionally, flow charts are used herein to illustrate operations performed by systems according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in the exact order in which they are performed. Rather, the various steps may be processed in reverse order or simultaneously. Meanwhile, other operations may be added to the processes, or a certain step or several steps of operations may be removed from the processes.

Referring to fig. 1, a schematic flow chart of an optional example of a data protection implementation method provided in the present application is shown, where the method may be applied to a computer device, such as a notebook computer, a desktop computer, and the like, and the present application does not limit a device type of the computer device, and the data protection implementation method provided in this embodiment may be specifically implemented by a firmware BIOS (basic input and Output System) of the computer device, as shown in fig. 1, and the data protection implementation method may include, but is not limited to, the following steps:

step S11, obtaining target working parameters, adjusting the first working parameters of the first firmware storage space of the computer equipment to the target working parameters, so that the mainboard controller of the computer equipment is switched from a hardware sorting mode to a software sorting mode to work;

in practical application of the application, the storage space of the firmware BIOS of the computer device can be divided into a first firmware storage space and a second firmware storage space, and some data which is more important for the computer device, such as some data which is not desired to be changed by a user at will, or some data which can affect the normal operation and safety of a computer device system, etc., are provided. For example, data of a very important area for starting up such as a RO (Read-Only) area of Coreboot and a boot area of uefi (unified Extensible Firmware interface), and some key data such as a special flag (identifier), an OA3 key of a Machine, an MTM (Machine Type Model) set in BIOS, if the information is modified after the computer device leaves a factory, adverse effects are often caused on user data, a usage mode and usage security of the computer device, so that the user cannot use the computer device normally and safely.

Therefore, the data listed above but not limited to the data listed above can be written into the second firmware storage space as the data to be protected, and before the computer device leaves the factory, the second firmware storage space is changed into a permanent read-only storage space, so that the data stored in the second firmware storage space cannot be tampered and deleted after leaving the factory, and the protection for the startup of the BIOS is enhanced.

It can be seen that the first firmware storage space configured in the present application is a read-write attribute, and the second firmware storage space is a read-only attribute, so that, in an application running process of the computer device, the computer device can respond to a data write request and a data read request for the first firmware storage space, but cannot respond to a data write request for the second firmware storage space, and can only respond to a data read request for the second firmware storage space. The method and the device do not limit the division mode of the firmware storage space of the computer device, namely the first firmware storage space and the second firmware storage space of the BIOS storage space.

For example, for an SPI ROM (serial peripheral Interface ROM) Flash chip supporting OTP (One Time Program, Write-once protection), such as the BIOS SPI ROM shown in fig. 2, before the computer device leaves the factory, the entire storage space of the BIOS SPI ROM may be divided into Read-Write Flash (i.e., a first firmware storage space having data Read-Write attribute) and Read-Only Flash (i.e., a second firmware storage space having data Read-Only attribute), the key information listed above but not limited thereto is written into the Read-Only Flash to be divided, and between leaves the factory, the part of the firmware storage space is changed into a permanent Read-Only area, so that the data stored in the Read-Only Flash cannot be rewritten or destroyed, thereby enhancing the protection of the user data, and satisfying the requirements of the computer device purchasers (e.g., individual users, regional or national units, government units, etc.) Enterprise organization, etc.) software and hardware security requirements for computer equipment.

Based on the above analysis, the present application may implement subsequent permanent protection of the second firmware storage space in a manner of writing a certain number of write protection start instructions into the computer device firmware storage space (e.g., the storage space of the BIOS SPI ROM) and performing OTP operation on the second firmware storage space, which is the problem of the prior art described in the background section. However, for a computer device using an Intel big core (i.e. an Intel big core) processor architecture, because a motherboard Controller (such as a Platform Controller Hub, PCH for short, integrated south bridge, which may also be referred to as a Platform Controller Hub) usually adopts a hardware sequencing manner to send instructions to a firmware storage space of the computer device, the manner can only send a limited number of instructions, and often cannot send all instructions for starting OTP operations to a BIOS spool, which cannot realize OTP operations to a second firmware storage space.

In order to further solve the above problem, the present application proposes to use a software sequencing mode (software sequencing mode) to complete transmission of all instructions for starting the OTP operation, so as to solve the technical problem that the computer device, using a hardware sequencing mode, has a limited number of instructions to be able to send to the BIOS SPI ROM, and cannot start the OTP operation on the second firmware storage space. The working principle of the computer device operating in a software sequencing or hardware sequencing mode is not described in detail in the application.

By combining the description of the invention concept of the present application, the present application can determine that the computer device works in a hardware sequencing mode and a software sequencing mode differently, that is, it is determined whether the computer device is a key parameter of the hardware sequencing mode or the software sequencing mode, and by changing the key parameter, switching between the two modes can be realized.

The key parameter may be determined through analysis to be a first working parameter of a first firmware storage space of the computer device, such as a state parameter in a Read-Write Flash in fig. 2 for implementing a register corresponding to a conventional CSM MRC cache event log, and the like.

Similarly, the application may also determine target operating parameters of the first firmware storage space, such as the target state parameters of the registers, when the computer device operates in a software sequencing mode. Thus, when it is necessary to execute an OTP operation on a second firmware storage space in the computer device, the PCH may send the target operating parameter to a computer device firmware (such as a BIOS), and specifically may send the target operating parameter to a BIOS SPI ROM, so that the firmware adjusts the first operating parameter of the first firmware storage space to the target operating parameter, that is, clears the first operating parameter, and writes the target operating parameter.

Step S12, receiving a write protection starting instruction sent by the mainboard controller in a software sorting mode;

as described above, for a firmware memory (e.g., a BIOS SPI ROM) hung on a main board controller PCH, OTP operation needs to be performed on a second firmware storage space (e.g., an RO region where Read-Only Flash is located) included in the firmware memory, the operating mode of the PCH is switched to a software sequencing mode according to the above-mentioned mode, and because the software sequencing mode operates, a core processor architecture platform of a computer device does not limit an SPI ROM instruction transmitted by the PCH, the PCH can transmit a write-protect start instruction for starting the OTP operation of the second firmware storage space of the computer device, that is, all SPI ROM instructions for implementing the OTP operation to the BIOS SPI ROM, so that the BIOS obtains all start instructions capable of starting the OTP operation on the RO region in the BIOS SPI ROM.

It should be noted that, regarding the implementation process of sending the SPI ROM instruction when the PCH is in the software sequencing mode, the implementation process may be determined by combining the working principle of the software sequencing mode, and details are not described in this application.

In addition, for computer devices of different models produced by different manufacturers, data stored in the second firmware storage space that needs to perform OTP operation may be different, and the number and content of write protection enable instructions for implementing OTP operation may also be different. In practical application of this embodiment, the BIOS may sequentially write the received write-protection start instructions into the status register, and a specific implementation process of this embodiment is not described in detail in this embodiment

In step S13, in response to the write-protect start instruction, a write-once protection operation for a second firmware storage space of the computer device is performed.

As described above, the process of starting the OTP operation is relatively complicated, and therefore, the number of the write-protection start instructions of this embodiment is plural, but the specific instruction number and content of the plural write-protection start instructions are not limited, and can be determined according to actual situations.

According to the above manner, after the PCH is in a software sequencing manner and a plurality of required write-protection start instructions are sent to the BIOS SPI ROM, the OTP operation for the second firmware storage space may be started in response to the plurality of write-protection start instructions, and a specific implementation process of the OTP operation is not described in detail in the present application.

The OTP is a memory type of the singlechip, which means one-time programmable, namely, after a program is burnt into the singlechip, the program cannot be changed and cleared again. Based on the principle, after the data to be protected of the computer equipment is determined, the one-time programming for the second firmware storage space, namely Read-Only Flash, is started and executed according to the mode, and the data to be protected and the program supporting the work of the Read-Only Flash are written into the Read-Only Flash, so that the subsequent change and removal of the data are avoided, and the safety of the stored data is improved.

In some embodiments, in order to protect the important data of the BIOS, an OTP register may be configured inside the Flash of the BIOS to indicate that the register may be programmed only once, and the programming of the register is completed before the computer device leaves the factory, so as to ensure that the stored data is not changed and cleared after leaving the factory. In order to protect the OTP register, a LOCK register may be provided, which has a similar working principle as the OTP register and can be programmed only once, and each bit of the LOCK register corresponds to an OTP register for locking the OTP register and cannot be written into the OTP register, so as to protect the data stored in the FLASH chip where the OTP register is located from being changed or erased.

Similarly, for other storage devices of the computer device, the OTP register and the LOCK register may also be deployed to protect the storage data thereof, and the specific implementation process is not described in detail in this application. In practical application, data and storage devices that need to perform OTP operation can be determined according to the needs of an operator and a client, and similar OTP operation implementation processes for each storage device can refer to the implementation process of performing OTP operation on Read-Only Flash of the BIOS SPI ROM described in this embodiment.

In summary, in order to improve the safety and reliability of the second firmware storage space for storing important information in the computer device, and avoid the data stored in the second firmware storage space from being changed and cleared after the computer device leaves the factory, the OTP mode is used to implement write protection of the data stored in the second firmware storage space, so that for a computer device whose motherboard controller operates in the hardware sorting mode, in order to solve the limitation of the platform sending the SPI ROM instruction number to the motherboard controller, and reliably implement the OTP operation of the second firmware storage space, the application proposes to switch the operating mode of the motherboard controller to the software sorting mode, and specifically, may adjust the first operating parameter in the first firmware storage space of the computer device, that is, the key parameter affecting the operation of the hardware sorting mode, to the target operating parameter, that is, the key parameter ensuring the operation of the software sorting mode, therefore, the mainboard controller is switched to work in a software sequencing mode, so that the firmware of the computer equipment can receive all write protection starting instructions sent by the mainboard controller to realize OTP operation, the OTP operation on the storage space of the second firmware is executed by responding to the write protection starting instructions, the operation of changing and clearing the data in the storage space of the second firmware after the computer leaves the factory is avoided, and the safety and reliability of the data in the storage space of the second firmware are improved.

Referring to fig. 3, which is a schematic flow chart of yet another optional example of the data protection implementation method proposed in the present application, this embodiment may be an optional detailed implementation of the data protection implementation method described in the foregoing embodiment, but is not limited to such a detailed implementation described in this embodiment, and as shown in fig. 3, the method may include:

step S31, obtaining a first target state parameter of a first register and a second target state parameter of a second register of a first firmware storage space of the computer device;

step S32, updating the first state parameter of the first register to a first target state parameter, and updating the second state parameter of the second register to a second target state parameter;

in conjunction with the above description of the two operation modes, namely hardware sequencing and software sequencing, of the motherboard controller of the computer device, the difference information of the two operation modes may be parameters in the status register, and therefore, both the first register and the second register of this embodiment may be status registers in Read-Write Flash, and are usually undefined registers, but the specific information of the two registers is not limited, and may be determined according to, but not limited to, the difference of the PCH operation modes, the requirement of the processor architecture platform of the computer device, and the like, and this embodiment is not described in detail here.

Based on this, when determining that the hardware sequencing mode is selected to affect the PCH operating mode according to the above-described modes of determining the first operating parameter and the target operating parameter, the respective state parameters of the first register and the second register are respectively and correspondingly marked as the first state parameter and the second state parameter, the specific contents of the two state parameters may be determined according to the operating principle of the hardware sequencing mode, and the specific contents of the two state parameters are not limited in the present application.

Similarly, the respective target state parameters of the first register and the second register may be determined according to factors such as a working principle of a software sequencing mode, and the like, and are sequentially recorded as the first target state parameter and the second target state parameter, after the first target state parameter and the second target state parameter are obtained by the firmware of the computer device, the original state parameter of the corresponding register in the storage space of the second firmware may be directly cleared, and the target state parameter is written into the corresponding register, so that the computer device meets a condition that the PCH operates in the software sequencing mode.

It should be noted that, regarding the implementation method for switching the motherboard controller of the computer device from the hardware sorting mode to the software sorting mode, including but not limited to the method described above in this embodiment, and for the firmware of the computer device of this application, it is necessary to use a chip supporting OTP operation, but it does not limit the type of the chip used, such as a FLASH chip. In addition, for the computer device implementing the data protection implementation method proposed in the present application, a main MAF architecture is usually adopted, and the firmware memory is only hung on the PCH, that is, the PCH implements command transmission to the BIOS SPI ROM, and details about the working principle of the MAF architecture and the PCH operation are not described in the present application.

Step S33, receiving a write protection instruction sent by a mainboard controller of the computer equipment in the working process of switching the mainboard controller from a hardware sorting mode to a software sorting mode;

in step S34, in response to the write-protect start instruction, a write-once protection operation for a second firmware storage space of the computer device is performed.

Regarding the implementation process of step S33 and step S34, reference may be made to the description of the corresponding parts in the above embodiments, and this embodiment is not described again.

To sum up, in this embodiment, data to be protected of the computer device is written into a second firmware storage space, such as the RO region after the BIOS SPI ROM divides the storage space, because the main controller PCH of the computer device operates in a hardware sequencing mode and cannot send a complete write protection start instruction for implementing the OTP operation to the BIOS SPI ROM, which may cause the BIOS to fail to implement the OTP operation on the RO region, the present embodiment proposes to adjust respective state parameters of two registers in the first firmware storage space, that is, the RW region, to target state parameters enabling the PCH to operate in a software sequencing mode, so that the PCH enters the software sequencing mode to operate and sends the complete write protection start instruction for implementing the OTP operation to the BIOS ROM, and thus, in response to these write protection start instructions, the OTP operation on the second firmware storage space can be reliably implemented, the permanent locking of the second firmware storage space is realized, and any writing operation on the data stored in the second firmware storage space can not be carried out subsequently, so that the safety and reliability of data storage are greatly improved, and the protection requirement of special customers on realizing specific function data of the computer equipment is met.

In practical application, in order to implement reliability of the OTP operation performed on the second firmware storage space, the present application may further perform write protection verification on the second firmware storage space, specifically referring to the schematic structural diagram of the computer device shown in fig. 4, the write protection verification module in the read-only region may be used to implement verification of the OTP operation on the RO region in the BIOS SPI ROM, so as to prompt and re-perform the OTP operation in time when the OTP operation fails.

Based on this, referring to a flow diagram of another optional example of the data protection implementation method proposed in the present application shown in fig. 5, the method may include:

step S51, obtaining target working parameters, adjusting the first working parameters of the first firmware storage space of the computer equipment to the target working parameters, so that the mainboard controller of the computer equipment is switched from a hardware sorting mode to a software sorting mode to work;

step S52, receiving a write protection starting instruction sent by the mainboard controller when the mainboard controller works in a software sequencing mode;

step S53, in response to the write-protection start instruction, performing an OTP operation for a second firmware memory space of the computer device;

for specific implementation processes of step S51 to step S53, reference may be made to the description of corresponding parts in the foregoing embodiments, and details are not described again in this embodiment.

Step S54, verifying whether the OTP operation on the second firmware memory space is successful, and if so, entering step S55; if not, returning to the step S51 to perform the write-once protection operation on the second firmware storage space again;

in the boot protection verification stage, in addition to implementing other protection verifications on the BIOS, the boot protection verification may be performed on the RO region of the BIOS SPI ROM, for example, whether the RO region can be written or not is verified, so as to determine whether the OTP operation previously performed on the RO region is successful or not.

After the verification, it is determined that the OTP operation performed on the second firmware storage space before is unsuccessful, the method may directly return to step S51 to re-perform the data protection implementation method, and perform the OTP operation on the second firmware storage space again, in a manner described in this embodiment.

In still other embodiments, in case of unsuccessful verification, the embodiment may also return to step S53, and execute a write-once protection operation on the second firmware storage space of the computer device in response to the write-protection start instruction again, so as to reduce the time taken by the PCH working mode switching or detection and the write-protection start instruction sending thereof, so as to improve the efficiency of the data protection implementation method.

In practical applications of the further embodiments, the number of times of failures that allow the execution of the OTP operation may be preset, so that the embodiment may count the number of times of execution of the OTP operation on the second firmware storage space, and detect whether the counted number of times of execution reaches the preset number of times of failures when it is verified that the OTP operation executed this time fails, if not, step S53 may be executed continuously, the OTP operation is executed again on the second firmware storage space, and if so, step S51 is returned again, and the data protection implementation method provided in the present application is executed again, so as to implement the OTP operation on the second firmware storage space.

It should be understood that in the process of returning to step S51 to re-execute the OTP operation, the operating parameter currently possessed by the first firmware storage space (i.e. the target status parameter adjusted last time) may be taken as the first operating parameter and updated to the re-acquired target status parameter.

In still other embodiments, in a case that the OTP operation is not successfully performed on the second firmware storage space for one or more times in the above manner, corresponding alarm information may be output to notify relevant detection personnel to repair the BIOS configuration and other software and hardware configurations of the computer device, so as to ensure that the OTP operation on the second firmware storage space is implemented, and a specific repair process is not described in detail in this application.

Step S55, restoring the current target working parameter of the first firmware storage space to the first working parameter, so that the mainboard controller switches from the software sorting mode to the hardware sorting mode to work;

as described above in relation to the computer device suitable for the data protection implementation method provided in the present application, in general, a motherboard controller of the computer device may operate in a hardware sequencing mode to meet data read-write requirements during an application running process of the computer device. Therefore, after determining that the OTP operation on the second firmware storage space is successfully completed, the application may restore the operating mode of the motherboard controller to a hardware sequencing mode.

Specifically, in combination with the description of the switching control process between the hardware sequencing mode and the software sequencing mode, the reverse process of step S51 may be adopted in this embodiment to implement switching the working mode of the PCH from the software sequencing mode to the hardware sequencing mode, and details of the specific implementation process are not repeated in this application.

In step S56, in response to the data reading request for the second firmware storage space, the requested data stored in the second firmware storage space is read.

Since the OTP operation has been executed on the second firmware storage space of the computer device in this application, after the PCH of the computer device is restored to the hardware sequencing mode, after a data reading instruction of any application to the second firmware storage space is responded, and a data reading request for the second firmware storage space is sent to the computer device firmware, the computer device firmware may read the requested data stored in the second firmware storage space in response to the data reading request, and details about a data reading process for the second firmware storage space are not described in this embodiment.

According to the above manner, the computer device firmware receives the data write request for the second firmware storage space, and since the second firmware storage space performs the OTP operation, it is prohibited to respond to the data write request, and the data write request may be directly ignored or deleted, and a notification message for prohibiting the write operation may also be fed back to the application initiating the data write request, which is not limited in this application.

In summary, for a computer device that operates in a hardware sorting manner on a processor architecture platform, under a condition that some important data need to be write-protected, before the computer device leaves a factory, the important data may be written into a second firmware storage space of the computer device, and then, a motherboard controller of the computer device is temporarily switched to a software sorting manner to operate by adjusting a first working parameter of a first firmware storage space to a target working parameter, so that the motherboard controller can send all write-protection start instructions required for implementing OTP operation to a firmware of the computer device, so that the firmware of the computer device responds to the write-protection start instruction, and can implement OTP operation on the second firmware storage space, that is, implement permanent write protection on data stored in the second firmware storage space.

In order to further improve reliability of the OTP operation, in the embodiment, in the process of starting the self-test of the computer device, reliability verification is performed on the OTP operation in the second firmware storage space, that is, whether the OTP operation on the second firmware storage space is successful is verified, if the OTP operation on the second firmware storage space is not successful, the OTP operation is performed again, so that the OTP operation on the second firmware storage space is successfully implemented, and then, the working mode of the computer device platform is restored to the original hardware sorting mode, so that application operation requirements of the computer device are met, and normal, safe and reliable operation of the computer device after leaving the factory is ensured.

In the following, the data protection implementation method will be described from the perspective of a motherboard controller of the computer device in conjunction with the implementation process of the data protection implementation method described above from the perspective of the firmware of the computer device.

Referring to fig. 6, a flow chart of yet another alternative example of the data protection implementation method proposed in the present application is shown, and as analyzed above, the method may be applied to a motherboard controller of the computer device, such as the PCH in fig. 4, and as shown in fig. 6, the data protection implementation method executed by the PCH may include, but is not limited to, the following steps:

step S61, determining that the first working parameter of the first firmware storage space of the computer device firmware is adjusted to the target working parameter, and switching from the hardware sorting mode to the software sorting mode to work;

for the implementation process of adjusting the first working parameter of the first firmware storage space to the target working parameter, reference may be made to the description of the above embodiment, which is not repeated in this embodiment.

In some embodiments, if the first operating parameter of the first firmware storage space that needs to be adjusted is the state parameter of each of the first register and the second register, after the BIOS of the computer device adjusts the state parameters of the two registers to the corresponding target state parameters, the adjustment result may be fed back to the motherboard controller, so that the motherboard controller determines that the first operating parameter of the first firmware storage space is adjusted to the target operating parameter, and then the motherboard controller will operate in a software sequencing manner.

The adjustment result fed back by the BIOS may be a sorting mode switching instruction, so that the motherboard controller may switch to a software sorting mode to work in response to the sorting mode switching instruction, but is not limited to the adjustment result content and the sorting mode switching implementation manner.

In the practical application of the application, the BIOS may not need to feed back the adjustment result, and the subsequent PCH operation reads the data in the BIOS spi ROM, and may directly operate according to the software sequencing mode according to the data content (mainly the target operating parameter).

Step S62, acquiring a write-protection start instruction for starting a write-once protection operation;

as can be known from the above description of the write-protection start instruction, for computer devices of different models and different manufacturers, the number and the content of the write-protection instructions for implementing OTP operations may be different, and the write-protection start instruction for starting OTP operations may be obtained according to the configuration content of the computer device itself.

In step S63, a write-protect start instruction is sent to the firmware, so that the firmware performs a write-once protection operation for the second firmware storage space of the firmware in response to the write-protect start instruction.

According to the application, data transmission between the motherboard controller PCH and the firmware BIOS can be realized according to a data communication protocol between the motherboard controller PCH and the firmware BIOS, that is, the motherboard controller PCH sends all acquired write protection start instructions for realizing OTP operation to the BIOS of the computer device, specifically, as shown in fig. 4, the write protection start instructions can be sent to the BIOS SPIROM to execute OTP operation on an RO region (i.e., a second firmware storage space) therein, so as to realize permanent write protection on stored data in the RO region.

In summary, when it is necessary to perform permanent write protection on important data stored in the second firmware storage space of the computer device, so as to prevent the data from being rewritten and erased after the computer device leaves the factory, and the normal and safe use of the computer device is affected, the embodiment may adopt a manner of adjusting the first operating parameter of the first firmware storage space to the target operating parameter, thereby switching the main board controller from the common hardware sequencing mode to the software sequencing mode to work, ensuring that all write protection starting instructions for realizing OTP operation are sent to the firmware of the computer equipment, the firmware responds to the write protection starting instruction, OTP operation on the storage space of the second firmware is executed, the stored data is locked permanently, and the data stored in the storage space of the second firmware cannot be written any more subsequently, so that the storage safety of the data is improved, and the running safety and reliability of the computer equipment are further ensured.

In practical applications, different selling objects or regions of a computer device may have special security requirements for the computer device, which makes the difference between the motherboards of the corresponding computer devices in hardware level, and during the assembly process of the computer device, in order to ensure that the assembled motherboards meet the corresponding security requirements, a motherboard type identifier, such as a Board ID, may be configured. At present, the product mainly provides a hardware-level Board ID to computer device system components, such as BIOS, EC, etc., by way of GPIO (General-purpose input/output) table. This approach tends to increase the complexity and operating cost of the motherboard.

In order to improve the above problem, the present application further proposes to perform OTP operation on the existing memory chip of the computer device, so as to implement irreversible multi-hardware-level Board ID configuration under the BOM (bill of material). Based on this, referring to fig. 7, which is a flowchart illustrating a further alternative example of the data protection implementation method proposed in the present application, this embodiment mainly describes how to implement the process of OTP encoding for motherboard type identification by using an existing memory chip of a computer device, as shown in fig. 7, the method may include:

step S71, reading the mainboard type identification recorded by the external interface memory;

the mainboard type identifier may be written into the external interface memory in a write-once protection manner during the mainboard configuration process of the computer device.

With reference to the schematic structural diagram shown in fig. 8, after determining that the motherboard type identifier Board ID of the motherboard should be installed on the computer device, the Board ID may be written into the SPI chip (i.e., the external interface memory) and subjected to OTP operation, thereby ensuring that the recorded Board ID is not changed and erased at will. For a specific implementation process of performing the OTP operation on the Board ID recorded by the SPI chip, reference may be made to the description of the corresponding part in the above embodiment, and this embodiment is not described again.

In some embodiments, after the computer device system is powered on, the production line may configure the Board ID to a microcontroller of the computer device, such as an EC or an eSIO (embedded microcontroller and legacy input output device) in fig. 8, according to a configuration requirement, by using a configuration tool, that is, a write protection initiation instruction for implementing the OTP operation is sent to the microprocessor, and in response to the write protection initiation instruction, the microprocessor executes the OTP operation for the external interface memory, that is, implements OTP encoding on the Board ID, where a specific implementation process is not described in detail.

Therefore, in order to implement the Board ID permanent storage, the PCH or other controller may send a write protection start instruction to a microcontroller of the computer device, so that the microcontroller responds to the write protection start instruction, executes a write-once protection operation for the external interface memory, and writes the motherboard type identifier into the external interface memory.

Before the OTP operation is executed, the BoardID required to be configured can be verified by the EC or the eSIO, if the verification fails, the BoardID can be considered as an error, corresponding prompt information is output to update the Board ID, if the verification succeeds, integrity verification can be carried out on the received write protection instruction, and after the verification passes, the OTP operation is executed again to permanently write the Board ID into the SPI chip.

In still other embodiments, the implementation process of permanently writing the Board ID into the SPI chip by using the OTP coding method may also be implemented by the PCH in fig. 8, and the implementation process is similar, and is not described in detail in this application.

Step S72, responding to the mainboard configuration request, and implementing the mainboard configuration of the computer equipment according to the mainboard configuration specification corresponding to the mainboard type identification;

and step S73, responding to the mainboard configuration detection request, detecting the mainboard type identifier as a target identifier, and detecting the mainboard configuration information of the computer equipment according to the mainboard configuration specification corresponding to the target identifier.

In practical application of this embodiment, after the Board ID write protection at the irreversible hardware level is implemented in the manner described above, the BIOS, Firmware, or software of the system may implement different requirements according to the input of the BoardID, and the specific requirement content is not described in detail in this application.

When the mainboard configuration request is received when the mainboard configuration request needs to be configured for the computer equipment, the mainboard configuration request can be responded, and the stored mainboard type identifier can be read so as to obtain the mainboard configuration specification corresponding to the mainboard type identifier, for example, what configuration the mainboard with the mainboard type identifier should have, thereby completing the mainboard configuration for the computer equipment according to the mainboard configuration specification and ensuring that the configured mainboard structure meets the corresponding requirements. The required mainboard configuration structure is often different for the mainboards with different mainboard type identifications, the mainboard configuration specifications corresponding to the different mainboard type identifications can be determined according to various requirements such as market requirements, customer requirements and the like, and specific contents are not limited.

After the mainboard configuration of the computer equipment is completed according to the above manner, the mainboard configuration detection request can be further responded to perform correctness verification on the mainboard configuration information of the computer equipment, a specific verification manner is not limited, and verification contents can still be determined according to a mainboard configuration specification corresponding to the mainboard type identifier of the computer equipment, which is not described in detail in the application.

In summary, in this embodiment, the existing memory chip of the computer device is utilized to implement write-once protection coding of the motherboard type identifier at the irreversible hardware level, the complexity and the operation cost of the motherboard hardware circuit are not increased, the storage security of the motherboard type identifier can be ensured, malicious modification and elimination can be avoided, and the motherboard configuration efficiency and reliability of the computer device can be improved according to the motherboard type identifier.

Referring to fig. 9, a schematic structural diagram of an alternative example of the data protection implementation apparatus proposed in the present application, which may be applied to firmware of a computer device, as shown in fig. 9, may include:

a reference adjusting module 91, configured to obtain a target working parameter, and adjust a first working parameter of a first firmware storage space of a computer device to the target working parameter, so that a motherboard controller of the computer device switches from a hardware sorting mode to a software sorting mode to work;

in one possible implementation, the reference adjusting module 91 may include:

the system comprises a target state parameter acquisition unit, a first storage unit and a second storage unit, wherein the target state parameter acquisition unit is used for acquiring a first target state parameter of a first register aiming at a first firmware storage space of the computer equipment and a second target state parameter of a second register;

and the state parameter adjusting unit is used for updating the first state parameter of the first register to the first target state parameter and updating the second state parameter of the second register to the second target state parameter.

A write protection instruction receiving module 92, configured to receive a write protection start instruction sent by the motherboard controller in the software sequencing mode;

and a write-protection executing module 93, configured to execute, in response to the write-protection starting instruction, a write-once protection operation for a second firmware storage space of the computer device.

In some embodiments, the data protection implementation apparatus provided in the present application may include:

the storage space dividing module is used for responding to a dividing request aiming at a firmware storage space of the computer equipment, and dividing the firmware storage space into a first firmware storage space and a second firmware storage space;

the data to be protected is written in the module, is used for obtaining the data to be protected, write said data to be protected into said second firmware memory space;

In still other embodiments, on the basis of the data protection implementation apparatus described in the foregoing embodiments, as shown in fig. 10, the apparatus may further include:

a verification module 94 for verifying whether a write-once protection operation for the second firmware storage space is successful;

a working parameter restoring module 95, configured to restore the current target working parameter of the first firmware storage space to the first working parameter when the verification result of the verifying module is yes, so that the motherboard controller switches from the software sorting mode to the hardware sorting mode to work;

and a data reading module 96, configured to read the requested data stored in the second firmware storage space in response to a data reading request for the second firmware storage space.

Referring to fig. 11, a schematic structural diagram of yet another alternative example of the data protection implementation apparatus proposed in the present application, the apparatus may be applied to a motherboard controller of a computer device, and as shown in fig. 11, the apparatus may include:

the sorting mode switching module 111 is configured to determine that a first working parameter of a first firmware storage space of the firmware of the computer device is a target working parameter, and switch the hardware sorting mode to a software sorting mode to work;

a write-protection start instruction obtaining module 112, configured to obtain a write-protection start instruction for starting a write-once protection operation;

a write-protect start instruction sending module 113, configured to send the write-protect start instruction to the firmware, so that the firmware, in response to the write-protect start instruction, executes a write-protect-once operation for a second firmware storage space of the firmware.

In some embodiments, the apparatus may further comprise:

the mainboard type identifier reading module is used for reading a mainboard type identifier recorded by an external interface memory, and the mainboard type identifier is written into the external interface memory by adopting a write-once protection mode in the mainboard configuration process of the computer equipment;

in one possible implementation, the apparatus may further include:

and the write protection starting instruction sending module is used for sending the write protection starting instruction to a microcontroller of the computer equipment so that the microcontroller responds to the write protection starting instruction, executes one-time write protection operation aiming at the external interface memory and writes the mainboard type identifier into the external interface memory.

The mainboard configuration module is used for responding to a mainboard configuration request and realizing mainboard configuration of the computer equipment according to a mainboard configuration specification corresponding to the mainboard type identifier; and/or the presence of a gas in the gas,

and the mainboard configuration detection module is used for responding to a mainboard configuration detection request, detecting that the mainboard type identifier is a target identifier, and detecting mainboard configuration information of the computer equipment according to a mainboard configuration specification corresponding to the target identifier.

It should be noted that, various modules, units, and the like in the embodiments of the foregoing apparatuses may be stored in the memory as program modules, and the processor executes the program modules stored in the memory to implement corresponding functions, and for the functions implemented by the program modules and their combinations and the achieved technical effects, reference may be made to the description of corresponding parts in the embodiments of the foregoing methods, which is not described in detail in this embodiment.

The present application further provides a storage medium, on which a computer program may be stored, where the computer program may be called and loaded by a processor to implement the steps of the data protection implementation method described in the foregoing embodiments.

Referring to fig. 12, in order to implement an optional structural diagram of a computer device for implementing the data protection implementation method provided in the present application, the computer device may include: a motherboard 121, and a firmware 122 and a motherboard controller 123 disposed in the motherboard 121, wherein:

the motherboard 121, also called a motherboard, a system board or a motherboard, is installed in the chassis and is one of the most basic and important components of the computer equipment. The motherboard 121 is generally a rectangular circuit board, and main circuit systems forming the computer device, such as BIOS chips, I/O control chips, keyboard and panel control switch interfaces, indicator light connectors, expansion slots, and dc power supply connectors for the motherboard and the plug-in card, are mounted thereon.

In practical applications, the manufacturing quality of the motherboard is high and low, which determines the stability of the hardware system. And the chip of the motherboard is usually a motherboard chipset, which determines the specification, performance and general function of the motherboard, which in turn affects the performance of the whole computer system. Therefore, when computer equipment is produced, the assembly of the mainboard chipset of the computer equipment can be realized according to the requirements of markets, special customers and the like, and the corresponding mainboard type identifier is configured, so that the quick detection and verification of the mainboard type can be realized in the following, and the specific implementation process can refer to the description of the corresponding part of the embodiment.

The firmware 122 may be a BIOS chip, which is fully called ROM-BIOS, and is abbreviated as ROM BIOS, and may provide a lowest-level most direct hardware control program for the computer device, and is a hub communicating between the software program and the hardware device, and is responsible for solving the immediate requirement of the hardware, and executing according to the operation requirement of the software on the hardware.

In the embodiment of the present application, in combination with the above description, the storage space, i.e., the BIOS SPI ROM, may be divided into two areas, i.e., the first firmware storage space (i.e., the RW area) and the second firmware storage space (i.e., the RO area), and after the BIOS important data is written into the RO area, the OTP operation is performed on the RO area to implement permanent write protection on the stored data in the RO area. It can be seen that the firmware 122 can load and execute the first program to implement the steps of the data protection implementation method described above from a firmware perspective.

The main board controller 123 may be the PCH, and as described above, the main board controller 123 may enter a software sequencing mode, send a complete write protection start instruction to the BIOS, and implement the OTP operation on the RO region in the BIOS, and as a result, the main board controller 123 may load and execute the second program to implement the steps of the data protection implementation method described above from the perspective of the main board controller, and the specific implementation process is not described in detail. Moreover, the present application does not describe in detail the functions of the PCH implemented in the computer device.

It should be understood that the structure of the computer device shown in fig. 12 is not limited to the computer device in the embodiment of the present application, and in practical applications, the computer device may include more or less components than those shown in fig. 12, or may combine some components, such as the microprocessor EC/eSIO and the SPI chip shown in fig. 8, and other input devices, output devices, etc., which are not listed herein.

Finally, it should be noted that, in the present specification, the embodiments are described in a progressive or parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The device and the computer equipment disclosed by the embodiment correspond to the method disclosed by the embodiment, so that the description is relatively simple, and the relevant points can be referred to the method part for description.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for implementing data protection, the method comprising:

2. The method of claim 1, prior to the performing a write-once protection operation for a second firmware storage space of the computer device, the method further comprising:

3. The method of claim 1, wherein obtaining the target operating parameter and adjusting the first operating parameter of the first firmware storage space of the computer device to the target operating parameter comprises:

4. The method of any of claims 1-3, further comprising:

5. A method for implementing data protection, the method comprising:

6. The method of claim 5, further comprising:

7. The method of claim 6, further comprising:

8. An apparatus for implementing data protection, the apparatus comprising:

9. An apparatus for implementing data protection, the apparatus comprising:

10. A computer device, the computer device comprising:

a main board;

firmware and a motherboard controller disposed in the motherboard, wherein:

the firmware is used for loading and executing a pre-stored first program to realize the steps of the data protection realization method according to claims 1-3;

the main board controller is used for loading and executing a pre-stored second program so as to implement the steps of the data protection implementation method according to any one of claims 4 to 7.