CN108519938B - Memory chip compatibility test method, system and test host - Google Patents
Memory chip compatibility test method, system and test host Download PDFInfo
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- CN108519938B CN108519938B CN201810332396.8A CN201810332396A CN108519938B CN 108519938 B CN108519938 B CN 108519938B CN 201810332396 A CN201810332396 A CN 201810332396A CN 108519938 B CN108519938 B CN 108519938B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2247—Verification or detection of system hardware configuration
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
Abstract
The application relates to a method and a system for testing compatibility of a memory chip and a test host. The method comprises the following steps: detecting whether the compatibility test of the current test chip is finished; if the test is finished, detecting whether all the memory chips mounted on the test board are tested completely; if not, sending a switching instruction to the test board, wherein the switching instruction is used for indicating the test board to disconnect the current test chip from the system to be tested, and connecting a memory chip to be tested on the test board as the test chip with the system to be tested; sending a test instruction to a tested system, wherein the test instruction is used for indicating the tested system to execute a test task of a compatibility test on a test chip; acquiring test data corresponding to the test chip; and returning to the step of detecting whether the compatibility test of the current test chip is finished or not until all the memory chips mounted on the test board are tested. The test chip can be automatically switched in the compatibility test, a plurality of memory chips can be tested in one test period, and the test efficiency is improved.
Description
Technical Field
The present application relates to the field of memory test technologies, and in particular, to a method and a system for testing compatibility of a memory chip, and a test host.
Background
With the development of information technology, memory chips are widely used as carriers for storing information, and various types of memory chips are produced according to different application requirements. After an application system is developed or designed, compatibility tests are usually performed on a plurality of different types of memory chips, so that corresponding checking and debugging can be performed according to test faults.
In a traditional test method, each independent test can only test one memory chip, and particularly when the compatibility test of a plurality of memory chips is faced, the chips need to be replaced and the test needs to be restarted by manual watching, so that the test efficiency is low.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method, a system and a host for testing compatibility of a memory chip, which can improve testing efficiency.
A method for testing compatibility of a memory chip, the method comprising:
detecting whether the compatibility test of the current test chip is finished;
if the test is finished, detecting whether all the memory chips mounted on the test board are tested completely;
if not, sending a switching instruction to the test board, wherein the switching instruction is used for indicating the test board to disconnect the current test chip from the system to be tested, and connecting a memory chip to be tested on the test board as a test chip with the system to be tested;
sending a test instruction to the tested system, wherein the test instruction is used for indicating the tested system to execute a test task of a compatibility test on the test chip;
acquiring test data corresponding to the test chip;
and returning to the step of detecting whether the compatibility test of the current test chip is finished or not until all the memory chips mounted on the test board are tested.
In one embodiment, the method further comprises the following steps:
acquiring input test content and test times;
and generating a test instruction according to the test content and the test times.
A test host comprising a memory and a processor, the memory storing a computer program that when executed by the processor performs the steps of:
detecting whether the compatibility test of the current test chip is finished;
if the test is finished, detecting whether all the memory chips mounted on the test board are tested completely;
if not, sending a switching instruction to the test board, wherein the switching instruction is used for indicating the test board to disconnect the current test chip from the system to be tested, and connecting a memory chip to be tested on the test board as a test chip with the system to be tested;
sending a test instruction to the tested system, wherein the test instruction is used for indicating the tested system to execute a test task of a compatibility test on the test chip;
acquiring test data corresponding to the test chip;
and returning to the step of detecting whether the compatibility test of the current test chip is finished or not until all the memory chips mounted on the test board are tested.
A memory chip compatibility testing system, the system comprising: the system comprises a test host, a tested system connected with the test host and a test board connected with the test host and the tested system, wherein,
the test host is used for sending a switching instruction to the test board and sending a test instruction to the tested system when detecting that the compatibility test of the current test chip is completed and the test board comprises a memory chip to be tested;
the test board comprises at least one memory chip, and is used for receiving the switching instruction, disconnecting the current test chip from the system to be tested according to the switching instruction, and connecting one memory chip to be tested on the test board as a test chip with the system to be tested;
and the tested system is used for receiving the test instruction sent by the test host, executing a test task of the compatibility test on the test chip according to the test instruction, and feeding back test data to the test host.
In one embodiment, the test board further comprises: an analog switch unit, a signal connector respectively connected with the analog switch unit and the tested system, and a controller respectively connected with the analog switch unit and the test host, wherein,
the controller is used for receiving a switching instruction sent by the test host, generating a corresponding control instruction according to the switching instruction and sending the control instruction to the analog switch unit;
the analog switch unit is used for receiving the control instruction, disconnecting the current test chip according to the control instruction and connecting a memory chip to be tested on the test board as a test chip;
the signal connector is used for connecting the system to be tested with the test chip through the analog switch unit so as to execute the test task in the test instruction.
In one embodiment, the test board further comprises: a power supply conversion unit connected with an input power supply, and a relay respectively connected with the power supply conversion unit, the controller and the system to be tested,
the power supply conversion unit is used for converting an input power supply into working power supplies of the test board and the system to be tested respectively;
the controller is also used for generating a power-off instruction and sending the power-off instruction to the relay when receiving the switching instruction, and generating a power supply instruction and sending the power supply instruction to the relay after a to-be-tested memory chip connected to the test board is used as a test chip;
the relay is used for being disconnected when the power-off instruction is received and being closed when the power supply instruction is received.
In one embodiment, the controller is further configured to detect whether the test board or the system under test is powered down, generate a power-on instruction if the power-off instruction is power-down, where the power-on instruction is used to instruct the power conversion unit to perform a power-on operation, detect whether a working power supply of the test board and the system under test is normal, and generate power supply normal information and send the power supply normal information to the test host if the power supply of the test board and the working power supply of the system under test are normal.
A method for testing compatibility of a memory chip, the method comprising:
the method comprises the steps that a test host detects whether compatibility test of a current test chip is finished, if yes, whether all memory chips mounted on a test board are finished or not is detected, and if not, a switching instruction is sent to the test board and used for indicating the test board to disconnect the current test chip from a system to be tested, and one memory chip to be tested on the test board is used as a test chip to be connected with the system to be tested;
the test board receives the switching instruction, disconnects the current test chip from the system to be tested according to the switching instruction, and connects a memory chip to be tested on the test board as a test chip with the system to be tested;
the test host sends a test instruction to the tested system, wherein the test instruction is used for indicating the tested system to execute a test task of a compatibility test on the test chip;
and the tested system receives the test instruction, executes a test task of the compatibility test on the test chip according to the test instruction, and feeds back test data to the test host.
In one embodiment, the step of receiving the switching instruction by the test board, disconnecting the current test chip from the system under test according to the switching instruction, and connecting a memory chip under test on the test board as a test chip to the system under test includes:
the controller receives the switching instruction, generates a corresponding control instruction according to the switching instruction and sends the control instruction to the analog switch unit;
and the analog switch unit receives the control instruction, disconnects the current test chip according to the control instruction, and connects a memory chip to be tested on the test board as the test chip.
In one embodiment, the method further comprises:
when the controller receives the switching instruction, a power-off instruction is generated and sent to the relay;
the relay executes disconnection operation according to the received power-off instruction;
the controller generates a corresponding control instruction according to the switching instruction and sends the control instruction to the analog switch unit;
the analog switch unit receives the control instruction, disconnects the current test chip according to the control instruction, and connects a memory chip to be tested on the test board as a test chip;
the controller generates a power supply instruction and sends the power supply instruction to the relay;
and the relay executes closing operation according to the received power supply instruction.
According to the memory chip compatibility test method, the memory chip compatibility test system and the test host, the compatibility test process of the current test chip is detected, when the test of the test chip is completed, a switching instruction for switching the test chip to the memory chip to be tested is generated to indicate that the memory chip to be tested is automatically controlled to be connected with the system to be tested according to the switching instruction, the memory chip to be tested connected with the system to be tested is used as the test chip, the test instruction is further sent to the system to be tested to test the compatibility of the test chip and the system to be tested, and test data are obtained. The test process does not need human intervention, and after the current test chip completes the test, the next memory chip to be tested is automatically switched to be connected with the system to be tested, so that the compatibility test of a plurality of memory chips can be realized in one independent test period, and the test efficiency is further improved.
Drawings
FIG. 1 is a diagram illustrating an exemplary embodiment of a system for testing compatibility of a memory chip;
FIG. 2 is a schematic diagram of a test board according to one embodiment;
FIG. 3 is a flow chart illustrating a method for testing compatibility of a memory chip according to an embodiment;
FIG. 4 is a flowchart illustrating the step of the controller performing the memory chip switch according to one embodiment;
FIG. 5 is a flowchart illustrating a method for testing compatibility of a memory chip according to an embodiment;
FIG. 6 is a flow chart illustrating a method for testing compatibility of a memory chip according to an embodiment;
FIG. 7 is a diagram of the internal structure of the test host in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In one embodiment, as shown in FIG. 1, a memory chip compatibility test system is provided. The test system comprises a test host 102, a system under test 104 and a test board 106, wherein the test host 102 is connected with the system under test 104 and the test board 106 respectively, and the system under test 104 is connected with the test board 106.
The test host 102 is an upper computer, and may specifically be a terminal device. Further, the terminal device may be, but is not limited to, various personal computers, notebook computers. The system under test 104 refers to a system that needs to test compatibility with different memory chips. Specifically, the System under test may be an SoC (System-on-a-Chip), for example, a newly developed SoC Chip, and it is required to verify whether the SoC Chip is compatible with a plurality of different memory chips, and in the compatibility verification process, the integrated Chip is the System under test. Test board 106 refers to a device that is composed of at least one memory chip that needs to be tested for compatibility with the current system under test. In one embodiment, the test board 106 may include more than one memory chip for compatibility testing. Specifically, the Memory chip may include one or more types of Memory chips with any one or more specifications, such as an EMMC (Embedded Multi Media Card), nand, sd (Secure Digital Memory Card), usb (Universal Serial Bus), tf (Trans-flash Memory), and the like, which may be specifically selected according to test requirements and is not limited herein.
In this embodiment, the test host 102 is configured to send a switch instruction to the test board and send a test instruction to the system under test when it is detected that the compatibility test of the current test chip is completed and the test board includes a memory chip to be tested.
The test chip refers to a memory chip currently executing a compatibility test. The memory chip to be tested refers to a memory chip which is not subjected to the compatibility test in the test board. The switching instruction is an instruction for instructing switching to the next memory chip to be tested. Specifically, the switching instruction may include an identifier of the current test chip and an identifier of the next memory chip to be tested that needs to be tested.
The test host is pre-configured with the identification of all the memory chips in the test board and the test sequence of all the memory chips for compatibility test. And determining the next memory chip to be tested according to the current test chip and the test sequence, and generating a switching instruction according to the test chip identifier and the next memory chip identifier to be tested to indicate the test board to disconnect the current test chip from the system to be tested and establish the next memory chip to be tested to be connected with the system to be tested.
The test board 106 is configured to receive the switching instruction, disconnect the current test chip from the system under test according to the switching instruction, and connect a memory chip to be tested on the test board as a test chip to the system under test.
Specifically, the test board 106 analyzes the switching instruction to obtain the current test chip identifier and the next memory chip identifier to be tested, disconnects the corresponding test chip from the system under test according to the current test chip identifier, and then connects the memory chip corresponding to the next memory chip identifier to be tested to the system under test, thereby realizing automatic switching of a plurality of memory chips in the memory chip compatibility test.
The system under test 104 is configured to receive a test instruction sent by the test host, execute a test task of a compatibility test on the test chip according to the test instruction, and feed back test data to the test host.
Test instructions refer to instructions that comprise a test task. Wherein the test tasks may be generated by test scripts pre-configured in the test host 102. Specifically, test scripts are written in advance by using a development tool Notepad + + in the test host, and the test scripts are stored in the system root directory. The test scripts may include, but are not limited to, the following three test scripts: run _ full _ disk _ seq _ write.sh script for full disk sequential write testing; sh script of run _ performance _ test used for performance read-write test; and an iorsd test script set containing a read-write aging test, a Standby test and a rebot test. Based on the test script, the compatibility test and the aging test of the memory chip can be realized. The test data is data generated when a test task is executed.
Specifically, when the system under test 104 receives a test instruction sent by the test host, the compatibility test is performed on the test chip connected to the system under test according to the test instruction, and the obtained test data is fed back to the test host. For example, when the test task is a performance read-write test, the system under test 104 performs read-write operation on the test chip connected to the test task, and the test data generated in the read-write test process of the memory chip is fed back to the test host 102 through the system under test. The test host 102 and the system under test 104 are in communication connection through a serial port.
In an embodiment, firmware carrying a test script is burned in the memory chip in advance, and when a test instruction is received, the test script corresponding to the test instruction is executed, and the test data is returned to the test host 102 through a serial port of the system under test 104.
According to the memory chip compatibility test system, the test host detects the compatibility test progress of the current test chip, when the test of the test chip is detected to be completed, a switching instruction for switching the test chip to the memory chip to be tested is generated, the memory chip to be tested is automatically controlled to be connected with the tested system according to the switching instruction, the memory chip to be tested connected with the tested system is used as the test chip, the test instruction is further sent to the tested system to test the compatibility of the test chip and the tested system, and test data are obtained. The test process does not need human intervention, and after the current test chip completes the test, the next memory chip to be tested is automatically switched to be connected with the system to be tested, so that the compatibility test of a plurality of memory chips can be realized in one independent test period, and the test efficiency is further improved.
In one embodiment, as shown in fig. 2, a schematic diagram of a test board 106 is shown, the test board includes: the test system comprises an analog switch unit 202, a signal connector 204 respectively connected with the analog switch unit 202 and the system under test 104, and a controller 206 respectively connected with the analog switch unit 202 and the test host 102. In addition, the test board 106 includes memory chips EMMC 1-EMMC 8 connected to the signal connector 204 through the analog switch unit 202.
The controller 206 is configured to receive a switching instruction sent by the test host, generate a corresponding control instruction according to the switching instruction, and send the control instruction to the analog switch unit.
The controller 206, which is a core control unit of the test board, directly controls the switching process of the memory chips. In an embodiment, the controller 206 is a single chip, and may specifically be a microcontroller of the model STM32F 103. The microcontroller has low power consumption and working maximum frequency of 72MHz, is provided with two I2C buses and three UART interfaces, and can meet the requirement of a memory chip compatibility test system. In addition, the program design of the microcontroller can be simplified by utilizing the packaged function library, and the development efficiency is improved.
Specifically, the controller 206 is connected to and communicates with the test host 102 via a serial port (the UART1 shown in FIG. 2). The test host 102 sends a switching instruction to the controller 206 through the serial UART1, and the controller 206 parses the received switching instruction, generates a corresponding control instruction according to the parsed content, and controls the on/off state in the analog switch unit 202 through the control instruction.
The analog switch unit 202 is configured to receive the control instruction, disconnect the current test chip according to the control instruction, and connect a memory chip to be tested on the test board as a test chip. The automatic switching of the memory chips is realized by controlling the on/off of the switches corresponding to the memory chips in the analog switch unit 202.
Specifically, the analog switch unit 202 may adopt a multiplexing analog switch chip with model number SN74CB3Q3251, and the maximum data bandwidth of the chip reaches 500MHz, which may meet the requirement of the signal transmission rate of the memory chip in the test process. Moreover, the chip supports signal switching of 1 to 8, each path of input control instruction can be controlled to be divided into 8 paths of signal output, and only one path of input control instruction can be switched at a time, so that switching of 8 storage chips can be realized. Based on the structure and knowledge of the SN74CB3Q3251, the chip includes, in addition to 8 pins connected to an external device (e.g., a memory chip), an active low-level enable pin OE and three control pins, and the combination of level signals of the three control pins can control 8 output pins, thereby implementing switching of 8 memory chips. In conjunction with the control principle of the SN74CB3Q3251 chip, the control instructions generated by the controller 206 include level signals of three control pins of the SN74CB3Q3251 chip.
Further, the number of analog switch chips in the analog switch unit 202 may be determined according to the number of signal terminals of the memory chip under test. Taking the example of an EMMC memory chip, the EMMC includes 11 signal paths, and thus, the analog switch unit 202 may include 11 multiplexing analog switch chips, each of which controls the switching of one EMMC signal terminal. In addition, in order to visually display the current test state, an analog switch chip can be added to switch the indicator lamps in different states for indicating the memory chip currently being tested.
The signal connector 204 is used for connecting the system under test 104 with the test chip through the analog switch unit 202 to execute the test task in the test instruction.
In the present embodiment, the signal transmission between the system under test 104 and the test chip can be realized through the signal connector 204 to perform the related operations in the compatibility test. Taking read-write test as an example, the test host 102 sends the test instruction to the system under test 104, and performs read-write operation on the test chip through the system under test 104 and the signal connector 204, and the test data is returned to the test host 102 through the signal connector 204 and the system under test 104.
In addition, the test board 106 can test the compatibility of different tested systems through the signal connector 204, thereby improving the utilization rate of the test board.
With continued reference to fig. 2, in one embodiment, the test board 106 further includes a power conversion unit 208 connected to the input power, and a relay 210 respectively connected to the power conversion unit 208, the controller 206, and the system under test 104.
The power conversion unit 208 is used for converting the input power into the working power of the test board 106 and the system under test 104. In this embodiment, the test board 106 and the system under test 104 are powered by a unified input power source, and the working power source is obtained by converting the input power source through the power conversion unit 208.
Specifically, the power conversion unit 208 includes a voltage conversion chip and a voltage stabilization chip, and the power conversion unit 208 obtains an input power through the power adapter, and obtains different output power through the conversion of the voltage conversion chip and the voltage stabilization chip, so as to supply power to different devices in the test system respectively. The power consumption of the whole test system is calculated, and a proper power adapter, a proper voltage conversion chip and a proper voltage stabilization chip are selected based on the calculation result so as to ensure the normal power supply of the system.
For example, the voltage conversion chip is a DCDC conversion chip with a model number of MT1482, and the voltage stabilization chip is an ASM1117 voltage stabilization chip. The input power supply is reduced in voltage through the MT1482 chip to obtain 5V output voltage, and then the 5V voltage output by the MT1482 chip is converted into 3.3V voltage through the four-way ASM1117 chip, and the voltage is respectively used as a working power supply for the memory chip, the analog switch unit 202, the inverter driving chip and the controller 206. In addition, the working power supply required by the system under test 104 can be obtained through the voltage conversion chip and/or the voltage stabilization chip, and the power is supplied to the system under test 104 through the relay 210.
In addition, the controller 206 is further configured to generate a power-off instruction and send the power-off instruction to the relay 210 when receiving the switching instruction, and generate a power-on instruction and send the power-on instruction to the relay 210 after connecting a memory chip to be tested on the test board as a test chip. The relay 210 is configured to open when receiving a power-off command and close when receiving a power-on command.
In the implementation, the switching of the memory chips is performed after the power failure, so that the fault caused by the switching of the memory chips during the operation of the system to be tested is avoided, the power supply is performed after the switching is completed, the test of the memory chips is ensured to be executed in the normal operation state of the system to be tested, and the test accuracy is ensured.
Further, the relay 210 is also used for switching the working power supply of the system to be tested. Different working power supplies may exist in different tested systems, and the switching of the working power supplies can be realized through the relay 210, so that the test board can be suitable for different tested systems.
In an embodiment, the controller 206 is further configured to detect whether the test board 106 or the system under test 104 is powered down, generate a power-on instruction if the power-off instruction is power-off, where the power-on instruction is used to instruct the power conversion unit to perform a power-on operation, detect whether the working power sources of the test board 106 and the system under test 104 are normal, and generate a power-supply-normal message and send the power-supply-normal message to the test host 102 if the power-supply-normal message is power-off.
When the power failure condition of the test board 106 or the system under test 104 is detected, a power-on instruction is generated to instruct the power conversion unit to perform the power-on operation again, and after the test board 106 and the system under test 104 are powered on again, power-supply normal information is generated and sent to the test host 102 to instruct the test host 102 to continue to execute the interrupted test operation.
According to the memory chip compatibility test system, the test host generates the switching instruction, the test board automatically controls the memory chip to be tested to be connected with the system to be tested according to the switching instruction, the memory chip to be tested connected with the system to be tested is used as the test chip, the test instruction is further sent to the system to be tested to test the compatibility of the test chip and the system to be tested, and test data are obtained. The test process does not need human intervention, and the compatibility test of the plurality of memory chips can be realized in one independent test period, so that the test efficiency is improved.
In an embodiment, as shown in fig. 3, a method for testing compatibility of a memory chip is provided, where the method is applied to a system for testing compatibility of a memory chip according to any embodiment, and includes the following steps:
and S302, the test host detects whether the compatibility test of the current test chip is finished, if so, detects whether all the memory chips mounted on the test board are finished, otherwise, sends a switching instruction to the test board, wherein the switching instruction is used for indicating the test board to disconnect the current test chip from the system to be tested, and connecting a memory chip to be tested on the test board as the test chip with the system to be tested.
The test chip refers to a memory chip currently executing a compatibility test. The memory chip to be tested refers to a memory chip which is not subjected to the compatibility test in the test board. The switching instruction is an instruction for instructing switching to the next memory chip to be tested. Specifically, the switching instruction may include an identifier of the current test chip and an identifier of the next memory chip to be tested that needs to be tested.
The test host is pre-configured with the identification of all the memory chips in the test board and the test sequence of all the memory chips for compatibility test. And determining the next memory chip to be tested according to the current test chip and the test sequence, and generating a switching instruction according to the test chip identifier and the next memory chip identifier to be tested to indicate the test board to disconnect the current test chip from the system to be tested and establish the next memory chip to be tested to be connected with the system to be tested.
S304, the test board receives the switching instruction, disconnects the current test chip from the system to be tested according to the switching instruction, and connects a memory chip to be tested on the test board as the test chip with the system to be tested.
Specifically, the test board analyzes the switching instruction to obtain a current test chip identifier and a next memory chip identifier to be tested, the corresponding test chip is disconnected from the tested system according to the current test chip identifier, and then the memory chip corresponding to the next memory chip identifier to be tested is connected to the tested system, so that automatic switching of the plurality of memory chips in the memory chip compatibility test is realized.
S306, the test host sends a test instruction to the tested system, and the test instruction is used for indicating the tested system to execute a test task of the compatibility test on the test chip.
When the test board completes the switching of the memory chips and takes a memory chip to be tested as a new test chip to be connected with the system to be tested, the test host sends a test instruction to the system to be tested so as to indicate the system to be tested to execute a test task of the compatibility test on the test chip.
Further, before the test host sends the test instruction to the system under test, the method further includes: and receiving a test chip switching completion instruction sent by the test board. So that the test operation is performed after the handover is completed.
S308, the tested system receives the test instruction, executes the test task of the compatibility test on the test chip according to the test instruction, and feeds back the test data to the test host.
Test instructions refer to instructions that comprise a test task. The test tasks can be generated by test scripts pre-configured in the test host. Specifically, test scripts are written in advance by using a development tool Notepad + + in the test host, and the test scripts are stored in the system root directory. The test scripts may include, but are not limited to, the following three test scripts: run _ full _ disk _ seq _ write.sh script for full disk sequential write testing; sh script of run _ performance _ test used for performance read-write test; and an iorsd test script set containing a read-write aging test, a Standby test and a rebot test. Based on the test script, the compatibility test and the aging test of the memory chip can be realized. The test data is data generated when a test task is executed.
Specifically, when the tested system receives a test instruction sent by the test host, the compatibility test is executed on a test chip connected with the tested system according to the test instruction, and the obtained test data is fed back to the test host. For example, when the test task is a performance read-write test, the read-write operation is performed on the test chip connected to the test task through the tested system, and test data generated in the read-write test process of the memory chip is fed back to the test host through the tested system. The test host computer is in communication connection with the tested system through a serial port.
According to the memory chip compatibility test method, the test host detects the compatibility test progress of the current test chip, when the test of the test chip is detected to be completed, a switching instruction for switching the test chip to the memory chip to be tested is generated, the memory chip to be tested is automatically controlled to be connected with the system to be tested according to the switching instruction, the memory chip to be tested connected with the system to be tested is used as the test chip, the test instruction is further sent to the system to be tested to test the compatibility of the test chip and the system to be tested, and test data are obtained. The test process does not need human intervention, and after the current test chip completes the test, the next memory chip to be tested is automatically switched to be connected with the system to be tested, so that the compatibility test of a plurality of memory chips can be realized in one independent test period, and the test efficiency is further improved.
In an embodiment, the test board receives the switching instruction, disconnects the current test chip from the system under test according to the switching instruction, and connects a memory chip under test on the test board as the test chip to the system under test, including: the controller receives the switching instruction, generates a corresponding control instruction according to the switching instruction and sends the control instruction to the analog switch unit; the analog switch unit receives the control instruction, disconnects the current test chip according to the control instruction, and connects a memory chip to be tested on the test board as the test chip.
Specifically, the controller is connected to and communicates with the test host via a serial port (e.g., UART1 shown in FIG. 2). The test host sends a switching instruction to the controller through the serial port UART1, the controller analyzes the received switching instruction, and generates a corresponding control instruction according to the analyzed content, so as to control the on-off state in the analog switch unit through the control instruction.
In one embodiment, the controller controls the switching of the memory chip in an interrupt processing manner. As shown in fig. 4, the method includes the following steps S402 to S410:
and starting a test flow after receiving a test starting instruction sent by the test host.
S402, the controller performs initialization configuration on the test board.
S404, initializing the serial port interrupt. The serial port is a serial port connected with a test host in the test board.
S406, detecting whether the serial port has interruption. And when a switching instruction sent by the test host is received through the serial port, entering a serial port interrupt service program.
S408, analyzing the switching instruction and controlling the test chip to switch.
Specifically, a corresponding control instruction is generated according to the switching instruction to control the analog switch unit to execute the switching operation of the memory chip.
S410, when the test chip completes the switching, a test chip switching completion instruction is returned to the test host. And when the test host receives the completion instruction, performing compatibility test on the current test chip.
In an embodiment, as shown in fig. 5, the method for testing compatibility of a memory chip further includes the following steps:
and S502, when the controller receives the switching instruction, generating a power-off instruction and sending the power-off instruction to the relay.
And S504, the relay executes the disconnection operation according to the received power-off instruction.
In this embodiment, the controller generates a power-off instruction and sends the power-off instruction to the relay when receiving the power-off instruction, and the relay is disconnected when receiving the power-off instruction, so that the memory chips are switched after the power-off, and the failure caused by switching the memory chips when the system to be tested operates is avoided.
And S506, the controller generates a corresponding control instruction according to the switching instruction and sends the control instruction to the analog switch unit.
And S508, the analog switch unit receives the control instruction, disconnects the current test chip according to the control instruction, and connects a memory chip to be tested on the test board as the test chip.
After the tested system is powered off, the controller generates a corresponding control instruction according to the switching instruction and sends the control instruction to the analog switch unit so as to indicate the analog switch unit to complete the switching of the test chip.
And S510, generating a power supply instruction by the controller and sending the power supply instruction to the relay.
And S512, the relay executes closing operation according to the received power supply instruction.
And after the switching is finished, power is supplied, so that the test of the memory chip is executed in the state that the tested system normally runs, and the test accuracy is ensured.
In an embodiment, as shown in fig. 6, a method for testing compatibility of a memory chip applied to a test host is also provided. Specifically, the internal structure of the test host may be as shown in fig. 7, and the test host includes a processor, a memory, a network interface, a display screen, and an input device, which are connected through a system bus. The method shown in FIG. 6 is performed by a processor of a test host. The method comprises the following steps:
s602, detecting whether the compatibility test of the current test chip is completed.
Specifically, whether the compatibility test of the current test chip is completed or not can be judged according to the currently acquired test data.
S604, if yes, detecting whether all the memory chips mounted on the test board are tested.
When the current test chip completes the compatibility test, whether all the memory chips mounted on the test board are tested completely is further detected, so that whether the test chips need to be switched is determined based on the detection result.
Specifically, whether the current test chip is the memory chip which executes the test last is judged according to the current test chip and a preset test sequence, if yes, all the memory chips mounted on the test board are tested, and if not, a switching instruction is generated according to the next memory chip to be tested.
And S606, if not, sending a switching instruction to the test board, wherein the switching instruction is used for indicating the test board to disconnect the current test chip from the system to be tested, and connecting a memory chip to be tested on the test board as the test chip to the system to be tested.
Specifically, the next memory chip to be tested is determined according to the current test chip and the test sequence, and then a switching instruction is generated according to the test chip identifier and the next memory chip identifier to be tested to indicate the test board to disconnect the current test chip from the system to be tested, and establish the connection between the next memory chip to be tested and the system to be tested.
S608, sending a test instruction to the tested system, wherein the test instruction is used for instructing the tested system to execute a test task of the compatibility test on the test chip.
When the test board completes the switching of the memory chips and takes a memory chip to be tested as a new test chip to be connected with the system to be tested, a test instruction is sent to the system to be tested so as to indicate the system to be tested to execute a test task of the compatibility test on the test chip.
Further, before sending the test instruction to the system under test, the method further includes: and receiving a test chip switching completion instruction sent by the test board. So that the test operation is performed after the handover is completed.
S610, test data corresponding to the test chip is obtained.
The test data is generated when the test task is executed. Specifically, when the tested system receives a test instruction sent by the test host, the compatibility test is executed on a test chip connected with the tested system according to the test instruction, the obtained test data is fed back to the test host, and the test host receives the test data so as to obtain a compatibility test result according to the test data.
In an embodiment, the method for testing compatibility of a memory chip applied to a test host further includes: acquiring input test content and test times; and generating a test instruction according to the test content and the test times.
Specifically, a user can pre-configure test contents and test times through a test interface displayed by the test host according to test requirements, and the test host generates corresponding test instructions according to the configured test contents and test data to instruct the tested system and the test chip to execute tests related to the test instructions.
Furthermore, the test interface displayed by the test host comprises a tested system configuration area, a test board configuration area, a data receiving area and a state display area. The tested system configuration area is used for configuring a serial port communicated with the tested system, and setting serial port numbers, baud rates and storage positions of printing information in the testing process. The test board configuration area is used for configuring a serial port for communicating with the test board, a current test chip, power control and a test scheme, and the test scheme specifically includes but is not limited to three test contents: full-disk sequential writing, performance testing and iorsd testing scripts. Furthermore, the single-test check box in the configuration area of the test board can be checked to retest a certain memory chip, and simultaneously, a required test case can be selected for testing. The data receiving area is used for displaying log information printed in the test process, the test process and the test data. The state display area is used for displaying the current test state of each memory chip, the test state comprises three types of test completion, test in progress, non-test and test failure, and specifically, color marks corresponding to each test state are displayed on the marks of each memory chip, for example, gray indicates non-test, yellow indicates in-test, green indicates test completion, and red indicates test failure, so that the test state of each memory chip can be conveniently and quickly known.
According to the memory chip compatibility test method, the compatibility test process of the current test chip is detected, when the test of the test chip is detected to be completed, a switching instruction for switching the test chip to the memory chip to be tested is generated, the memory chip to be tested is automatically controlled to be connected with the system to be tested according to the switching instruction, the memory chip to be tested connected with the system to be tested is used as the test chip, the test instruction is further sent to the system to be tested to test the compatibility of the test chip and the system to be tested, and test data are obtained. The test process does not need human intervention, and after the current test chip completes the test, the next memory chip to be tested is automatically switched to be connected with the system to be tested, so that the compatibility test of a plurality of memory chips can be realized in one independent test period, and the test efficiency is further improved.
It should be understood that although the various steps in the flow charts of fig. 2-6 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2-6 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
In addition, as in the test host architecture shown in FIG. 7, a processor is used to provide computational and control capabilities. The memory of the test host comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The network interface of the test host is used for communicating with an external terminal through network connection. The computer program is executed by a processor to implement a memory chip compatibility testing method. The display screen of the test host can be a liquid crystal display screen or an electronic ink display screen, and the input device of the test host can be a touch layer covered on the display screen, a key, a track ball or a touch pad arranged on the shell of the test host, an external keyboard, a touch pad or a mouse and the like.
It will be understood by those skilled in the art that the configuration shown in fig. 7 is a block diagram of only a portion of the configuration relevant to the present application, and does not constitute a limitation on the test host to which the present application is applied, and a particular test host may include more or less components than those shown in the drawings, or combine certain components, or have a different arrangement of components.
In one embodiment, a computer-readable storage medium is provided, having a computer program stored thereon, which when executed by a processor, performs the steps of:
detecting whether the compatibility test of the current test chip is finished;
if the test is finished, detecting whether all the memory chips mounted on the test board are tested completely;
if not, sending a switching instruction to the test board, wherein the switching instruction is used for indicating the test board to disconnect the current test chip from the system to be tested, and connecting a memory chip to be tested on the test board as the test chip with the system to be tested;
sending a test instruction to a tested system, wherein the test instruction is used for indicating the tested system to execute a test task of a compatibility test on a test chip;
acquiring test data corresponding to the test chip;
and returning to the step of detecting whether the compatibility test of the current test chip is finished or not until all the memory chips mounted on the test board are tested.
In one embodiment, the computer program when executed by the processor further performs the steps of:
acquiring input test content and test times;
and generating a test instruction according to the test content and the test times.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware related to instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above examples only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (6)
1. A memory chip compatibility test system, the system comprising: the system comprises a test host, a tested system connected with the test host and a test board connected with the test host and the tested system, wherein,
the test host is used for detecting whether the compatibility test of the current test chip is finished or not, if so, detecting whether all the memory chips mounted on the test board are finished or not, and when detecting that the compatibility test of the current test chip is finished and the test board comprises the memory chip to be tested, sending a switching instruction to the test board and sending a test instruction to the tested system;
the test board comprises at least one memory chip, and also comprises an analog switch unit, a signal connector respectively connected with the analog switch unit and the tested system, and a controller respectively connected with the analog switch unit and the test host, wherein the controller is used for receiving a switching instruction sent by the test host, generating a corresponding control instruction according to the switching instruction and sending the control instruction to the analog switch unit; the analog switch unit is used for receiving the control instruction, disconnecting the current test chip according to the control instruction and connecting a memory chip to be tested on the test board as a test chip; the signal connector is used for connecting the system to be tested with the test chip through the analog switch unit so as to execute the test task in the test instruction; the analog switch unit is a multiplexing analog switch chip, and the input of the multiplexing analog switch chip is connected with at most 8 storage chips;
and the tested system is used for receiving the test instruction sent by the test host, executing a test task of the compatibility test on the test chip according to the test instruction, and feeding back test data to the test host.
2. The system of claim 1, wherein the test host is further configured to obtain input test contents and test times; and generating a test instruction according to the test content and the test times.
3. The system of claim 2, wherein the test plate further comprises: a power supply conversion unit connected with an input power supply, and a relay respectively connected with the power supply conversion unit, the controller and the system to be tested,
the power supply conversion unit is used for converting an input power supply into working power supplies of the test board and the system to be tested respectively;
the controller is also used for generating a power-off instruction and sending the power-off instruction to the relay when receiving the switching instruction, and generating a power supply instruction and sending the power supply instruction to the relay after a to-be-tested memory chip connected to the test board is used as a test chip;
the relay is used for being disconnected when the power-off instruction is received and being closed when the power supply instruction is received.
4. The system of claim 3, wherein the controller is further configured to detect whether the test board or the system under test is powered down, and if so, generate a power-on instruction, where the power-on instruction is used to instruct the power conversion unit to perform a power-on operation, detect whether a working power source of the test board and the system under test is normal, and if so, generate a power-supply-normal message and send the power-supply-normal message to the test host.
5. A memory chip compatibility test method applied to the memory chip compatibility test system according to any one of claims 1 to 4, the method comprising:
the method comprises the steps that a test host detects whether compatibility test of a current test chip is finished, if yes, whether all memory chips mounted on a test board are finished or not is detected, and if not, a switching instruction is sent to the test board and used for indicating the test board to disconnect the current test chip from a system to be tested, and one memory chip to be tested on the test board is used as a test chip to be connected with the system to be tested;
the test board receives the switching instruction through the controller, generates a corresponding control instruction according to the switching instruction and sends the control instruction to the analog switch unit; receiving the control instruction through an analog switch unit, disconnecting the connection between the tested system and the current test chip according to the control instruction, and connecting a to-be-tested memory chip on the test board as a test chip to be connected with the tested system; disconnecting the current test chip from the system to be tested according to the switching instruction, and connecting a memory chip to be tested on the test board as a test chip with the system to be tested; the analog switch unit is a multiplexing analog switch chip, and the input of the multiplexing analog switch chip is connected with at most 8 storage chips;
the test host sends a test instruction to the tested system, wherein the test instruction is used for indicating the tested system to execute a test task of a compatibility test on the test chip;
and the tested system receives the test instruction, executes a test task of the compatibility test on the test chip according to the test instruction, and feeds back test data to the test host.
6. The method of claim 5, wherein the test board receiving the switch command, disconnecting the current test chip from the system under test according to the switch command, and connecting a memory chip under test on the test board as a test chip to the system under test comprises:
the controller receives the switching instruction, generates a corresponding control instruction according to the switching instruction and sends the control instruction to the analog switch unit;
and the analog switch unit receives the control instruction, disconnects the current test chip according to the control instruction, and connects a memory chip to be tested on the test board as the test chip.
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| CN109801671B (en) * | 2018-12-19 | 2021-02-12 | 珠海妙存科技有限公司 | Memory testing device and method compatible with eMMC protocol and SD protocol |
| CN110389870A (en) * | 2019-07-23 | 2019-10-29 | 深圳忆联信息系统有限公司 | A kind of Ink Die Flash test device and its test method |
| CN110824336A (en) * | 2019-10-10 | 2020-02-21 | 合肥格易集成电路有限公司 | Test system and test method |
| CN110888042B (en) * | 2019-12-09 | 2022-02-25 | 青岛歌尔微电子研究院有限公司 | Method and equipment for testing ASIC chip wafer and computer storage medium |
| CN112816851A (en) * | 2020-12-31 | 2021-05-18 | 上海移远通信技术股份有限公司 | Chip reliability testing device and method |
| CN115641906A (en) * | 2021-07-19 | 2023-01-24 | 长鑫存储技术有限公司 | Test method, test device and test system of storage device |
| US11893284B2 (en) | 2021-07-19 | 2024-02-06 | Changxin Memory Technologies, Inc. | Method, device and system for testing memory devices |
| CN113933684A (en) * | 2021-09-26 | 2022-01-14 | 武汉光谷信息光电子创新中心有限公司 | System and method for testing chip characteristics |
| CN116991710B (en) * | 2023-06-27 | 2024-04-09 | 珠海妙存科技有限公司 | Automatic test method and system, electronic equipment and storage medium thereof |
| CN116580758A (en) * | 2023-07-13 | 2023-08-11 | 联和存储科技(江苏)有限公司 | SD NAND test device, SD NAND test method, and computer-readable storage medium |
| CN117012258B (en) * | 2023-09-26 | 2024-01-02 | 合肥康芯威存储技术有限公司 | Analysis device, method and medium for storing chip state data |
| CN117608947B (en) * | 2024-01-24 | 2024-04-23 | 合肥康芯威存储技术有限公司 | Fault testing system and method for memory |
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