CN112816851A - Chip reliability testing device and method - Google Patents
Chip reliability testing device and method Download PDFInfo
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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Abstract
The embodiment of the invention relates to the technical field of chip testing, and discloses a chip reliability testing device, which comprises: the control module is used for receiving a detection trigger signal from the computing equipment and controlling the switching chip to be communicated with the test board in sequence; the communicated test board is used for receiving a networking detection instruction from the computing equipment through the switching chip and transmitting the networking detection instruction to the module to be detected; the module to be tested responds to the networking detection instruction and receives the networking signal through the networking interface, so that the module to be tested generates a test result according to the networking signal, and the test result is transmitted to the computing equipment through the communicated test board and the switching chip. The device and the method for testing the reliability of the chip can realize the automatic reliability test of the chip, know the test result in real time, reduce manual operation and improve the timeliness of the function test.
Description
Technical Field
The embodiment of the invention relates to the technical field of chip testing, in particular to a device and a method for testing chip reliability.
Background
Generally, the chip needs to be fully tested in the development process. The reliability life test of the chip is to put the module to be tested into professional equipment, such as an incubator, for testing. In the testing process, in order to test whether the module to be tested has quality problems, the module to be tested needs to be taken out from the incubator periodically according to requirements, function check is carried out, then the incubator is put into the incubator again, testing is carried out continuously, and the steps are repeated for multiple times until the reliability service life test is completed. Therefore, the test process is very complicated, the workload of a tester is large, and the time point of testing the sample to be tested which has a problem cannot be accurately controlled for a long time due to manual intervention.
Disclosure of Invention
The invention aims to provide a chip reliability testing device and method, which can realize automatic reliability testing of a chip, know a testing result in real time, reduce manual operation and improve timeliness of functional testing.
In order to solve the above technical problem, an embodiment of the present invention provides a device for testing chip reliability, including: control module, switch chip, a plurality of test panel that are used for connecting the module that awaits measuring, every test panel includes: a networking interface for receiving an external signal; the control module is connected with the switching chip, and the switching chip is connected with the plurality of test boards; the control module and the switching chip are also used for being respectively externally connected with computing equipment; the control module is used for receiving a detection trigger signal from the computing equipment and controlling the switching chip to be communicated with the test board in sequence; the communicated test board is used for receiving a networking detection instruction from the computing equipment through the switching chip and transmitting the networking detection instruction to the module to be detected; the module to be tested responds to the networking detection instruction, receives a networking signal through the networking interface, generates a test result according to the networking signal, and transmits the test result to the computing equipment through the communicated test board and the switching chip.
In addition, the switching chip comprises a plurality of switching signal output ports, and each testing board is provided with a networking signal transmission port; each switching signal output port is correspondingly connected with a networking signal transmission port of one test board.
Additionally, the networking signal transmission port includes: the network signal uploading port is used for receiving signals and the network signal issuing port is used for sending signals; the number of the switching chips is at least two, the switching signal output port of one switching chip is connected with the networking signal uploading port, and the switching signal output port of the other switching chip is connected with the networking signal issuing port.
In addition, the networking interface is used for receiving a V2X signal and a 5G signal.
In addition, the control module is specifically configured to sequentially communicate with the test boards in a cyclic detection manner, and the time for the control module to complete cyclic detection of all the test boards is less than the restart time of a single module to be tested.
In addition, each of the test boards further comprises: an RGMII signal interface; the chip reliability testing device further comprises: and the Ethernet communication module is connected with each RGMII signal interface.
In addition, each of the test boards further comprises: a working state output interface; the chip reliability testing device further comprises: and the status indicator light is connected with each working status output interface and is used for indicating the working status of the module to be tested.
The embodiment of the invention also provides a chip reliability testing method, which is applied to the chip reliability testing device under the preset testing condition; the chip reliability testing method comprises the following steps: the control module receives a detection trigger signal from the computing equipment and controls the switching chip to be communicated with the test board in sequence; the communicated test board receives a networking detection instruction from the computing equipment through the switching chip, the networking detection instruction is transmitted to the module to be tested, the module to be tested responds to the networking detection instruction, a networking signal is received by the networking interface, the module to be tested generates a test result according to the networking signal, and the test result is transmitted to the computing equipment through the communicated test board and the switching chip by the module to be tested.
In addition, the control module controls the switching chip to sequentially communicate with the test board, and the method comprises the following steps: the control module is sequentially communicated with the test boards in a circulating detection mode, and the time for the control module to circularly detect all the test boards is less than the restarting time of the test boards.
Additionally, the networking detection instructions include: V2X networking instructions and 5G networking instructions.
Compared with the prior art, the embodiment of the invention provides a chip reliability testing device, which comprises a control module, a switching chip and a plurality of testing boards for connecting to-be-tested modules, wherein each testing board comprises: a networking interface for receiving an external signal; the control module is connected with a switching chip, and the switching chip is connected with a plurality of test boards; the control module and the switching chip are also used for being respectively externally connected with computing equipment; the control module is used for receiving a detection trigger signal from the computing equipment and controlling the switching chip to be communicated with the test board in sequence; the communicated test board is used for receiving a networking detection instruction from the computing equipment through the switching chip and transmitting the networking detection instruction to the module to be detected; the module to be tested responds to the networking detection instruction, receives the networking signal through the networking interface, generates a test result according to the networking signal, and transmits the test result to the computing equipment through the communicated test board and the switching chip.
In the scheme, the test board connected with the module to be tested is used for testing the module to be tested, and the control module controls the switching chip to be communicated with each test board in sequence, so that the computing equipment can test the module to be tested connected with each communicated test board in sequence; the communicated test board and the switching chip can realize the information transmission between the module to be tested and the computing equipment, so that the module to be tested can receive the networking detection instruction of the computing equipment; the module to be tested responds to the networking detection instruction and receives the networking signal through the networking interface, generates a test result according to the networking signal and returns the test result to the computing equipment through the communicated test board and the switching chip, so that the automatic reliability test of the chip is realized, the test result can be known in real time through the computing equipment, the manual operation is reduced, and meanwhile, the timeliness of the function test is improved.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
FIG. 1 is a schematic structural diagram of a chip reliability testing apparatus according to a first embodiment of the present invention;
FIG. 2 is a flow chart of a chip reliability testing method according to a second embodiment of the present invention;
FIG. 3 is a schematic flow chart of a forced test of a module to be tested according to a second embodiment of the present invention;
fig. 4 is a flowchart illustrating a test procedure for three communication functions according to a second embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in order to provide a better understanding of the present application in various embodiments of the present invention. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
The first embodiment of the present invention relates to a chip reliability testing apparatus, and the core of the present embodiment is to include: control module, switch chip, a plurality of test panel that are used for connecting the module that awaits measuring, every test panel includes: a networking interface for receiving an external signal; the control module is connected with a switching chip, and the switching chip is connected with a plurality of test boards; the control module and the switching chip are also used for being respectively externally connected with computing equipment; the control module is used for receiving a detection trigger signal from the computing equipment and controlling the switching chip to be communicated with the test board in sequence; the communicated test board is used for receiving a networking detection instruction from the computing equipment through the switching chip and transmitting the networking detection instruction to the module to be detected; the module to be tested responds to the networking detection instruction, receives the networking signal through the networking interface, generates a test result according to the networking signal, and transmits the test result to the computing equipment through the communicated test board and the switching chip.
In the scheme, the test board connected with the module to be tested is used for testing the module to be tested, and the control module controls the switching chip to be communicated with each test board in sequence, so that the computing equipment can test the module to be tested connected with each communicated test board in sequence; the communicated test board and the switching chip can realize the information transmission between the module to be tested and the computing equipment, so that the module to be tested can receive the networking detection instruction of the computing equipment; the module to be tested responds to the networking detection instruction and receives the networking signal through the networking interface, generates a test result according to the networking signal and returns the test result to the computing equipment through the communicated test board and the switching chip, so that the automatic reliability test of the chip is realized, the test result can be known in real time through the computing equipment, the manual operation is reduced, and meanwhile, the timeliness of the function test is improved.
The following describes the implementation details of the chip reliability testing apparatus according to the present embodiment in detail, and the following is only provided for easy understanding and is not necessary to implement the present embodiment.
Fig. 1 is a schematic structural diagram of a chip reliability testing apparatus according to this embodiment:
the chip reliability testing device comprises: the device comprises a control module Controller, a switching chip SWITCH and a plurality of test boards TE-A for connecting the modules to be tested; the control module Controller is connected with a switching chip SWITCH which is connected with a plurality of test boards TE-A, and each test board TE-A comprises a networking interface for receiving external signals; the control module Controller and the SWITCH chip SWITCH are further configured to respectively connect to an external computing device (in the figure, the computing device is connected through the DB9_ Connector interface, and the computing device is not shown).
The test board TE-a can be understood as an interface module for carrying a module to be tested, and mainly implements information transfer between the module to be tested, the control module Controller, and the SWITCH chip SWITCH. The number of test boards TE-a can be set according to the data of the module to be tested required by the actual test, for example: in this embodiment, the number of the test boards TE-a is set to 10, and the reliability test can be performed on 10 modules to be tested at one time. When the reliability test is carried out, the whole chip reliability test device is placed in a preset test environment, and a control module Controller and a SWITCH chip SWITCH of the chip reliability test device are placed in the test environment and are respectively externally connected with computing equipment outside the test environment.
When the test is needed, a tester can operate on the computing device to send a detection trigger signal to the control module Controller, the control module Controller is used for receiving the detection trigger signal from the computing device, and then the switching chip SWITCH is controlled to be sequentially communicated with the test board TE-a for testing, and specifically, when the control module Controller is communicated with one test board TE-a, the test is performed on the module to be tested which is connected with the communicated test board TE-a.
In this embodiment, after the computing device is powered on, the AT command is sent to the module to be tested through the main serial port, so that the module to be tested is in a forced sending state (a high-load working state), and the module to be tested is maintained in the forced sending state during the testing process.
The process of testing a module under test connected to the test board TE-a to be connected is as follows: the communicated test board TE-A is used for receiving a networking detection instruction from the computing equipment through the switching chip SWITCH, transmitting the networking detection instruction to the module to be tested, receiving an external networking signal by the module to be tested through a networking interface in response to the networking detection instruction, generating a test result according to the networking signal, and transmitting the test result to the computing equipment through the communicated test board TE-A and the switching chip SWITCH; the computing equipment can judge whether the networking function of the module to be tested is normal or not according to the received test result. Therefore, automatic reliability test of the chip is realized, the test result can be known in real time through the computing equipment, manual operation is reduced, and timeliness of function test is improved.
Further, the control module Controller is specifically configured to sequentially communicate with the test board TE-a in a cyclic detection manner. As shown in fig. 1, there are 10 test boards TE-a (TE-a _1, TE-a _2, TE-a _3, to TE-a _10, respectively) in the chip reliability testing apparatus, that is, there are 10 modules to be tested. The computing device can only communicate with the module to be tested on one test board TE-a at the same time, and therefore, in this embodiment, the test boards TE-a need to be sequentially communicated in a cyclic detection switching manner, for example, after the computing device communicates with the module to be tested on the first test board TE-a normally, the control module Controller immediately switches to the second test board TE-a, and after the communication is normal, the control module Controller switches to the third test board TE-a, and so on, and the cycle is repeated, so as to monitor whether the modules to be tested on the 10 test boards TE-a can all communicate normally. It should be noted that the number of the test boards TE-a in fig. 1 is only for illustration, and in practical applications, the number of the test boards TE-a can be set according to the actual needs.
It should be noted that in this embodiment, if the computing device can receive the data content of the to-be-tested module, the to-be-tested module is considered to be able to work normally; otherwise, if the returned test result is wrong or has no data content, it can be determined that the module to be tested has a fault. When a certain module to be tested is detected to have a fault, the control module Controller continues to sequentially communicate with the test board TE-A for testing in a circulating detection mode, and if the computing equipment can receive the receiving and sending data content of the module to be tested in the subsequent testing process, the restarting fault of the module to be tested can be determined. If the computing device still does not receive the data receiving and sending content of the module to be tested in the subsequent limited test process, it can be confirmed that other faults occur in the module to be tested carried by the test board TE-a.
Preferably, the test board TE-a is used to detect the restart time of the module under test. In this embodiment, the time for the control module Controller to complete the cyclic detection of all the test boards TE-a is less than the restart time of a single module to be tested. Therefore, if a certain module to be tested is restarted in the test process, the module to be tested is not restarted yet, the control module Controller starts the next test, and the test board TE-a can be detected to be incapable of normal communication at this moment; if the module to be tested is detected to be capable of normally receiving and sending data and is in a normal state in the subsequent testing process, the reason that the module to be tested fails last time can be determined to be restart. At this time, the time of last fault is marked as the restart time of the module to be tested, so as to obtain the restart time of the test board TE-A.
Further, the SWITCH chip SWITCH includes a plurality of SWITCH signal output ports, and each test board TE-a has a networking signal transmission port; each switching signal output port is correspondingly connected with a networking signal transmission port of one test board TE-A.
As shown in fig. 1, the networking signal transmission port includes: the network signal uploading port UART _ RXD _ TE-A is used for receiving signals, and the network signal issuing port UART _ TXD _ TE-A is used for sending signals; the number of the switching chips SWITCH is at least two, wherein a switching signal output port of one switching chip SWITCH is connected with the networking signal uploading port UART _ RXD _ TE-A, and a switching signal output port of the other switching chip SWITCH is connected with the networking signal sending port UART _ TXD _ TE-A.
Specifically, the control module Controller is connected with at least two switching chips SWITCH, wherein all switching signal output ports of one switching chip SWITCH are connected with networking signal uploading ports UART _ RXD _ TE-A of all test boards TE-A, so that each test board TE-A receives signals from the computing equipment; all the switching signal output ports of the other switching chip SWITCH are connected with the networking signal issuing ports UART _ TXD _ TE-A of all the test boards TE-A, so that each test board TE-A sends signals from the module to be tested.
It is worth noting that the networking interface Antenna _ Connector is configured to receive the V2X signal and the 5G signal.
Specifically, the module under test in this embodiment has a 5G communication function (to implement connection between the module under test and the 5G network) and a V2X communication function (to implement connection between the module under test and the V2X network). The networking interface is embodied as an antenna.
When the two communication functions are tested, the computing equipment can respectively send different networking detection instructions to the module to be tested so as to respectively test the two communication functions of the module to be tested. For example: if the 5G communication function needs to be tested, the 5G communication function is connected with an external real network, the computing equipment firstly sends a section of data to the module to be tested, and the data is uploaded to the real network by the module to be tested; after uploading, downloading a section of data (5G signal) from the real network to the module to be tested, and returning the 5G communication result to the computing equipment by the module to be tested, so that the testing of the computing equipment on the 5G communication function of the module to be tested is realized. The test of the V2X communication function by the computing device is substantially the same as the 5G communication function, and is not described in detail in this embodiment. The computing equipment can judge whether the 5G communication function and the V2X communication function of the module to be tested are normal or not according to the returned test result. It should be noted that, in practical applications, the two communication functions are not tested simultaneously, but are tested separately.
It should be noted that, if the computing device finds that the V2X communication function is normal but the 5G communication function fails during the test, it can be determined that the 5G offline condition occurs in the module to be tested; if the 5G communication function is normal and the V2X communication function is failed, the V2X offline condition of the module to be tested can be confirmed.
It should be noted that when the 5G communication function is used, a USIM card needs to be inserted into the USIM _ Connector to perform the 5G communication.
Further, each test board TE-a further comprises: RGMII signal interface RGMII; the chip reliability testing device further comprises: an Ethernet communication module Ethernet PHY connected to each RGMII signal interface RGMII.
Specifically, the module under test in this embodiment has an Ethernet communication function, and the test board TE-a leads out an Ethernet communication function interface of the module under test, i.e., the RGMII signal interface RGMII, and performs data communication with the Ethernet communication module Ethernet _ PHY through the RGMII signal interface RGMII, specifically, RGMII _ MDIO _ TE-a _1 is connected with RGMII _ MDIO, RGMII _ RXD _ TE-a _1 is connected with RGMII _ TXD, and RGMII _ TXD _ TE-a _1 is connected with RGMII _ RXD.
It should be noted that, when testing the Ethernet communication function of the module under test, the router may be used to make the computing device and the Ethernet _ PHY of the Ethernet communication module in the same lan, and the computing device and each Ethernet _ PHY of the Ethernet communication modules sequentially transmit data to each other, so as to detect whether the Ethernet communication function of the module under test connected to the Ethernet _ PHY of the Ethernet communication module is normal.
Further, each test board TE-a further comprises: a working state output interface STATUS; the chip reliability testing device further comprises: and the STATUS indicator lamp is connected with each working STATUS output interface STATUS and is used for indicating the working STATUS of the module to be tested. Therefore, the working state of the module to be tested can be visually observed through the state indicating lamp.
Specifically, the control module Controller mainly uses a plurality of GPIO ports to connect the switching device, specifically, as shown in fig. 1, 6 GPIO ports are connected to a switching chip SWITCH of 10-to-1 switching. The test board TE-a further comprises: the power interface PWRKEY, the RESET SWITCH interface RESET and the control module Controller are respectively connected with the power interface PWRKEY and the RESET SWITCH interface RESET through a switching chip SWITCH. The test board TE-a further comprises: (network STATUS) indicates the interface NET _ STATUS, the debug interface circuit test point DBG _ UART, and the USB interface USB Connector.
The control module Controller also includes: the power interface PWRKEY, the RESET switch interface RESET, and the control module Controller communicate with the computing device through the two control signal transmission ports UART _ TXD _ C and UART _ TXD _ C.
Compared with the prior art, the embodiment of the invention provides a chip reliability testing device, which is characterized in that a testing board TE-A connected with a module to be tested is used for testing the module to be tested, and a control module Controller controls a switching chip SWITCH to be sequentially communicated with the testing boards TE-A, so that a computing device can sequentially test the module to be tested connected with each communicated testing board TE-A; the communicated test board TE-A and the switching chip SWITCH can realize the information transmission between the module to be tested and the computing equipment, so that the module to be tested can receive the networking detection instruction of the computing equipment; the module to be tested responds to the networking detection instruction, receives an external networking signal through the networking interface, generates a test result according to the networking signal, and returns the test result to the computing equipment through the communicated test board TE-A and the switching chip SWITCH, so that the automatic reliability test of the chip is realized, the test result can be known in real time through the computing equipment, the manual operation is reduced, and meanwhile, the timeliness of the function test is improved.
A second embodiment of the present invention relates to a chip reliability testing method, and the chip reliability testing method in this embodiment is applied to the chip reliability testing apparatus in the above-described embodiment.
Fig. 2 shows a schematic flow chart of the chip reliability testing method, which specifically includes:
step 101: the control module receives a detection trigger signal from the computing equipment and controls the switching chip to be communicated with the test board in sequence.
Specifically, when testing is needed, a tester can operate on the computing device to send a detection trigger signal to the control module, the control module is used for receiving the detection trigger signal from the computing device, then the control switching chip is sequentially communicated with the test boards for testing, and specifically, when the control module is communicated with one test board, the control module tests a module to be tested connected with the communicated test board.
Further, the control module control switches the chip and communicates the survey test panel in proper order, includes: the control module is sequentially communicated with the test board in a circulating detection mode.
Specifically, the computing device can only communicate with one test board at the same time, and therefore, in this embodiment, the test boards need to be sequentially communicated in a cyclic detection switching manner, for example, after the computing device communicates with the module to be tested on the first test board normally, the control module immediately switches to the second test board, and after the communication is normal, switches to the third test board, and so on, and repeats cyclically, thereby monitoring whether the modules to be tested on 10 test boards can all communicate normally.
It should be noted that in this embodiment, if the computing device can receive the data content of the to-be-tested module, the to-be-tested module is considered to be able to work normally; otherwise, if the returned test result is wrong or has no data content, it can be determined that the module to be tested has a fault. When a certain module to be tested is detected to have a fault, the control module continues to be sequentially communicated with the test board for testing in a circulating detection mode, and if the computing equipment can receive the data receiving and sending contents of the module to be tested in the subsequent test process, the restarting fault of the module to be tested can be determined. If the computing equipment still does not receive the transceiving data content of the module to be tested in the subsequent limited test process, the module to be tested carried by the test board can be confirmed to have other faults.
Preferably, the time for the control module to complete the cyclic detection of all the test boards is less than the restart time of the module to be tested. In order to further accurately detect the restarting time of the module to be tested. In this embodiment, the time for the control module to complete the cyclic detection of all the test boards is less than the restart time of a single module to be tested. Therefore, if a certain module to be tested is restarted in the test process, the module to be tested is not restarted yet, the control module starts the next round of test, and the situation that the module to be tested cannot normally communicate can be detected; if the module to be tested is detected to be capable of normally receiving and sending data and is in a normal state in the subsequent testing process, the reason that the module to be tested fails last time can be determined to be restart. At this time, the time of last fault is marked as the restart time of the module to be tested, so that the restart time of the test board is obtained.
Step 102: the connected test board receives the networking detection instruction from the computing equipment through the switching chip.
Step 103: and transmitting the networking detection instruction to the module to be tested, enabling the module to be tested to respond to the networking detection instruction, receiving the networking signal by using the networking interface, enabling the module to be tested to generate a test result according to the networking signal, and transmitting the test result to the computing equipment by the module to be tested through the communicated test board and the switching chip.
Specifically, in the above step 102 and step 103, the computing device may determine whether the networking function of the module to be tested is normal according to the received test result, so as to implement an automatic reliability test of the chip, and the computing device may know the test result in real time, thereby reducing manual operations and improving timeliness of the function test.
In some embodiments, before testing the 5G, V2X and the ethernet communication function of the module under test, the test mode needs to be tested in a strong state.
As shown in fig. 3, a specific process of testing the to-be-tested mode in the strong-hair state in this embodiment includes:
step S11: and powering on the chip reliability testing device, and sequentially powering on the modules to be tested.
Step S12: and judging whether the status indicator lamp of each test board is lightened or not. If the brightness is changed, the step S13 is performed (the computing device switches the chip and the test board to sequentially open the strong hair mode of the module to be tested, so that the module to be tested is kept in a strong hair state within a set time); if the light is not turned on, the routine proceeds to step S14 (power supply failure cause detection). The process of step S14 is completed, and after the power failure is cleared, the process returns to step S11 to power on again.
After step S13, step S15 is performed: and judging whether the two parameters of the temperature and the current consumption of the module to be tested reach set values or not when the module to be tested is maintained in the strong state. If the set value is reached, the process proceeds to step S16 (end forced state, shutdown). If the setting value is not reached, the routine proceeds to step S17 (determination of forced failure and return of the result to the computing device). And after the result of the step S17 is returned to the computing equipment, the staff finds out the reason of the forced transmission failure according to the returned result, and returns to the step S13 to enable the module to be tested to be in the forced transmission state again.
In this embodiment, the module to be tested has a 5G communication function (to realize the connection between the module to be tested and the 5G network), a V2X communication function (to realize the connection between the module to be tested and the V2X network), and an ethernet communication function. The specific test process of three communication functions is shown in fig. 4, and includes:
step S21: and powering on the chip reliability testing device, and sequentially powering on the modules to be tested.
Step S22: and judging whether the status indicator lamp of each test board is lightened or not. If the brightness is changed, the process goes to step S23 (the control module controls to sequentially and cyclically open the serial port of the module to be tested, so that the module to be tested communicates with the computing device). If the light is not turned on, the routine proceeds to step S24 (power supply failure cause detection). The process of step S24 is completed, and after the power failure is cleared, the process returns to step S21 to power on again.
After step S23, step S25 is performed: and judging whether the module to be tested can normally communicate with the computing equipment. If normal communication is possible, the step S26 is entered (V2X function test, in which the computing equipment sends AT command to the module to be tested, and the module to be tested returns test result to the computing equipment); if normal communication is not possible, the flow proceeds to step S27 (test failure is determined and the failure cause is found) and step S27 completes the process, and after the failure cause is eliminated, the flow returns to step S23 to re-perform the communication test.
After completion of step S26, the flow proceeds to step S28: the module to be tested respectively uploads and downloads data by using the 5G network card and the external network, the control module calculates the data and time, and returns the result to the calculation equipment.
Specifically, in the step S26 and the step S28, if the 5G communication function needs to be tested, the computing device sends a 5G networking instruction to the module to be tested, the module to be tested starts the 5G communication function to be connected with the external real network, the computing device first sends a piece of data to the module to be tested, and the data is uploaded to the real network by the module to be tested; after uploading, downloading a section of data (5G signal) from the real network to the module to be tested, and returning the 5G communication result to the computing equipment by the module to be tested, so that the testing of the computing equipment on the 5G communication function of the module to be tested is realized.
The test of the V2X communication function by the computing equipment is the same as the test of the 5G communication function, except that the networking detection command is changed into a V2X networking command, and the returned networking signal is changed into a V2X signal. This embodiment will not be described in detail.
If the computing equipment finds that the V2X communication function is normal but the 5G communication function is failed during testing, the 5G offline condition of the module to be tested can be confirmed; if the 5G communication function is normal and the V2X communication function is failed, the V2X offline condition of the module to be tested can be confirmed.
After completion of step S28, the flow proceeds to step S29: and the router is utilized to enable the computing equipment and the module to be tested to be positioned under the same local area network, so that data transmission between the computing equipment and the module to be tested is realized.
The testing process of the Ethernet communication function is as follows: when testing the Ethernet communication function of the module to be tested, the router can be used to make the computing device and the Ethernet _ PHY of the Ethernet communication module in the same lan, and the computing device and each Ethernet _ PHY of the Ethernet communication modules sequentially transmit data to each other, so as to detect whether the Ethernet communication function of the module to be tested connected to the Ethernet _ PHY of the Ethernet communication module is normal.
After step S29 is completed, all communication functions are tested, and step S30 is performed to turn off all modules to be tested and the chip reliability testing apparatus.
It should be noted that, in fig. 4, the test sequence of the three communication functions is defined as: V2X communication test, 5G communication test, and ethernet communication test, but it should be understood that in practical application, the test sequence of the three communication functions can be set as required, and the test sequence of the three communication functions shown in fig. 4 does not limit the present embodiment.
Compared with the prior art, the embodiment of the invention provides a chip reliability testing method, wherein a control module receives a detection trigger signal from computing equipment and controls a switching chip to be communicated with a testing board in sequence; the communicated test board receives a networking detection instruction from the computing equipment through the switching chip, the networking detection instruction is transmitted to the module to be tested, the module to be tested responds to the networking detection instruction and receives a networking signal through the networking interface, the module to be tested generates a test result according to the networking signal, the test result is transmitted to the computing equipment through the communicated test board and the switching chip, and the computing equipment can judge whether the networking function of the module to be tested is normal or not according to the received test result, so that the automatic reliability test of the chip is realized, the test result can be known in real time through the computing equipment, the manual operation is reduced, and meanwhile, the timeliness of the function test is improved.
The steps of the above methods are divided for clarity, and the implementation may be combined into one step or split some steps, and the steps are divided into multiple steps, so long as the same logical relationship is included, which are all within the protection scope of the present patent; it is within the scope of the patent to add insignificant modifications to the algorithms or processes or to introduce insignificant design changes to the core design without changing the algorithms or processes.
It is to be understood that this embodiment is a method embodiment related to the first embodiment, and that this embodiment can be implemented in cooperation with the first embodiment. The related technical details mentioned in the first embodiment are still valid in this embodiment, and are not described herein again in order to reduce repetition. Accordingly, the related-art details mentioned in the present embodiment can also be applied to the first embodiment.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (10)
1. A chip reliability testing device is characterized by comprising: control module, switch chip, a plurality of test panel that are used for connecting the module that awaits measuring, every test panel includes: a networking interface for receiving an external signal;
the control module is connected with the switching chip, and the switching chip is connected with the plurality of test boards; the control module and the switching chip are also used for being respectively externally connected with computing equipment;
the control module is used for receiving a detection trigger signal from the computing equipment and controlling the switching chip to be communicated with the test board in sequence;
the communicated test board is used for receiving a networking detection instruction from the computing equipment through the switching chip and transmitting the networking detection instruction to the module to be detected;
the module to be tested responds to the networking detection instruction, receives a networking signal through the networking interface, generates a test result according to the networking signal, and transmits the test result to the computing equipment through the communicated test board and the switching chip.
2. The device for testing the reliability of chips according to claim 1, wherein the switching chip comprises a plurality of switching signal output ports, each of the test boards has a networking signal transmission port;
each switching signal output port is correspondingly connected with a networking signal transmission port of one test board.
3. The chip reliability testing device according to claim 2, wherein the networking signal transmission port comprises: the network signal uploading port is used for receiving signals and the network signal issuing port is used for sending signals;
the number of the switching chips is at least two, the switching signal output port of one switching chip is connected with the networking signal uploading port, and the switching signal output port of the other switching chip is connected with the networking signal issuing port.
4. The chip reliability testing device according to claim 1, wherein the networking interface is configured to receive a V2X signal and a 5G signal.
5. The device for testing chip reliability according to claim 1, wherein the control module is specifically configured to sequentially communicate with the test boards through a cyclic detection manner, and a time for the control module to complete cyclic detection of all the test boards is shorter than a restart time of a single module under test.
6. The chip reliability test device according to any one of claims 1 to 5, wherein each of the test boards further comprises: an RGMII signal interface;
the chip reliability testing device further comprises: and the Ethernet communication module is connected with each RGMII signal interface.
7. The chip reliability test device according to any one of claims 1 to 5, wherein each of the test boards further comprises: a working state output interface;
the chip reliability testing device further comprises: and the status indicator light is connected with each working status output interface and is used for indicating the working status of the module to be tested.
8. A chip reliability test method, characterized by being applied to the chip reliability test apparatus of any one of the above claims 1 to 7 under a preset test condition; the chip reliability testing method comprises the following steps:
the control module receives a detection trigger signal from the computing equipment and controls the switching chip to be communicated with the test board in sequence;
the communicated test board receives a networking detection instruction from the computing equipment through the switching chip, the networking detection instruction is transmitted to the module to be tested, the module to be tested responds to the networking detection instruction, a networking signal is received by the networking interface, the module to be tested generates a test result according to the networking signal, and the test result is transmitted to the computing equipment through the communicated test board and the switching chip by the module to be tested.
9. The method for testing the reliability of the chip according to claim 8, wherein the controlling module controls the switching chip to sequentially communicate with the testing board, comprising:
the control module is sequentially communicated with the test boards in a circulating detection mode, and the time for the control module to circularly detect all the test boards is shorter than the restarting time of the module to be detected.
10. The chip reliability test method according to claim 8, wherein the networking detection instruction comprises: V2X networking instructions and 5G networking instructions.
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