CN219179919U

CN219179919U - Master-slave equipment debugging system

Info

Publication number: CN219179919U
Application number: CN202320048541.6U
Authority: CN
Inventors: 彭鹤; 杨生涛; 林元庆
Original assignee: SICHUAN ZHONGWANG KEXIMENG TECHNOLOGY CO LTD
Current assignee: SICHUAN ZHONGWANG KEXIMENG TECHNOLOGY CO LTD
Priority date: 2023-01-06
Filing date: 2023-01-06
Publication date: 2023-06-13
Anticipated expiration: 2033-01-06

Abstract

The utility model relates to the technical field of debugging, in particular to a debugging system of master-slave equipment, which comprises the following components: the system comprises a master device, a plurality of slave devices, a serial port matrix, a singlechip and a debugging host; the master device is connected with the plurality of slave devices through the serial matrix, one end of the singlechip is connected with the serial matrix, the other end of the singlechip is connected with the debugging host, and then the master device or the slave devices to be debugged can be rapidly switched through the serial matrix, so that the debugging efficiency is improved.

Description

Master-slave equipment debugging system

Technical Field

The utility model relates to the technical field of debugging, in particular to a debugging system of master-slave equipment.

Background

In serial port debugging applications of multiple slave devices of one host, the corresponding slave devices need to be manually connected, so that inconvenience is brought to debugging operation, and a situation of inserting a wrong debugging line often occurs, so that debugging efficiency is reduced.

Disclosure of Invention

The present utility model has been made in view of the above problems, and it is an object of the present utility model to provide a commissioning system of a master-slave device that overcomes or at least partially solves the above problems.

The utility model provides a debugging system of master-slave equipment, which comprises the following components:

the system comprises a master device, a plurality of slave devices, a serial port matrix, a singlechip and a debugging host;

the master device is connected with the plurality of slave devices through the serial port matrix;

and one end of the singlechip is connected with the serial port matrix, and the other end of the singlechip is connected with the debugging host.

Preferably, the singlechip is connected with the debugging host through a control bus.

Preferably, the serial port matrix is connected with an RS232 interface of the debugging host through a command terminal bus.

Preferably, the method further comprises: and one end of the ADC acquisition module is respectively connected with the master equipment and the plurality of slave equipment, and the other end of the ADC acquisition module is connected with the singlechip.

Preferably, each serial port of the serial port matrix is isolated and suspended.

Preferably, the master device is specifically connected with the main boards corresponding to the plurality of slave devices through the serial port matrix.

Preferably, the single chip microcomputer is specifically any one of the following:

MCU, CPU, GPU and FPGA.

One or more technical solutions in the embodiments of the present utility model at least have the following technical effects or advantages:

the utility model provides a debugging system of master-slave equipment, which comprises the following components: the system comprises a master device, a plurality of slave devices, a serial port matrix, a singlechip and a debugging host; the master device is connected with the plurality of slave devices through the serial matrix, one end of the singlechip is connected with the serial matrix, the other end of the singlechip is connected with the debugging host, and then the master device or the slave devices to be debugged can be rapidly switched through the serial matrix, so that the debugging efficiency is improved.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the utility model. Also throughout the drawings, like reference numerals are used to designate like parts. In the drawings:

fig. 1 is a schematic structural diagram of a debug system of a master-slave device in an embodiment of the present utility model.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present utility model, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.

The embodiment of the utility model provides a debugging system of master-slave equipment, as shown in fig. 1, comprising:

one master device 101, a plurality of slave devices 102, a serial port matrix 103, a singlechip 104 and a debug host 105;

the master device 101 and the plurality of slave devices 102 are connected through a serial port matrix 103;

one end of the singlechip 104 is connected with the serial port matrix, and the other end is connected with the debugging host 105.

In an alternative embodiment, the singlechip 104 is connected to the debug host 105 via a control bus 106. The debug host 105 is used to debug the master device 101 or the plurality of slave devices 102. Specifically, the debug host 105 sends a control instruction to the serial port matrix 103 through the singlechip 104, so as to connect with the master device 101 or any slave device 102, so as to debug the master device 101 or any slave device 102.

By adopting the serial port matrix 103, a plurality of devices can be debugged at the same time.

The serial port matrix 103 is connected with an RS232 interface of the debug host through the command terminal bus 107, so that the debug result of the master device 101 or any slave device 102 is transmitted to the debug host 105 through the command terminal bus 107 for display.

In an alternative embodiment, the system further comprises: and one end of the ADC acquisition module 108 is respectively connected with the master device 101 and the plurality of slave devices 102, and the other end of the ADC acquisition module is connected with the singlechip 104. The ADC acquisition module 08 is configured to acquire corresponding abnormal signals during a testing process of the master device 101 or the slave device 102, and transmit the abnormal signals to the testing host 105 through the singlechip 104.

Each path of serial port in the serial port matrix 103 is isolated and suspended, so that the serial port matrix 103 is isolated from each other when the master device 101 and any slave device 102 are connected, and mutual interference between the master device and any slave device is prevented. When any device needs to be debugged or monitored, a control command is sent to the singlechip 104 through the control bus 106, and the singlechip 104 configures a switching state to the serial port matrix 103, so that serial port switching is realized.

The test host 105 may be connected to not only the respective devices, i.e., the master device 101 and the plurality of slave devices 102, through the serial matrix 103, but also the master device 101 is connected to the respective slave devices 102 through the serial matrix 103, so as to enable communication between the master device 101 and the respective slave devices 102.

The master device 101 is specifically connected to the corresponding motherboard of each of the plurality of slave devices 102 through a serial port matrix 103. If there are 4 slave devices 102, it is specifically a motherboard 1, a motherboard 2, a motherboard 3, and a motherboard 4.

The singlechip is specifically any one of the following:

MCU, CPU, GPU and FPGA. Of course, other chips are also possible and are not limited thereto.

While preferred embodiments of the present utility model have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the utility model.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present utility model without departing from the spirit or scope of the utility model. Thus, it is intended that the present utility model also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

1. A master-slave device commissioning system comprising:

2. The system of claim 1, wherein the single-chip microcomputer is connected to the debug host via a control bus.

3. The system of claim 1, wherein the serial port matrix is coupled to an RS232 interface of the debug host via a command termination bus.

4. The system as recited in claim 1, further comprising: and one end of the ADC acquisition module is respectively connected with the master equipment and the plurality of slave equipment, and the other end of the ADC acquisition module is connected with the singlechip.

5. The system of claim 1, wherein each of the plurality of serial ports of the serial port matrix is suspended in isolation.

6. The system of claim 1, wherein the master device is connected to a motherboard corresponding to each of the plurality of slave devices through the serial port matrix.

7. The system of claim 1, wherein the single-chip microcomputer is specifically any one of the following:

MCU, CPU, GPU and FPGA.