CN107704406A - Chip testing exception monitoring device, method, computer equipment and storage medium - Google Patents
Chip testing exception monitoring device, method, computer equipment and storage medium Download PDFInfo
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- CN107704406A CN107704406A CN201711044918.6A CN201711044918A CN107704406A CN 107704406 A CN107704406 A CN 107704406A CN 201711044918 A CN201711044918 A CN 201711044918A CN 107704406 A CN107704406 A CN 107704406A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/38—Universal adapter
- G06F2213/3852—Converter between protocols
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Abstract
The present invention relates to a kind of chip testing exception monitoring device, method, computer equipment and storage medium.The device includes：Multi-serial port modular converter and switch module, Multi-serial port modular converter is connected with least one test chip, for at least one test chip output interface to be forwarded to and test chip output interface parallel network interface correspondingly, switch module is connected with Multi-serial port modular converter and host computer respectively, for the parallel network interface of Multi-serial port modular converter to be forwarded into serial network interface, communicated by serial network interface with host computer.Realize that parallel multi-channel serial port data input, the single channel network interface data of high speed serialization export by Multi-serial port modular converter, the serial data of all chips is monitored in real time using a host computer, improve the real-time and accuracy of test chip abnormal conditions monitoring, so that staff is handled abnormal conditions in time, and personal monitoring is avoided not in time or the problem of missing inspection.
Description
Technical field
The present invention relates to chip testing field, more particularly to a kind of chip testing exception monitoring device, method, computer
Equipment and storage medium.
Background technology
When carrying out high/low temperature test to chip, to ensure that the quality of test and test abnormal conditions progress are anti-in time
Feedback, it is therefore desirable to monitored in real time to test process.At present, it is by artificial for the exception monitoring in chip testing process
The mode of poll check, local preservation is carried out to every road serial data using serial ports software secureCRT, by judging that serial ports is
No normal print identifies exception.
Based on JESD22-A108, JESD47I standard and specific actual requirement, one time test chip quantity is generally
45, and the testing time of overlength is needed, and the frequency of hand inspection is limited to, it will lead to not find and feed back exception in time
Situation, so as to significantly reduce chip testing efficiency.
The content of the invention
Based on this, it is necessary to can not in time be found for personal monitoring's mode and feed back abnormal conditions, so as to reduce core
The problem of built-in testing efficiency, there is provided a kind of chip testing exception monitoring device, method, computer equipment and storage medium.
A kind of chip testing exception monitoring device, including：Multi-serial port modular converter and switch module,
The Multi-serial port modular converter is connected with least one test chip, at least one test chip is defeated
Outgoing interface is forwarded to and the test chip output interface parallel network interface correspondingly；
The switch module is connected with Multi-serial port modular converter and host computer respectively, for by the Multi-serial port modulus of conversion
The parallel network interface of block is forwarded to serial network interface, is communicated by the serial network interface with host computer.
In one of the embodiments, the Multi-serial port modular converter includes at least one serial interface unit and at least one
Individual super network interface unit；
The serial interface unit connects one to one with the test chip, for the output of the test chip to be connect
Mouth is forwarded to parallel serial ports；
The super network interface unit connects one to one with the serial interface unit, for the parallel serial ports to be transferred
To parallel network interface.
In one of the embodiments, the Multi-serial port modular converter also includes power module of voltage regulation, the voltage-stabilized power supply
Module includes power conversion unit, first voltage converting unit, current limiting unit and the second voltage converting unit being sequentially connected；
The power conversion unit external power supply, is depressured to the external power supply voltage and AC-DC is changed, and exports conversion
DC voltage afterwards；The DC voltage is converted to and is adapted to the Multi-serial port modular converter by the first voltage converting unit
First voltage；The current limiting unit carries out decompression current limliting to the first voltage and handles and export, and the Multi-serial port is changed
Module is powered；The voltage conversion that the second voltage converting unit exports the current limiting unit is second voltage, to institute
Super network interface unit is stated to be powered.
In one of the embodiments, in addition to power supply monitoring module, the power supply monitoring module include：Master control borad and
At least one piece of power panel for including multiple-output electric power；
The master control borad is connected with the power panel, for being controlled to the power panel, and receives host computer transmission
Instruction, the power supply parameter of the power panel is obtained according to the instruction, the power supply parameter is uploaded to host computer；
The power panel is connected with the test chip, and the test chip is distributed and powered, and monitors each survey in real time
Try the power supply parameter of chip.
In one of the embodiments, the power panel also includes voltage switching unit, the protection list that multichannel is sequentially connected
Member, sampling unit and A/D converting units；The voltage switching unit is connected with input power, supply voltage is switched to required
Input voltage；The protection location carries out current-limiting protection to the power panel；The corresponding out-put supply of sampling unit collection
Voltage, and transmit to the A/D converting units；The A/D converting units by the voltage conversion of the out-put supply be electric current and/
Or performance number, and the electric current and/or performance number are sent to the master control borad.
A kind of chip testing method for monitoring abnormality, comprises the following steps：
Serial ports Monitoring instruction is triggered according to input signal, and test chip supervised according to the serial ports Monitoring instruction of initiation
Survey；
String that test chip is sent, being transmitted by Multi-serial port modular converter and switch module is received by serial network interface
Mouth data；
Judge whether the test chip is abnormal according to the serial data.
In one of the embodiments, in addition to：
According to input signal trigger current Monitoring instruction, and the electric current according to the instruction of the current monitoring of initiation to test chip
Data are monitored；
Obtain the current data of the test chip；
Judge whether the test chip is abnormal according to the current data of the test chip.
In one of the embodiments, it is described that the whether abnormal step of the test chip is judged according to the serial data
Including：
Detect the serial data and whether there is default key parameter；
When detecting that the serial data has default key parameter, judge whether the key parameter is abnormal.
A kind of computer equipment, including memory, processor and storage can be run on a memory and on a processor
Computer program, the chip testing method for monitoring abnormality described in any of the above-described is realized during the computing device program.
A kind of computer-readable recording medium, is stored thereon with computer program, and the program is realized when being executed by processor
Chip testing method for monitoring abnormality described in any of the above-described.
Said chip test exception monitoring device, method, computer equipment and storage medium, will be surveyed by Multi-serial port module
Try chip parallel output interface to the test chip output interface parallel network interface, and pass through interchanger correspondingly
The parallel network interface of Multi-serial port modular converter is forwarded to serial network interface and is connected with host computer by module, upper using one so as to realize
Machine is monitored in real time to the serial data of all chips, improves the real-time of test chip abnormal conditions monitoring and accurate
Property, so that staff is handled abnormal conditions in time, also, personal monitoring is avoided not in time or the problem of missing inspection.
Brief description of the drawings
Fig. 1 is the structural representation of an embodiment SMIS built-in testing exception monitoring device；
Fig. 2 is the structural representation of Multi-serial port modular converter in an embodiment；
Fig. 3 is the structural representation of another embodiment SMIS built-in testing exception monitoring device；
Fig. 4 is the structural representation of power module of voltage regulation in an embodiment；
Fig. 5 is the circuit structure diagram of power module of voltage regulation in another embodiment；
Fig. 6 is the circuit structure diagram of Multi-serial port modular converter in another embodiment；
Fig. 7 is the structural representation of power supply monitoring module in an embodiment；
Fig. 8 is the circuit structure diagram of master control borad in an embodiment；
Fig. 9 is the circuit structure diagram of electric source monitoring circuit in an embodiment；
Figure 10 is power panel and the structural representation of test chip wiring in an embodiment；
Figure 11 is power panel and the contrast schematic diagram of test chip wiring in an embodiment；
Figure 12 is the schematic flow sheet of an embodiment SMIS built-in testing method for monitoring abnormality；
Figure 13 is the schematic flow sheet of another embodiment SMIS built-in testing method for monitoring abnormality；
Figure 14 is the schematic flow sheet that monitoring of software initializes in an embodiment；
Figure 15 is the schematic flow sheet of another embodiment SMIS built-in testing method for monitoring abnormality；
Embodiment
In order that the object, technical solution and advantage of the application are more clearly understood, it is right below in conjunction with drawings and Examples
The application is further elaborated.It should be appreciated that specific embodiment described herein is only to explain the application, and
It is not used in restriction the application.
In one embodiment, as shown in figure 1, a kind of chip testing exception monitoring device 200, including：Multi-serial port modulus of conversion
Block 210 and switch module 220, Multi-serial port modular converter 210 are connected with least one test chip 100, for will at least
One output interface of test chip 100 is forwarded to and test chip output interface parallel network interface correspondingly, switch module
220 are connected with Multi-serial port modular converter 210 and host computer 300 respectively, for the parallel network interface of Multi-serial port modular converter 210 to be turned
Serial network interface is connected to, is communicated by serial network interface with host computer 300.
Need to carry out height to the IC that design is produced in IC (integrated circuit, integrated circuit) Qualify Phase
Low-Temperature Reliability is tested, in order to ensure the timely feedback of the quality of experiment and singularity in experiment, it is necessary to which experimentation is carried out
Monitoring in real time, by the way that multiple test IC 100 are connected into chip testing exception monitoring device 200, supervised extremely using chip testing
Survey device 200 and multiple parallel input serial ports are forwarded to a Serial output network interface so that be connected with multiple test IC parallel
Serial Port Line switching is connected into a Serial output netting twine with host computer 300, so as to can be realized by a host computer 300 simultaneously
Real-time monitoring to multiple test chips 100, avoid personal monitoring not in time or missing inspection situation, it is different to improve test chip
The real-time and accuracy of normal condition monitoring.
In one embodiment, as shown in Fig. 2 Multi-serial port modular converter 210 includes at least one serial interface unit
211 and at least one super network interface unit 212, serial interface unit 211 connected one to one with test chip 100, for will
The output interface of test chip 100 is forwarded to parallel serial ports, and super network interface unit 212 corresponds with serial interface unit 211
Connection, for parallel serial ports to be forwarded into parallel network interface.
Super network interface is a kind of embedded serial port networked device, for realizing serial ports to the two-way of the data of Ethernet interface
Bright forwarding, it internally completes protocol conversion, the concrete operations details that user changes without care of protocol.User can also pass through letter
Singly set the parameters to set its operational detail, wherein, the setting of parameter both can also may be used by being configured inside super network interface
By setting software to be configured, once to set persistence.
In the present embodiment, test chip 100 is connected to serial interface unit 211, super network interface unit by Serial Port Line
212 transfer serial ports into network interface, then carry out the transmission of data with host computer by the netting twine that network interface accesses.Pass through supernet list
The translation function that member 212 realizes " serial ports-network interface ", each equal correspondence mappings of serial ports are into a LAN IP address, each IP
Address re-maps into a corresponding virtual serial port number on host computer, it is achieved thereby that the transparent transmission function of serial ports.And due to super
Level network interface once sets the characteristic of persistence, and no matter whether host computer restarts, and serial port is unique corresponding to each serial ports
Determine, be truly realized the permanent use of once configuration.
In another specific embodiment, Multi-serial port modular converter 210 also includes string corresponding with each serial interface unit 211
Mouth run indicator, according to the fortune of serial interface unit 211 corresponding to the flicker frequency of serial ports run indicator or color instruction
Row state.
As shown in figure 3, being the structural representation of a chip testing exception monitoring device, Multi-serial port plate includes several serial ports
Interface and several super network interface (not shown)s, serial interface plate is interior to connect super network interface corresponding pin, is accessed between plate
The serial ports end of test chip, serial interface in the connecting plate of super network interface one end, the other end are connected to interchanger by netting twine, in it
Conversion of the serial ports to network interface is realized in portion's encapsulation.Multiple test chips access the serial interface of Multi-serial port plate by Serial Port Line respectively,
Multi-serial port plate realizes that serial interface inputs, after network interface output, then further accesses to interchanger by netting twine, finally from interchanger
A piece netting twine of middle extraction is connected to monitoring host computer, so as to realize multiple serial ports inputs, the function of a network interface output.By this
Chip testing exception monitoring device, the single channel network interface data by parallel multi-channel serial port data conversion into high speed serialization, network
Transport protocol conversion substantially increases the stability of data transfer into Ethernet host-host protocol.Also, each test core
Piece can access to the chip testing exception monitoring device, the Serial Port Information of all test chips and be passed to one eventually through network interface
Host computer, reduces the quantity of required host computer, and then reduces the cost being monitored extremely to chip testing, and letter
Experimental situation is changed.
In another embodiment, Multi-serial port modular converter 210 also includes power module of voltage regulation, as shown in figure 4, voltage-stabilized power supply
Module includes power conversion unit 213, first voltage converting unit 214, current limiting unit 215 and the second voltage being sequentially connected
Converting unit 216, the external power supply of power conversion unit 213, is depressured to external supply voltage and AC-DC is changed, and
DC voltage is converted to and fitted with Multi-serial port modular converter 210 by the DC voltage after output conversion, first voltage converting unit 214
The first voltage matched somebody with somebody, current limiting unit 215 carries out decompression current limliting to first voltage 214 and handles and export, to Multi-serial port modular converter
210 are powered, and the voltage conversion that second voltage converting unit 216 exports current limiting unit 215 is second voltage, to super net
Mouth unit 212 is powered.
In one embodiment, power conversion unit 213 includes fiery ox adapter, fiery ox adapter access 220V exchanges
Civil power, and it is converted into 12V DC voltage output.
As shown in figure 5, first voltage converting unit 214 includes MP1482DS chips, resistance R1, R2, R3, R4, R5,56,
Electric capacity OC1, OC2, OC3, OC4, OC5, the input pin IN of inductance OL1, MP1482DS chip and the output end of fiery ox adapter
Connection, the output end of fiery ox adapter are also connected by resistance R2 with the EN pins of MP1482DS chips, resistance R2 first end
It is connected with the output end of fiery ox adapter, resistance R2 the second end and the common port and resistance R4 of the EN pins of MP1482DS chips
First end connection, the positive pole of resistance R2 first end also with electrochemical capacitor OC2 is connected, electrochemical capacitor OC2 negative pole and resistance
R4 the second end connection, electrochemical capacitor OC2 negative pole connect with the common port at resistance R4 the second end and electric capacity OC4 first end
Connect, electric capacity OC4 the second end is connected with the SS pins of MP1482DS chips, electrochemical capacitor OC2 negative pole, resistance R4 the second end
It is grounded with electric capacity OC4 first end, the COMP pins of MP1482DS chips are connected with resistance R5 first end, and the second of resistance R5
End be connected with electric capacity OC5 first end, electric capacity OC5 the second end is connected with resistance R6 first end, resistance R6 the second end and
The FB pins connection of MP1482DS chips, resistance R6 the second end and the common port and resistance R3 of the FB pins of MP1482DS chips
First end connection, resistance R3 the second end is connected with inductance OL1 first end, inductance OL1 the second end and MP1482DS cores
The SW pins connection of piece, inductance OL1 the second end are also connected with an electric capacity OC1, pass through electric capacity OC1 and the BST of MP1482DS chips
Pin is connected, and resistance R3 the second end is connected with the common port of inductance OL1 first end with electrochemical capacitor OC3 positive pole, is electrolysed
The second end ground connection of electric capacity OC3 negative pole, resistance R6 first end and electric capacity OC5, the of resistance R3 the second end and inductance OL1
The common port of the common port of one end and electrochemical capacitor OC3 positive pole passes through output 5V voltages after series resistance R1.
Current limiting unit 215 includes current limliting chip MT9700, resistance R9, R10, R11, R12, electric capacity C1, C2, and first voltage turns
Change the output end of unit 214 the input pin IN with current limliting chip MT9700, resistance R9 first end, the first of electric capacity C1 respectively
End connection, resistance R9 the second end are connected with current limliting chip MT9700 EN pins, resistance R9 the second end and current limliting chip
The common port of MT9700 EN pins is connected with resistance R10 first end, resistance R10 the second end and electric capacity C1 the second termination
Ground, the first end of current limliting chip MT9700 ISET pins respectively with resistance R11, R12 are connected, resistance R11, R12 the second end
It is connected with electric capacity C2 first end, electric capacity C2 the second end is connected with current limliting chip MT9700 output pin OUT, MT9700 limits
Whole circuital current is limited to 4.25A by stream chip, and 5V voltages after MT9700 current limliting chips current limliting for Multi-serial port by changing
Module 210 is powered, and is that super network interface unit 212 is powered by second voltage converting unit 216.
In another embodiment, as shown in fig. 6, second voltage converting unit 216 includes AMS117-3.3V chips, pass through
It after 3.3V voltages is that super network interface unit 212 is powered that 5V voltage conversions are by AMS117-3.3V chips.
It can be that Multi-serial port modular converter 210 provides stable supply voltage by above-mentioned power module of voltage regulation, utilize
Whole circuital current can be limited to 4.25A by MT9700 current limlitings chip, when electric current is more than 4.25A, MT9700 current limliting chip meetings
Reach the purpose of reduction electric current by reducing output voltage, burnt so as to avoid the high current caused by short circuit or other exceptions
Ruin circuit.
As shown in fig. 6, the circuit diagram for Multi-serial port modular converter in a specific embodiment.Multi-serial port circuit realiration is by serial ports
Data are transformed into Ethernet and virtual serial port corresponding to High Speed Transfer to host computer PC.Multi-serial port modular converter turns including 24 tunnels
Circuit is changed, it is basically identical per road circuit structure, and Fig. 6 show the circuit diagram on wherein four tunnels, wherein, U11, U13, U15, U17
It is super network interface unit, realizes serial ports-network interface conversion, J24 and J2 are that the total power input of whole Multi-serial port modular converter connects
Mouthful, U8 be 3.3V LDO, is powered for the super network interface in 4 tunnels, J4, J5, J6, J7 for super network interface unit U11, U13, U15,
Serial interface unit corresponding to U17.
In another embodiment, chip testing exception monitoring device 200 also includes power supply monitoring module, power supply monitoring module
Including：Master control borad and at least one piece of power panel for including multiple-output electric power, master control borad is connected with power panel, for power supply
Plate is controlled, and receives the instruction of host computer transmission, and the power supply parameter of power panel is obtained according to instruction, power supply parameter is uploaded
To host computer, power panel is connected with test chip, and test chip is distributed and powered, and monitors the power supply of each test chip in real time
Parameter.
In one embodiment, as shown in fig. 7, master control borad is communicated by serial ports with host computer, power supply monitoring is being carried out
When, master control borad receives the instruction that host computer is sent, and the operation according to corresponding to performing the instruction, for example obtains the power supply of power panel
Parameter, when getting the power supply parameter of power panel, it is uploaded to host computer.
Communicated between master control borad and power panel by IIC interfaces, when master control borad receives the instruction of host computer transmission
When, the instruction is analyzed and performs corresponding operation, by IIC Interface Controller power panels, acquisition currently flows through power panel
Electric current, voltage and performance number, return to host computer after carrying out respective handling to acquired value.
As shown in figure 8, for master control borad circuit diagram in a specific embodiment, in the present embodiment, master control borad uses single-chip microcomputer
LPC1768, single-chip microcomputer LPC1768 are connected with host computer and each power panel, receive the power supply monitoring instruction that host computer issues, and
Each power panel collection current data is controlled according to the instruction and uploaded, single-chip microcomputer LPC1768 is additionally operable to the power supply to each power panel
The power supply of each device is controlled in distribution and Multi-serial port modular converter.In other embodiments, master control borad can also use it
His microcontroller.
Power panel is mainly used in realizing the function of current sample and power distribution, as shown in fig. 7, every piece of power panel inputs
DC-12V/30A power supplys, and 24 road power supply outputs are dispersed into, 24 road power supply outputs correspond respectively to the V shown in Fig. 71, V2... ...,
V24, V is exported to every road power supply by power panel simultaneously1, V2... ..., V24Output current be monitored.Wherein, power supply exports
V1, V2... ..., V24Two kinds of output modes of 5V/12V may be selected.
As shown in figure 9, for wherein the circuit diagram of observation circuit, the switching of 12V/5V patterns are carried out by R150 and R152 all the way
Hardware configuration, acquiescence NC R152 are 12V output modes, and VCCIN1 flows through current sampling resistor R25 afterwards by fuse F1,
And be powered from the output of P1 mouths, U1 is 12bit ADC chips, and the voltage and line voltage at ADC chips collection R25 both ends are simultaneously interior
Portion is converted into electric current and performance number, is sent by IIC interfaces to power supply master control borad.Wherein, fuse F1 current limlitings 2A, ADC chips
INA219BIDCNT chips can be used.
The above-mentioned method for carrying out concentration supply power to test chip by chip testing exception monitoring device, compared to traditional
The discrete type power supply mode of a power supply, the complexity that the experimental situation further reduced is built is respectively configured in every piece of test chip
Degree, and improve the security of experiment.Also, monitor the current value of every road test chip in real time by power panel and provided
Protection mechanism is flowed, so as to which power supply can be disconnected in time when test chip happened suddenly throat floater with protection circuit.
When testing chip, generally each test chip is positioned over to be tested in chamber, with each test
The Serial Port Line of chip connection is both needed to be connected with external devices by the threading hole of chamber.In one embodiment, power panel passes through
USB turns Serial Port Line and is connected with test chip, wherein, it is 5 ray modes that USB, which turns Serial Port Line, including 1 power line, 1 ground wire GND,
2 data lines and an ID line, 2 data lines are respectively to receive data wire RXD and transmission data wire TXD.
In another embodiment, as shown in Figure 10, USB turns Serial Port Line and uses 3 ray modes, only including 1 ground wire GND, 1
Data wire RXD and 1 transmission data wire TXD are received, and the ground wire GND of each test chip handle altogether, specifically, will
The earth terminal and power end of each test chip are respectively connected to the public power terminal plate in chamber, and by public power terminal plate
Draw the earth terminal connection of a ground wire and power panel, draw the power output end connection of a power line and power panel.
When as shown in figure 11, for 3 ray modes and 5 ray mode is respectively adopted, power panel and 45 pieces of test chips carry out power supply
Line and the contrast schematic diagram of Serial Port Line connection.When power panel is connected using 5 ray modes with test chip, 45 × 5 are needed altogether
=225 serial ports wires, when power panel is connected using 3 ray modes with test chip, 45 × 2=90 root serial ports is needed to lead altogether
Line, using 3 ray modes compared to 5 ray modes are used, the quantity of serial ports wire is considerably reduced, avoids the feelings of redundancy wiring
Condition, reduce further total line footpath, reduce because more than test chip quantity and caused by total line footpath of power line and Serial Port Line
More than the situation in chamber threading hole aperture.
Said chip test exception monitoring device, by Multi-serial port module by test chip parallel output interface to
Test chip output interface parallel network interface correspondingly, and by switch module by the parallel network interface of Multi-serial port modular converter
It is forwarded to serial network interface to be connected with host computer, the serial data of all chips is carried out in real time using a host computer so as to realize
Monitoring, reduces the quantity of required host computer, and then reduces the cost being monitored extremely to chip testing, and simplifies reality
Test environment.Also, exception monitoring device and method is tested by said chip, the test shape of test chip can be understood in real time
State, the real-time and accuracy of the monitoring of test chip abnormal conditions are improved, so that staff enters to abnormal conditions in time
Row processing, avoid personal monitoring not in time or missing inspection situation.And it is steady to use concentration supply power mode to provide test chip
Fixed dc source, the complexity that the experimental situation further reduced is built, and improve the security of experiment.
In another embodiment, as shown in figure 12, a kind of chip testing method for monitoring abnormality is also provided, this method includes step
Rapid S110 to S130：
S110, serial ports Monitoring instruction is triggered according to input signal, and according to the serial ports Monitoring instruction of initiation to test chip
It is monitored.
Input signal refers to the signal that user is generated in host computer by input operation, in the present embodiment, input signal
It is the corresponding signal for including triggering serial ports Monitoring instruction.Serial ports Monitoring instruction is can trigger according to being parsed to input signal,
Monitoring to test chip is performed according to the serial ports Monitoring instruction of initiation.
S120, by serial network interface receive it is that test chip is sent, pass through Multi-serial port modular converter and switch module and pass
Defeated serial data.
In the present embodiment, test chip is connected by Multi-serial port modular converter, switch module and host computer, and more strings
Mouth modular converter can connect polylith test chip, and therefore, host computer is i.e. acceptable by Multi-serial port modular converter, switch module
The serial data sent to polylith test chip, polylith test chip can be monitored in real time simultaneously.
S130, judge whether test chip is abnormal according to serial data.
In the present embodiment, serial data can be used for judging whether test chip is abnormal, passes through the serial data to reception
Analyzed, when serial data exception, then illustrate that test chip corresponding to the serial data is abnormal.
In another embodiment, serial data includes the key parameter for characterization test chip running status,
In said chip test method for monitoring abnormality, it can be realized using Multi-serial port modular converter while to polylith test chip
Monitored in real time, by analyzing the serial data of Multi-serial port modular converter transparent transmission, find test chip in time
Abnormal conditions, improve the efficiency of test chip exception monitoring, so as to staff according to monitoring result to abnormal conditions and
Shi Jinhang processing.
In one embodiment, judge whether abnormal step includes test chip according to serial data：Detect serial ports
Data whether there is default key parameter, when detecting that serial data has default key parameter, whether judge key parameter
It is abnormal.
Key parameter refers to the running parameter that can be used for identification test chip whether abnormal.In the present embodiment, examine first
Serial data is surveyed whether comprising default key parameter, when the serial data of reception is not comprising default key parameter, then explanation should
Test chip operation irregularity corresponding to serial data, when the serial data of reception includes default key parameter, then further sentence
The key parameter break with the presence or absence of abnormal, when the key parameter exception, then test chip operation irregularity corresponding to explanation, otherwise
Test chip is working properly corresponding to explanation.
In another embodiment, as shown in figure 13, chip testing method for monitoring abnormality also includes step S210 to S230：
S210, instructed according to input signal trigger current Monitoring instruction, and according to the current monitoring of initiation to test chip
Current data be monitored.
S220, obtain the current data of test chip.
S230, judge whether test chip is abnormal according to the current data of test chip.
In the present embodiment, input signal is to include the corresponding signal of trigger current Monitoring instruction.By to input signal
Carry out parsing trigger current Monitoring instruction, instructed to perform according to the current monitoring of initiation and the current data of test chip is supervised
Survey, and then can determine whether test chip is abnormal according to the current data of the test chip of acquisition.Based on current data to test
Chip method for monitoring abnormality, it can be achieved effectively to monitor the chip without serial ports such as PMU series, it is applied widely.
In another specific embodiment, the whether abnormal step bag of test chip is judged according to the current data of test chip
Include：The current data of test chip and predetermined threshold value are compared, judge whether test chip is abnormal according to comparative result.When
When the current data of test chip exceeds predetermined threshold value, then illustrate test chip operation exception.
In another embodiment, judge whether test chip abnormal and/or electricity according to test chip according to serial data
Fluxion is it is judged that after the whether abnormal step of test chip, in addition to step：When recognizing test chip exception, generation report
Alert information is simultaneously alarmed.
Wherein, warning message can be e-mail messages, and when recognizing test chip exception, mail is generated according to anomaly parameter
Information simultaneously triggers mail alarm, the mail is sent to relevant staff, after staff is according to the warning message received
Investigation abnormal conditions in time.In other embodiments, warning message can also be sound and light alarm information, short message etc..
When recognizing test chip exception, generate warning message and include the step of alarm：Tested when recognizing
During chip exception, whether abnormal time duration is judged more than the first preset duration, when abnormal time duration is default more than first
When long, generate warning message and alarmed.Wherein, the first preset duration may be configured as five minutes.
After the step of when recognizing test chip exception, generating warning message and being alarmed, in addition to：Work as knowledge
When being clipped to that test chip is abnormal and alarm duration is more than the second preset duration, trigger again and perform alarm.Wherein, second is default
Duration may be configured as 30 minutes.
In one embodiment, said chip test method for monitoring abnormality is performed by the monitoring of software of host computer.Should
Monitoring of software interface mainly includes 8 regions, and 8 regions are respectively real time data waveform display switch button, current experiment shape
State display window, serial port setting window, serial ports open button, operating result status bar, serial data and send window, serial data
Receive window and monitored parameter allocation window.
It is show states under real time data waveform display switch button default conditions, cyan button, is beaten when click switches to
During open state, button text is shown as " showing... ", while Button Color is changed into red, and corresponding can show currently is chosen
The real time data waveform of passage.
Current experiment status display window shows the state per serial ports all the way, per serial ports all the way with unique serial port table
Show, the path of corresponding serial ports is opened by double-clicking serial port, the background colour of selected serial port is blueness, and word is white；
Serial port represents that serial ports is not connected with to be red, and green represents serial ports connection, and all normal operations, yellow then represent com-state
It is open mode, but corresponding test chip is but without output critical data.
Serial port setting window can carry out tetra- parameters of baudrate, parity, databit, stopbit to each serial ports
Configured.
Serial ports opens button, i.e. open buttons, and it is equivalent with double-clicking the serial port in second area to click open buttons.
Operating result status bar shows the result phase of current operation, should when show buttons are opened in first area
Status bar is shown as " showing Successful！", when show buttons, which are clicked on, closes, the status bar shows " showing
closed！”.
Serial data, which sends window, includes an input area, two SRs, HEX and New Line choice boxs, when
When selecting New Line, the data of transmission add newline automatically, and as Hex in choosing, data are sent in a manner of hexadecimal.
Serial data, which receives window, includes a viewing area, clear buttons, HEX choice boxs and Threshold inputs
Frame, Threshold input frames have disabled the function (debugging is used), can not considered, whether HEX choice boxs determine display data mode
Shown for 16 systems, clear buttons are responsible for emptying viewing area, and not only real-time display serial ports receives data for viewing area, also
Time-write interval and current test chip numbering can be shown.
Monitoring parameters allocation window includes monitoring pattern button, Alarm Limit setting areas, can be monitored by clicking on
The mode of mode button selects to monitor serial data or monitoring current data, can be in Alarm Limit setting areas
Exception boundary value is set manually.
In one embodiment, double-click and choose normally functioning serial port COM117, now serial data receives window
Viewing area real-time reception and all serial datas of the serial ports can be shown, then click on show buttons, it will recall one it is new
Display interface, the new display interface includes waveform display area, and waveform display area can be based on serial data and receive window
Viewing area serial data extraction key parameter, and then drawing data curve and show.
Real-time condition display, realtime curve are supported, data is sent, switches check not at any time in above-mentioned monitoring of software interface
With serial ports path, set serial ports and monitoring parameters, serial data waveform the function such as to show, be easy to based on above-mentioned monitoring of software interface
User checks and managed the experimental state of each serial ports path.
In one embodiment, serial ports Monitoring instruction is being triggered according to input signal, and according to the serial ports Monitoring instruction of initiation
Before the step of being monitored to test chip, in addition to the step of initialized to the monitoring of software of host computer.As shown in figure 14,
The step of being initialized to the monitoring of software of host computer specifically includes step S310 to step S390：
S310, configuration file Default.py is read, obtain default parameters and initialize the display interface of monitoring of software.
S320, all serial ports being connected with host computer are opened successively.
S330, when serial ports, which is opened, occurs abnormal, the warning message of generation " serial ports opens failure " simultaneously exits software.
S340, when serial ports is successfully opened, generation and serial port log files of the same name and compressed file of the same name.
S350, when all serial ports are successfully opened, self-test operations are performed to all serial ports, and according to self-test operations brush
Com-state in new display interface.
S360, power panel self-checking command is sent to master control borad, and receive the power panel self-test parameter of master control borad return.
S370, judge whether power panel is abnormal according to power panel self-test parameter.
S380, when power panel self-test exception, the warning message of generation " power panel is abnormal " simultaneously exits software.
S390, when power panel self-test is normal, monitoring of software initialization is prompted to complete.
Mainly the display interface including monitoring of software, power supply monitoring plate initialize, monitor ring for above-mentioned monitoring of software initialization
Border self-test, opening correspond to serial ports per road and generate log files and corresponding compressed file.The display interface initialization of monitoring of software
Each road Serial Port Information and serial ports parameter setting interface are mainly initialized, all Serial Port Informations are shown to display interface, wherein
Serial Port Information includes current serial ports quantity, current all serial ports, com-state etc..In monitoring system, every piece of test chip
There are corresponding logic serial port, serial data log files, compressed file, current data file, serial ports caused by test chip
Data will be stored in corresponding serial data log files, and caused current data will be stored in corresponding current data file.
As shown in figure 15, method is monitored extremely to chip testing for monitoring of software.Monitoring of software completes initialization
Afterwards, test chip is accessed in Multi-serial port modular converter, click starts to monitor button.Software detection is opened to after initiation command
Originate and send corresponding Monitoring instruction.When Monitoring instruction is that current monitoring instructs, control master control borad performs the acquisition behaviour of current data
Make, and current data return host computer is pre-processed and is stored in compressed file.When Monitoring instruction is serial ports Monitoring instruction
When, control serial ports receives the serial data of test chip, by serial data real-time display corresponding to the serial ports currently chosen in UI
Interface serial data is received in the viewing area of window, and data are cleaned and identified, will recognize critical data deposit
In compressed file, initial data is stored in log files of the same name.After current data and/or critical data is acquired, according to pressure
The list of time, critical data and current data in contracting file, carry out abnormality detection in a manner of pre-set threshold value, different when recognizing
Chang Shi, whether abnormal time duration is judged more than five minutes, if abnormal time duration was not less than five minutes, trigger software interface
Abnormality mark, the abnormality mark can be represented by the color of UI interfaces serial port, otherwise trigger mail warning function, will be abnormal
Information is sent to relevant persons in charge.
Said chip tests method for monitoring abnormality, after completing to the initialization of monitoring of environmental, is triggered according to input signal
Monitoring to test chip, the Monitoring Data of polylith test chip is received by Multi-serial port modular converter, is realized while to more
The real-time monitoring of block test chip, by analyzing the serial data of transparent transmission, the exception of test chip is found in time
Situation, and warning message is generated according to abnormal information and alarmed, the efficiency of test chip exception monitoring is improved, is easy to work
Personnel are investigated and handled in time to abnormal conditions according to warning message.
In another embodiment, a kind of computer equipment is also provided, including memory, processor and is stored in memory
Computer program that is upper and can running on a processor, realize that the chip testing of the various embodiments described above is different during computing device program
Normal monitoring method.
In another embodiment, a kind of computer-readable recording medium is also provided, is stored thereon with computer program, the journey
The chip testing method for monitoring abnormality of the various embodiments described above is realized when sequence is executed by processor.
Each technical characteristic of above example can be combined arbitrarily, to make description succinct, not to above-described embodiment
In each technical characteristic it is all possible combination be all described, as long as however, lance is not present in the combination of these technical characteristics
Shield, all it is considered to be the scope of this specification record.
Above example only expresses the several embodiments of the present invention, and its description is more specific and detailed, but can not
Therefore it is construed as limiting the scope of the patent.It should be pointed out that for the person of ordinary skill of the art,
On the premise of not departing from present inventive concept, various modifications and improvements can be made, these belong to protection scope of the present invention.
Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (10)
- A kind of 1. chip testing exception monitoring device, it is characterised in that including：Multi-serial port modular converter and switch module,The Multi-serial port modular converter is connected with least one test chip, at least one test chip output to be connect Mouth is forwarded to and the test chip output interface parallel network interface correspondingly；The switch module is connected with Multi-serial port modular converter and host computer respectively, for by the Multi-serial port modular converter Parallel network interface is forwarded to serial network interface, is communicated by the serial network interface with host computer.
- 2. chip testing exception monitoring device according to claim 1, it is characterised in that the Multi-serial port modular converter bag Include at least one serial interface unit and at least one super network interface unit；The serial interface unit connects one to one with the test chip, for the output interface of the test chip to be turned It is connected to parallel serial ports；The super network interface unit connects one to one with the serial interface unit, for the parallel serial ports to be forwarded to simultaneously Row network interface.
- 3. chip testing exception monitoring device according to claim 2, it is characterised in that the Multi-serial port modular converter is also Including power module of voltage regulation, the power module of voltage regulation include be sequentially connected power conversion unit, first voltage converting unit, Current limiting unit and second voltage converting unit；The power conversion unit external power supply, the external power supply voltage is carried out Decompression and AC-DC conversion, and export the DC voltage after conversion；The first voltage converting unit is by the DC voltage Be converted to the first voltage being adapted to the Multi-serial port modular converter；The current limiting unit carries out decompression limit to the first voltage Stream process is simultaneously exported, and the Multi-serial port modular converter is powered；The second voltage converting unit is by the current limiting unit The voltage conversion of output is second voltage, and the super network interface unit is powered.
- 4. chip testing exception monitoring device according to claim 1, it is characterised in that also including power supply monitoring module, The power supply monitoring module includes：Master control borad and at least one piece of power panel for including multiple-output electric power；The master control borad is connected with the power panel, for being controlled to the power panel, and receives the finger of host computer transmission Order, the power supply parameter of the power panel is obtained according to the instruction, the power supply parameter is uploaded to host computer；The power panel is connected with the test chip, and the test chip is distributed and powered, and monitors each test core in real time The power supply parameter of piece.
- 5. chip testing exception monitoring device according to claim 4, it is characterised in that the power panel also includes multichannel Voltage switching unit, protection location, sampling unit and the A/D converting units being sequentially connected；The voltage switching unit and input Power supply is connected, and supply voltage is switched into required input voltage；The protection location carries out current-limiting protection to the power panel；Institute The voltage of the corresponding out-put supply of sampling unit collection is stated, and is transmitted to the A/D converting units；The A/D converting units are by institute The voltage conversion for stating out-put supply is electric current and/or performance number, and the electric current and/or performance number are sent to the master control Plate.
- 6. a kind of chip testing method for monitoring abnormality, it is characterised in that comprise the following steps：Serial ports Monitoring instruction is triggered according to input signal, and test chip is monitored according to the serial ports Monitoring instruction of initiation；Serial ports number that test chip is sent, being transmitted by Multi-serial port modular converter and switch module is received by serial network interface According to；Judge whether the test chip is abnormal according to the serial data.
- 7. chip testing method for monitoring abnormality according to claim 6, it is characterised in that also include：According to input signal trigger current Monitoring instruction, and the current data according to the instruction of the current monitoring of initiation to test chip It is monitored；Obtain the current data of the test chip；Judge whether the test chip is abnormal according to the current data of the test chip.
- 8. chip testing method for monitoring abnormality according to claim 6, it is characterised in that described according to the serial data Judge whether abnormal step includes the test chip：Detect the serial data and whether there is default key parameter；When detecting that the serial data has default key parameter, judge whether the key parameter is abnormal.
- 9. a kind of computer equipment, including memory, processor and storage can be run on a memory and on a processor Computer program, it is characterised in that the chip testing described in claim any one of 6-8 is realized during the computing device program Method for monitoring abnormality.
- 10. a kind of computer-readable recording medium, is stored thereon with computer program, it is characterised in that the program is by processor The chip testing method for monitoring abnormality described in claim any one of 6-8 is realized during execution.
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| CN108519938A (en) * | 2018-04-13 | 2018-09-11 | 珠海全志科技股份有限公司 | Storage chip compatibility test method, system and test main frame |
| CN109753050A (en) * | 2019-01-28 | 2019-05-14 | 西安爱生技术集团公司 | A kind of Portable unmanned machine handling controller test macro and test method |
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| CN111459143A (en) * | 2020-04-26 | 2020-07-28 | 上海航天计算机技术研究所 | Multi-serial port communication self-closed loop detection system and method |
| CN111487524A (en) * | 2020-05-15 | 2020-08-04 | 上海华力微电子有限公司 | Universal chip test system, test method and storage medium |
| CN111487524B (en) * | 2020-05-15 | 2022-03-11 | 上海华力微电子有限公司 | Universal chip test system, test method and storage medium |
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| CN113484735A (en) * | 2021-07-30 | 2021-10-08 | 锐石创芯（深圳）科技有限公司 | Chip test gating module and chip test system |
| CN113484735B (en) * | 2021-07-30 | 2022-11-08 | 锐石创芯(深圳)科技股份有限公司 | Chip test gating module and chip test system |
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| CN116126738B (en) * | 2023-04-17 | 2023-07-21 | 紫金诚征信有限公司 | Interface abnormality identification method and device and electronic equipment |
| CN117517934A (en) * | 2024-01-04 | 2024-02-06 | 江苏优众微纳半导体科技有限公司 | Chip auxiliary test system and test method |
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