CN117517934B - Chip auxiliary test system and test method - Google Patents
Chip auxiliary test system and test method Download PDFInfo
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- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
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Abstract
The invention discloses a chip auxiliary test system and a test method, which relate to the technical field of chip test and solve the problem that the test analysis is not carried out on internal components of a chip, so that the test process is incomplete; and then analyzing the response condition of the normal chip to determine whether the internal components of the chip reach the standard, and then judging whether the components of the chip have the mutual influence or not aiming at the components which do not reach the standard, or determining the specific abnormal signal of the chip by the fact that the components are abnormal, so that the comprehensiveness of the chip in the test process is improved, the test effect is improved, and the comprehensiveness in the test process is ensured.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a chip auxiliary testing system and a chip auxiliary testing method.
Background
Chips, also known as integrated circuits or microcircuits, are miniature electronic devices, often used as part of computers or other electronic devices. It is a generic term for semiconductor element products, and is the heart and brain of electronic devices, enabling electrical control.
The application with publication number CN116136567A discloses a chip test auxiliary device, which is applied to a chip test system, the chip test system also comprises an ESD machine, the ESD machine comprises a latch up test board for bearing a chip to be tested, and the auxiliary device comprises a microprocessor, a pulse level generating circuit, a power input interface, a sampling circuit and an operational amplifier circuit; after detecting a trigger signal of the ESD machine, the microprocessor controls the pulse level generating circuit to release the pulse level to a pin of the chip to be tested; acquiring current on a pin of a chip to be tested, which is acquired by a sampling circuit, and current data transmitted by an operational amplifier circuit; and comparing and analyzing the current data and the pulse level current released by the pulse level generating circuit to finish the test.
When a specific test is conducted on a chip, corresponding test current is generally sent to the inside of the chip, the quality of the chip is determined based on the change of the test current in different environments and different application scenes, but the chip can complete a corresponding data verification process due to different response degrees of internal components, but the chip has two conditions of slowness or rapidness, and the chip performance is required to be assessed according to test data of the internal components of the chip in the test process mainly because the change of current change trend generated by the internal different components in a corresponding test voltage state causes that the response time of the chip is not timely.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a chip auxiliary test system and a test method, which solve the problem that the test process is not comprehensive because the test analysis is not carried out on the internal components of the chip.
In order to achieve the above purpose, the invention is realized by the following technical scheme: a chip-assisted test system, comprising:
the pin testing terminal adopts an IC integrated circuit to test the pin resistance of the chip, determines the resistance value of different pins of each chip, judges whether the pins in the chip are tested normally and determines a normal chip;
the chip response test end, carries on the voltage change response test processing to the normal chip, carries on the average adjustment to the test voltage, then confirms the output curve of its electric current, confirms the electric current output curve and the same time interval trend parameter of the voltage average curve is unanimous, if is unanimous, carries out the temperature change test end, if is inconsistent, carries out the assembly test analysis end, includes:
step-up or step-down processing is carried out on the test voltage, a group of change periods T are confirmed, and a voltage change curve is generated based on the time trend of the change periods T, wherein T is a preset value;
confirming the current parameter generated by the chip in the change period T, and generating a current change curve based on the time trend;
according to the generated voltage change curve, confirming the internal change trend point, wherein trend trends of line segments at the front end and the rear end of the change trend point are inconsistent, confirming a time interval between adjacent change trend points according to time trend, and confirming trend values of the internal curve of the time interval, wherein the trend values are slopes of the line segments in the time interval;
confirming curve line segments of the same time period from the current change curve based on the confirmed time interval, determining specific parameters of two endpoints of the selected curve line segment, marking current parameters of a front endpoint as D1, marking current parameters of a rear endpoint as D2, adopting trend values= (D2-D1)/(time difference), judging whether the trend values are consistent with the confirmed trend values in the corresponding time interval or not, if so, executing a temperature change test end, and if not, executing a component test analysis end;
the component test analysis end adopts the same test mode of the chip response test end to determine the unqualified components in the chip, and when the unqualified components in the chip are only one group, abnormal signals of the chip components are directly generated, and the specific mode is as follows:
determining current change curves generated by different components in the chip in the change period T, analyzing trend analysis by analyzing the current change curves and the voltage change curves of the whole chip, judging whether trend trends of curve line segments of the components in the same time period are consistent, if so, marking the components as standard reaching components, and if not, marking the components as non-standard reaching components;
when the number of the substandard components is more than or equal to 2, starting an analysis end of the different standard components, confirming voltage curves generated by the substandard components in the chip, determining whether conditions of mutual influence exist or not based on the change conditions of the two voltage curves of the two substandard components, and generating component mutual interference signals or chip component abnormal signals; comprising the following steps:
calibrating a voltage change curve generated in a change period T based on the chip as a standard curve;
calibrating a voltage change curve generated by two substandard components or a plurality of substandard components in the change period T as a secondary change curve;
based on trend values of different time periods in the standard curve, determining whether trend values of corresponding time periods in the secondary change curve are the same, if so, not processing, and if not, calibrating curve line segments with different trend values as abnormal line segments;
confirming abnormal time intervals among abnormal line segments, and then comparing the abnormal time intervals generated by different unqualified components in pairs to confirm the overlapping time intervals:
if the overlapping time interval is located in the two different abnormal time intervals and the duty ratio exceeds Y1, generating a component mutual interference signal directly through the signal end, and displaying, wherein Y1 is a preset value;
if the duty ratio of the coincidence time interval between two different abnormal time intervals does not exceed Y1, generating a chip component abnormal signal directly through the signal end, and directly displaying.
Preferably, the temperature change testing terminal tests the chip by adopting standard voltage, changes the temperature of the testing environment in real time, confirms the current parameter output by the normal chip, and judges whether the current parameter output by the normal chip belongs to a preset current standard interval; comprising the following steps:
defining a group of test periods, wherein the test period is a preset period, and determining the current parameter outputted by the test period, and marking as DL t Wherein t represents different time points within the test period;
validating all current parameters DL generated t If the current parameters do not belong to the current standard interval, generating a standard signal through the signal end, and if the current parameters do not belong to the current standard interval, generating a suboptimal signal through the signal end.
Preferably, a chip auxiliary test method includes:
testing the pin resistance of the chip by adopting an IC integrated circuit, and determining whether the resistance values of different pins of the chip reach the standard or not, thereby locking a normal chip or a fault chip;
performing voltage change response test processing on a normal chip, performing average voltage adjustment on the test voltage, and then confirming the current output curve of the test voltage, and confirming whether trend parameters of the current output curve and the voltage average curve in the same period are consistent or not, so that a subsequent execution end is locked;
aiming at the situation that trend parameters are inconsistent, determining the unqualified components in the chip in the same mode of voltage change response test processing, if the unqualified components exceed 2 groups, determining whether the situation of mutual influence exists based on the change situation of two voltage curves of the two unqualified components, and generating a component mutual interference signal or a chip component abnormal signal based on a determination result;
aiming at the condition that trend parameters are consistent, the chip is tested by adopting standard voltage, the temperature of a testing environment is changed in real time, and the current parameters output by the normal chip are confirmed, so that the performance state of the chip is determined, and a standard signal or a suboptimal signal is generated for external testers to check.
The invention provides a chip auxiliary test system and a test method. Compared with the prior art, the method has the following beneficial effects:
the invention primarily tests the pins of the chip to identify whether the resistance of the pins meets the standard, and then determines the normal chip based on the identification result;
then analyzing the response condition of the normal chip to determine whether the internal components of the chip reach the standard, and judging whether the components of the chip have the mutual influence or not aiming at the components which do not reach the standard, or determining the specific abnormal signal of the chip by the fact that the components are abnormal, so that the comprehensiveness of the chip in the test process is improved, the test effect is improved, and the comprehensiveness in the test process is ensured;
aiming at a chip without an unqualified component, carrying out temperature test treatment on the chip, judging the current reaction of the chip in different temperature states, generating corresponding current values, and identifying the specific performance of the chip based on the values, so that the overall test effect of the whole chip is improved, and the comprehensiveness of the test process is ensured.
Drawings
FIG. 1 is a schematic diagram of a principal frame of the present invention;
FIG. 2 is a schematic diagram showing a specific flow of the chip test according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Referring to fig. 1, the application provides a chip auxiliary test system, which includes a pin test end, a chip response test end, a component test analysis end, a different-standard component analysis end, a temperature change test end and a signal end;
the pin testing end is electrically connected with the chip response testing end and the signal end input node respectively, the chip response testing end is electrically connected with the component testing analysis end and the temperature change testing end input node respectively, the component testing analysis end is electrically connected with the different standard component analysis end input node, and the temperature change testing end and the different standard component analysis end are electrically connected with the signal end input node respectively;
the pin testing end adopts an IC integrated circuit to test the pin resistance of the chip, determines the resistance value of different pins of each chip, and based on the resistance value, judges whether the pins in the chip are tested normally and determines a normal chip, specifically, the adopted testing equipment is generally a universal meter, the internal voltage of the universal meter is not more than 6V, and the measuring range is preferably R multiplied by 100 or R multiplied by 1 k;
the substep of determining whether its internal pin test is normal includes:
confirming the pin resistance of the internal pin of the corresponding component of the chip and marking the pin resistance as R i Wherein i represents different components, R is determined i Whether the chip belongs to a preset resistance interval, if so, the chip is tested normally, and belongs to a normal chip, and a chip response test end is executed to perform response test processing on the normal chip, if so, a chip is presentThe group resistance value does not belong to the resistance value interval and belongs to the abnormal chip, and a chip abnormal signal is generated through the signal end, wherein the resistance value interval is a preset interval.
The chip responds to the test end, carries on the voltage change to respond to the test processing to the normal chip, carries on the equilibrium adjustment to the test voltage, confirm its output curve of the electric current, confirm the electric current output curve and voltage the same interval trend parameter of the equilibrium curve of electric current are unanimous, if unanimous, carry out the temperature change test end, if inconsistent, carry out the module and test the analysis end, in particular, in order to guarantee whether the numerical value between its chip internal components meets the standard, carry on the up-regulation or down-regulation to the numerical value of the voltage, its regulation numerical value will not exceed the load standard voltage of this chip, in carrying on the regulation, need to confirm its regulation mode, when the internal voltage of the normal chip rises gradually, the correspondent electric current produced should rise gradually too, its trend should be unanimous;
wherein the sub-step of validating comprises:
gradually lifting or gradually descending the test voltage, confirming a group of change periods T, and generating a voltage change curve based on the time trend of the change periods T, wherein T is a preset value, and the specific value of the voltage change curve is drawn by an operator according to experience;
confirming the current parameter generated by the chip in the change period T, and generating a current change curve based on the time trend;
according to the generated voltage change curve, confirming the internal change trend point, wherein the trend of line segments (namely the slope of the line segments) at the front end and the rear end of the change trend point are inconsistent, specifically, the change trend point is the point of change in the curve, when the voltage steadily climbs, the change trend does not change, when the voltage steadily climbs, the corresponding change trend point appears, the slope of the front end line segment is 3, the slope of the rear end line segment is 4, the point of change trend point is the point of change trend, the time interval between the adjacent change trend points is confirmed according to the time trend, and the trend value of the curve in the time interval is confirmed;
confirming curve line segments of the same time period from the current change curve based on the confirmed time interval, determining specific parameters of two endpoints of the selected curve line segment, marking current parameters of a front endpoint as D1, marking current parameters of a rear endpoint as D2, adopting trend values= (D2-D1)/(time difference), specifically, determining the trend values in the voltage change curve in the same way, wherein the time difference is the total difference value of the corresponding time interval, judging whether the trend values are consistent with the confirmed trend values in the corresponding time interval, if so, executing a temperature change test end, and if not, executing a component test analysis end;
specifically, when the voltage changes, the internal current will also change correspondingly, if the current trend is inconsistent with the voltage trend during the test, the maximum voltage that the chip internal components may bear will change, and the components will not reach the standard during the test, so that the abnormal components in the chip need to be confirmed, so that the components can be replaced later.
The component test analysis end adopts the same test mode of the chip response test end to determine the current change curve generated by different components in the chip in the change period T, analyzes trend analysis of the current change curve and the voltage change curve of the whole chip, judges whether trend of curve line segments of the components in the same time period is consistent, marks the components as standard components if the trend is consistent, and marks the components as non-standard components if the trend is inconsistent;
specifically, when the voltage is changed normally, the corresponding current generated by the components is changed correspondingly, when the current is changed, the trend change in the same time period is determined according to the change trend of the current, if the corresponding components in the chip are normal, the components comprise diodes, built-in resistors and other micro components, the trend change generated is consistent, if the corresponding components in the chip are abnormal or the internal voltage does not reach the standard, the trend of the generated current change is inconsistent, and the non-standard components can be directly determined by adopting the same mode;
when the number of the unqualified components in the chip is more than or equal to 2, starting an analysis end of the different standard components, confirming a voltage curve generated by the unqualified components in the chip in a change period T, determining whether a mutual influence exists or not based on the change conditions of the two voltage curves of the two unqualified components, generating a mutual interference signal of the components through a signal end if the mutual influence exists, displaying the mutual influence signal, generating an abnormal signal of the chip components, displaying the abnormal signal if the mutual influence signal does not exist, particularly, causing the mutual interference of the signals among the components if the unqualified components are arranged or welded, and forming the simultaneous fluctuation of the voltages among the two unqualified components in the mutual interference process of the signals, so as to confirm whether the mutual influence exists or not;
when only one group of the components does not reach the standard in the chip, directly generating a chip component abnormal signal;
wherein the substep of determining whether there is an interaction comprises:
calibrating a voltage change curve generated in a change period T based on the chip as a standard curve;
calibrating a voltage change curve generated by two substandard components or a plurality of substandard components in the change period T as a secondary change curve;
determining whether trend values of corresponding time periods in a secondary change curve are the same or not based on trend values of different time periods in a standard curve, if so, not processing, if not, calibrating curve line segments with different trend values as abnormal line segments, specifically, determining change trend points of the trend values in the same manner as the determination mode of the analysis process, determining time intervals and trend values based on the determined change trend points, and determining curve line segments of the same time period according to the time intervals, so as to determine whether the trend values are consistent or not;
confirming abnormal time intervals among abnormal line segments, and then comparing the abnormal time intervals generated by different unqualified components in pairs to confirm the overlapping time intervals:
if the overlapping time interval is located in the two different abnormal time intervals and the duty ratio exceeds Y1, generating a component mutual interference signal directly through the signal end, and displaying the component mutual interference signal; wherein Y1 is a preset value, the specific value is empirically determined by an operator, the value is generally 90%, and assuming that abnormal time intervals generated by two different substandard components are respectively 2-7 and 1-6, the generated coincidence time interval is 2-6, the occupation ratio of the abnormal time interval in the first group is 83% = 5/6, the occupation ratio of the abnormal time interval in the second group is 83%, and the judgment condition is not satisfied;
if the duty ratio of the coincidence time interval between two different abnormal time intervals does not exceed Y1, generating a chip component abnormal signal directly through the signal end, and directly displaying.
Example two
In the specific implementation process, compared with the first embodiment, the main difference is that the temperature test processing is mainly performed on the chip with consistent chip response test to determine whether the temperature test of the normal chip reaches the standard, and the temperature change test end executes the test operation;
the temperature change testing end is used for testing the chip by adopting standard voltage, changing the temperature of the testing environment in real time, confirming the current parameters output by the normal chip, and judging whether the current parameters output by the normal chip belong to a preset current standard interval or not;
wherein, the substeps of judging are as follows:
defining a group of test periods, wherein the test periods are preset periods, the specific values of the test periods are determined by operators according to experience, and the current parameters output by the test periods are confirmed and marked as DL t Wherein t represents different time points within the test period;
validating all current parameters DL generated t Whether the current is in the current standard interval or not, if the current is in the current standard interval, generating a standard signal through a signal end, wherein the standard signal represents that the chip is a standard chip, and if a group of electricity existsIf the flow parameter does not belong to the current standard interval, generating a suboptimal signal through a signal end, wherein the suboptimal signal represents that the chip cannot act on a complex temperature use scene, but can be used in a normal working scene, and the quality of the chip is slightly inferior to that of a standard chip;
when the temperature limit changes, the resistance value inside the chip can correspondingly change, the corresponding current can be changed, when the current changes and does not reach the standard, the performance of the chip is required to be questioned, the overall operation performance of the chip is not up to the standard, and when the resistance value of the chip changes too much, the effect of the chip is deteriorated when the chip is normally used in the later stage, so that the chip is required to be subjected to temperature test treatment to ensure that the performance of the chip is not greatly influenced and changed in the limit temperature state.
Example III
A chip auxiliary test method comprises the following steps of;
testing the pin resistance of the chip by adopting an IC integrated circuit, and determining whether the resistance values of different pins of the chip reach the standard or not, thereby locking a normal chip or a fault chip;
performing voltage change response test processing on a normal chip, performing average voltage adjustment on the test voltage, and then confirming the current output curve of the test voltage, and confirming whether trend parameters of the current output curve and the voltage average curve in the same period are consistent or not, so that a subsequent execution end is locked;
aiming at the situation that trend parameters are inconsistent, determining the unqualified components in the chip in the same mode of voltage change response test processing, if the unqualified components exceed 2 groups, determining whether the situation of mutual influence exists based on the change situation of two voltage curves of the two unqualified components, and generating a component mutual interference signal or a chip component abnormal signal based on a determination result;
aiming at the condition that trend parameters are consistent, the chip is tested by adopting standard voltage, the temperature of a testing environment is changed in real time, and the current parameters output by the normal chip are confirmed, so that the performance state of the chip is determined, and a standard signal or a suboptimal signal is generated for external testers to check.
Example IV
This embodiment includes all of the three embodiments described above in the specific implementation.
Some of the data in the above formulas are numerical calculated by removing their dimensionality, and the contents not described in detail in the present specification are all well known in the prior art.
The above embodiments are only for illustrating the technical method of the present invention and not for limiting the same, and it should be understood by those skilled in the art that the technical method of the present invention may be modified or substituted without departing from the spirit and scope of the technical method of the present invention.
Claims (8)
1. A chip-assisted test system, comprising:
the pin testing terminal adopts an IC integrated circuit to test the pin resistance of the chip, determines the resistance value of different pins of each chip, judges whether the pins in the chip are tested normally and determines a normal chip;
the chip response test end, carries on the voltage change response test processing to the normal chip, carries on the average adjustment to the test voltage, then confirms the output curve of its electric current, confirms the electric current output curve and the same time interval trend parameter of the voltage average curve is unanimous, if is unanimous, carries out the temperature change test end, if is inconsistent, carries out the assembly test analysis end, includes:
step-up or step-down processing is carried out on the test voltage, a group of change periods T are confirmed, and a voltage change curve is generated based on the time trend of the change periods T, wherein T is a preset value;
confirming the current parameter generated by the chip in the change period T, and generating a current change curve based on the time trend;
according to the generated voltage change curve, confirming the internal change trend point, wherein trend trends of line segments at the front end and the rear end of the change trend point are inconsistent, confirming a time interval between adjacent change trend points according to time trend, and confirming trend values of the internal curve of the time interval, wherein the trend values are slopes of the line segments in the time interval;
confirming curve line segments of the same time period from the current change curve based on the confirmed time interval, determining specific parameters of two endpoints of the selected curve line segment, marking current parameters of a front endpoint as D1, marking current parameters of a rear endpoint as D2, adopting trend values= (D2-D1)/(time difference), judging whether the trend values are consistent with the confirmed trend values in the corresponding time interval or not, if so, executing a temperature change test end, and if not, executing a component test analysis end;
the component test analysis end adopts the same test mode of the chip response test end to determine the unqualified components in the chip, and when only one group of unqualified components in the chip is provided, abnormal signals of the chip components are directly generated;
when the number of the unqualified components is more than or equal to 2, an analysis end of the different standard components is started, voltage curves generated by the unqualified components in the chip are confirmed, whether the conditions of mutual influence exist or not is determined based on the change conditions of the two voltage curves of the two unqualified components, and component mutual interference signals or chip component abnormal signals are generated.
2. The chip assist test system according to claim 1, wherein the sub-step of determining whether the internal pin test is normal at the pin test terminal comprises:
confirming the pin resistance of the internal pin of the corresponding component of the chip and marking the pin resistance as R i Wherein i represents different components, R is determined i Whether the chip belongs to a preset resistance interval or not, if the chip belongs to the preset resistance interval, the chip is tested normally, the chip belongs to a normal chip, a chip response test end is executed to perform response test processing on the normal chip, and if a group of resistance values do not belong to the resistance interval, the resistance interval is the preset interval, a chip abnormal signal is generated through a signal end.
3. The chip auxiliary test system according to claim 1, wherein the specific manner of determining the unqualified component by the component test analysis end is:
and determining the current change curves generated by different components in the chip in the change period T, analyzing trend analysis by analyzing the current change curves and the voltage change curves of the whole chip, judging whether trend trends of curve line segments of the components in the same time period are consistent, if so, marking the components as standard reaching components, and if not, marking the components as non-standard reaching components.
4. A chip assist test system according to claim 3 wherein the substep of determining whether there is an interaction at the analysis end of the differential label assembly comprises:
calibrating a voltage change curve generated in a change period T based on the chip as a standard curve;
calibrating a voltage change curve generated by two substandard components or a plurality of substandard components in the change period T as a secondary change curve;
based on trend values of different time periods in the standard curve, determining whether trend values of corresponding time periods in the secondary change curve are the same, if so, not processing, and if not, calibrating curve line segments with different trend values as abnormal line segments;
confirming abnormal time intervals among abnormal line segments, and then comparing the abnormal time intervals generated by different unqualified components in pairs to confirm the overlapping time intervals:
if the overlapping time period is located in the two different abnormal time intervals and the duty ratio exceeds Y1, generating a component mutual interference signal directly through the signal end, and displaying, wherein Y1 is a preset value.
5. The chip assist test system according to claim 1, wherein the substep of determining whether there is an interaction further comprises:
if the duty ratio of the coincidence time interval between two different abnormal time intervals does not exceed Y1, generating a chip component abnormal signal directly through the signal end, and directly displaying.
6. The system of claim 1, wherein the temperature change testing terminal tests the chip with standard voltage, changes the temperature of the testing environment in real time, confirms the current parameter outputted by the normal chip, and determines whether the outputted current parameter belongs to a preset current standard interval.
7. The chip assist test system according to claim 6, wherein the substep of determining whether the output current parameter belongs to a preset current standard interval by the temperature change test terminal comprises:
defining a group of test periods, wherein the test period is a preset period, and determining the current parameter outputted by the test period, and marking as DL t Wherein t represents different time points within the test period;
validating all current parameters DL generated t If the current parameters do not belong to the current standard interval, generating a standard signal through the signal end, and if the current parameters do not belong to the current standard interval, generating a suboptimal signal through the signal end.
8. A chip-assisted test method, which is applied to a chip-assisted test system according to any one of claims 1 to 7, comprising:
testing the pin resistance of the chip by adopting an IC integrated circuit, and determining whether the resistance values of different pins of the chip reach the standard or not, thereby locking a normal chip or a fault chip;
performing voltage change response test processing on a normal chip, performing average voltage adjustment on the test voltage, and then confirming the current output curve of the test voltage, and confirming whether trend parameters of the current output curve and the voltage average curve in the same period are consistent or not, so that a subsequent execution end is locked;
aiming at the situation that trend parameters are inconsistent, determining the unqualified components in the chip in the same mode of voltage change response test processing, if the unqualified components exceed 2 groups, determining whether the situation of mutual influence exists based on the change situation of two voltage curves of the two unqualified components, and generating a component mutual interference signal or a chip component abnormal signal based on a determination result;
aiming at the condition that trend parameters are consistent, the chip is tested by adopting standard voltage, the temperature of a testing environment is changed in real time, and the current parameters output by the normal chip are confirmed, so that the performance state of the chip is determined, and a standard signal or a suboptimal signal is generated for external testers to check.
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