CN116665748A - Automatic test equipment for flash memory chip and test method thereof - Google Patents
Automatic test equipment for flash memory chip and test method thereof Download PDFInfo
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- CN116665748A CN116665748A CN202310669887.2A CN202310669887A CN116665748A CN 116665748 A CN116665748 A CN 116665748A CN 202310669887 A CN202310669887 A CN 202310669887A CN 116665748 A CN116665748 A CN 116665748A
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- 238000012360 testing method Methods 0.000 title claims abstract description 201
- 238000010998 test method Methods 0.000 title abstract description 5
- 230000002159 abnormal effect Effects 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 22
- 230000001133 acceleration Effects 0.000 claims abstract description 19
- 238000012545 processing Methods 0.000 claims description 24
- 238000013142 basic testing Methods 0.000 claims description 18
- 230000001052 transient effect Effects 0.000 claims description 11
- 230000003068 static effect Effects 0.000 claims description 10
- 238000012544 monitoring process Methods 0.000 claims description 6
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 5
- 230000000630 rising effect Effects 0.000 claims description 3
- 230000006978 adaptation Effects 0.000 claims 1
- 238000010200 validation analysis Methods 0.000 claims 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C2029/5004—Voltage
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The application discloses automatic test equipment and a test method thereof for a flash memory chip, which relate to the technical field of chip test, solve the technical problems that the flash memory chip in a normal state is not analyzed in multiple aspects, the reliability of the flash memory chip is not fully tested, the flash memory chip is divided into normal chips or abnormal chips according to specific parameters, the flash memory chip is subjected to high-temperature and voltage acceleration test aiming at the normal chips, whether the normal chips have unreliable conditions in the using process is judged according to test values, the running is adopted, the normal chips are subjected to the multiple-aspect test, the integrity and the accuracy of the chip test are improved, the limit test is carried out on the abnormal chips, the output parameters of the abnormal chips are determined, whether the parameters meet the regulations are analyzed, whether the abnormal chips are in a fault state or not is judged according to test results, and the integrity of the abnormal chips is improved.
Description
Technical Field
The application belongs to the technical field of chip testing, and particularly relates to automatic testing equipment and a testing method for a flash memory chip.
Background
The BIOS on the motherboard is mostly manufactured by using Flash Memory, and is translated into Chinese, namely a Flash Memory, which is commonly called as a Flash Memory, and is called as a Flash Memory for short; the flash memory disk is a mobile storage product, can be used for storing data files in any format, is convenient to carry, and is a personal 'data mobile center'.
The application with the patent publication number of CN105334448A relates to an automatic chip testing system. The system comprises an automated test control device for the chip and an automated test board for the chip. The automatic test control device for chips includes: the test control module is used for generating a test program selection command and sending the test program selection command to the automatic test board, wherein the test program selection command is used for selecting a test subprogram from the automatic test program, and the automatic test program comprises more than two test subprograms; the test result receiving module is used for receiving the test result sent by the automatic test board; the application is used for avoiding repeated programming of different test programs, thereby avoiding error in test, saving time, being easy to maintain, reducing cascade connection among boards and avoiding poor signal quality caused by cascade connection among multi-stage boards.
In the process of performing automatic test on a flash memory chip, whether the corresponding flash memory chip is normal or not is generally determined according to specific parameters of the flash memory chip, if the flash memory chip is in a normal state, no processing is needed, if the flash memory chip is in an abnormal state, an operator is notified, and an abnormal reason is analyzed, but for the flash memory chip in the normal state, multiple aspects of analysis are not performed, the reliability of the flash memory chip is not clear, and the whole test is not comprehensive.
Disclosure of Invention
The present application aims to solve at least one of the technical problems existing in the prior art; therefore, the application provides an automatic test device and a test method for a flash memory chip, which are used for solving the technical problems that the flash memory chip in a normal state is not analyzed in multiple aspects, the reliability of the flash memory chip is not clear, and the whole test is not comprehensive.
To achieve the above object, an embodiment according to a first aspect of the present application proposes an automated test equipment for a flash memory chip, comprising:
the test parameter acquisition end is used for acquiring basic test data generated in the test process of the flash memory chip and transmitting the acquired basic test data into the test analysis center, wherein the basic test data comprises output parameters generated in a standard test voltage state;
the parameter analysis unit is used for analyzing and confirming the basic test data according to the acquired basic test data, judging whether the corresponding flash memory chip is an abnormal chip or a normal chip, generating a comprehensive test signal if the flash memory chip is the normal chip, and generating an instant test signal if the flash memory chip is the abnormal chip, wherein the specific mode is as follows:
marking the generated output parameter as SC i Wherein i represents different flash memory chips;
directly extracting check preset interval from the storage unit, wherein the end values of both sides of the check preset interval are preset values, when SC i When the E is checked in the preset interval, the corresponding flash memory chip is marked as a normal chip, a comprehensive test signal is generated, the comprehensive test signal is transmitted to a comprehensive test terminal, and whenWhen checking a preset interval, marking the corresponding flash memory chip as an abnormal chip, generating an instant test signal, and transmitting the instant test signal into the ESD electrostatic test terminal;
the comprehensive test end is used for comprehensively testing the normal chip according to the comprehensive test signal, and comprises a high-temperature test unit and a voltage acceleration test unit, and the high-temperature test unit is used for carrying out high-temperature test on the normal chip under the normal working state, and the specific mode is as follows:
the standard test voltage is kept unchanged, the temperature of the external test environment of the flash memory chip is changed, and the environment temperature is continuously increased to a specified value, wherein the specific value of the specified value is drawn up by an operator according to experience;
defining a group of monitoring periods T, wherein T is a preset value, the T is generally 5min, a plurality of groups of specific parameters output by a normal chip are recorded in the monitoring periods T, and a group of recording intervals are constructed according to the recorded maximum value and minimum value;
comparing the recorded interval with the check preset interval, and when the recorded interval epsilon is compared with the check preset interval, not performing any processing, otherwise, generating a high-temperature unreliable signal through a signal generating unit, and transmitting the high-temperature unreliable signal into a display unit for display;
the method comprises the steps of performing acceleration adjustment on working voltage of a normal chip in a normal working state through a voltage acceleration test unit, confirming specific parameters generated by the normal chip, analyzing the reliability of the normal chip according to the comprehensive results of a high-temperature test and a voltage acceleration test, generating corresponding signals through a signal generation unit, and displaying through a display unit, wherein the specific modes are as follows:
confirming original standard test voltage, rapidly and randomly changing the standard test voltage in the test process, continuously rising or falling, recording output parameters and generated in the random change process, and marking the output parameters and the output parameters as SS k Wherein k represents different time points;
will correspond to the output parameter SS k The corresponding test voltage is marked as DY k By DY k ÷SS k ＝BZ k Obtaining the standard change parameter BZ k Binding the generated plurality of standard change parameters to generate a data packet;
extracting standard change interval from the memory unit, wherein the end values of both ends of the interval are preset values, the specific values are determined by an operator according to experience, and a plurality of standard change parameters BZ existing in the data packet are obtained k Comparing with the standard change interval, when all the standard change parameters BZ k When the voltage test signals belong to the standard change interval, no processing is performed, otherwise, a voltage test unreliable signal is generated through a signal generating unit, and the voltage test unreliable signal is displayed through a display unit;
the ESD static testing end performs transient voltage self-adaptive test on the flash memory chip marked as the abnormal chip, analyzes and confirms the corresponding transient current, analyzes and confirms whether the corresponding transient current reaches the standard, generates the corresponding processing signal according to the analysis result, displays the processing signal through the display unit, and analyzes and confirms whether the corresponding abnormal chip is in a fault state, and the specific mode is as follows:
confirming an original standard test voltage, and instantly increasing the standard test voltage to a maximum test voltage parameter, wherein the maximum test voltage parameter is a preset value, and recording an instant current parameter output by a flash memory chip;
marking an instantaneous current parameter as DL, marking a maximum test voltage parameter as YD, obtaining a judgment trend value QS by adopting YD/DL=QS, comparing the QS with a standard change interval, generating an abnormal signal through a signal generating unit when the QS is epsilon from the standard change interval, displaying the abnormal signal through a display unit, and when the abnormal signal is epsilon from the standard change interval, displaying the abnormal signal by a display unitWhen the standard changes the interval, a fault signal is generated by the signal generating unit and displayed by the display unit.
Compared with the prior art, the application has the beneficial effects that: according to specific parameters, the flash memory chip is divided into a normal chip or an abnormal chip, high temperature and voltage acceleration tests are conducted on the normal chip, whether the normal chip has unreliable conditions in the use process or not is judged according to test values, and the normal chip is tested in multiple aspects by adopting the running, so that the comprehensiveness and accuracy of the chip test are improved;
and aiming at the abnormal chip, carrying out limit test on the abnormal chip, determining the output parameter of the abnormal chip, analyzing whether the parameter meets the specification, judging whether the abnormal chip is in a fault state according to the test result, and improving the comprehensive degree of the abnormal chip, if the abnormal chip is only in the abnormal state, directly maintaining the abnormal chip, and if the abnormal chip is in the fault state, scrapping the abnormal chip, improving the accuracy of numerical analysis without manual intervention.
Drawings
FIG. 1 is a schematic diagram of a principal frame of the present application;
FIG. 2 is a schematic flow chart of the method of the present application.
Detailed Description
The technical solutions of the present application will be clearly and completely described in connection with the embodiments, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Example 1
Referring to fig. 1, the application provides an automated test apparatus for a flash memory chip, comprising a test collection end, a test analysis center and a display unit, wherein the test collection end is electrically connected with an input end of the test analysis center, and the test analysis center is electrically connected with an input end of the display unit;
the test analysis center comprises a parameter analysis unit, a storage unit, a comprehensive test end, an ESD static test end and a signal generation unit, wherein the parameter analysis unit is electrically connected with the comprehensive test end and the ESD static test end input end, the storage unit is respectively electrically connected with the parameter analysis unit, the ESD static test end and the comprehensive test end input end, the comprehensive test end comprises a high-temperature test unit and a voltage acceleration test unit, and the comprehensive test end and the ESD static test end are in telecommunication connection with the signal generation unit input end;
the test parameter acquisition end is used for acquiring basic test data generated in the test process of the flash memory chip and transmitting the acquired basic test data into the test analysis center, wherein the basic test data comprises output parameters generated in a standard test voltage state, and specific values of the standard test voltage are drawn by an operator according to experience and are generally standard voltages in a normal working state of the flash memory chip;
the parameter analysis unit is used for analyzing and confirming the basic test data according to the acquired basic test data and judging whether the corresponding flash memory chip is an abnormal chip or a normal chip, wherein the specific mode for analyzing and confirming is as follows:
marking the generated output parameter as SC i Wherein i represents different flash memory chips;
directly extracting the checking preset interval from the storage unit, wherein the end values of both sides of the checking preset interval are preset values, the specific value is drawn by an operator according to experience, and when SC i When the E is checked in the preset interval, the corresponding flash memory chip is marked as a normal chip, a comprehensive test signal is generated, the comprehensive test signal is transmitted to a comprehensive test terminal, and whenWhen checking the preset interval, marking the corresponding flash memory chip as an abnormal chip, generating an instant test signal, and transmitting the instant test signal into the ESD static test terminal.
The comprehensive test terminal is used for comprehensively testing the normal chip according to the comprehensive test signal, carrying out high-temperature test on the normal chip under the normal working state through the high-temperature test unit, carrying out acceleration adjustment on the working voltage of the normal chip under the normal working state through the voltage acceleration test unit, confirming specific parameters generated by the normal chip, analyzing the reliability of the normal chip according to the comprehensive results of the high-temperature test and the voltage acceleration test, generating corresponding signals through the signal generation unit, and carrying out display through the display unit, wherein the specific mode of carrying out the high-temperature test by the high-temperature test unit is as follows:
the standard test voltage is kept unchanged, the temperature of the external test environment of the flash memory chip is changed, and the environment temperature is continuously increased to a specified value, wherein the specific value of the specified value is drawn up by an operator according to experience;
defining a group of monitoring periods T, wherein T is a preset value, the T is generally 5min, a plurality of groups of specific parameters output by a normal chip are recorded in the monitoring periods T, and a group of recording intervals are constructed according to the recorded maximum value and minimum value;
and comparing the recorded interval with the check preset interval, and when the recorded interval epsilon is compared with the check preset interval, not performing any processing, otherwise, generating a high-temperature unreliable signal through a signal generating unit and transmitting the high-temperature unreliable signal into a display unit for display.
The specific mode for carrying out the voltage acceleration test is as follows:
confirming original standard test voltage, rapidly and randomly changing the standard test voltage in the test process, continuously rising or falling, recording output parameters and generated in the random change process, and marking the output parameters and the output parameters as SS k Wherein k represents different time points;
will correspond to the output parameter SS k The corresponding test voltage is marked as DY k By DY k ÷SS k ＝BZ k Obtaining the standard change parameter BZ k Binding the generated plurality of standard change parameters to generate a data packet;
extracting standard change interval from the memory unit, wherein the end values of both ends of the interval are preset values, the specific values are determined by an operator according to experience, and a plurality of standard change parameters BZ existing in the data packet are obtained k Comparing with the standard change interval, when all the standard change parameters BZ k And when the voltage test signal belongs to the standard change interval, no processing is performed, otherwise, the voltage test unreliable signal is generated through the signal generating unit and displayed through the display unit for an external operator to check.
Example two
The ESD static testing end performs transient voltage self-adaptive test on the flash memory chip marked as the abnormal chip, analyzes and confirms corresponding transient current, analyzes and confirms whether the corresponding transient current meets the standard, generates corresponding processing signals according to analysis results, displays the processing signals through the display unit, and analyzes and confirms whether the corresponding abnormal chip is in a fault state, wherein the specific mode of performing the transient voltage self-adaptive test is as follows:
confirming an original standard test voltage, and instantly increasing the standard test voltage to a maximum test voltage parameter, wherein the maximum test voltage parameter is a preset value, the specific value is drawn by an operator according to experience, and instant current parameters output by a flash memory chip are recorded;
marking an instantaneous current parameter as DL, marking a maximum test voltage parameter as YD, obtaining a judging trend value QS by adopting YD/DL=QS, comparing the QS with a standard change interval, when the QS is in an epsilon standard change interval, specifically, the standard change interval is specifically described in the first embodiment, an abnormal signal is generated by a signal generating unit and displayed by a display unit, an external operator knows that the flash memory chip is an abnormal chip, maintenance and detection are needed, and when the QS is in an epsilon standard change interval, the abnormal signal is generated by the signal generating unit and displayed by the display unitWhen the standard changes the interval, generating a fault signal through the signal generating unit, displaying the fault signal through the display unit, and checking by an external operator to obtain that the flash memory chip is the fault signal in time, wherein the fault signal needs to be dealt with in time;
the signal generating unit generates different processing signals according to the test results of the comprehensive test end and the ESD static test end, displays the processing signals through the display unit, and allows external personnel to check the processing signals to make corresponding measures in time.
Example III
The application provides a test method of automatic test equipment for a flash memory chip, which comprises the following steps:
step one, according to basic test data generated in the test process, confirming whether the flash memory chip to be tested is a normal chip or an abnormal chip;
step two, comprehensively testing a normal chip, keeping the original voltage value unchanged, changing the temperature of the external environment of the flash memory chip, increasing the temperature to a specified value, confirming output parameters and analyzing and evaluating after the temperature is increased to the corresponding specified value, and judging whether the flash memory chip is reliable or not in a high-temperature environment;
step three, performing voltage acceleration test processing on the normal chip, taking an original voltage value as an initial voltage, randomly changing voltage parameters to enable the voltage value to continuously rise or fall rapidly, recording randomly generated output parameters, analyzing whether the output parameters accord with regulations, and judging whether the flash memory chip is reliable under the rapid change of the voltage value according to specific results;
and fourthly, aiming at the abnormal chip, performing self-test processing by adopting an instantaneous voltage self-adaptive test signal, recording instantaneous current parameters generated in the test processing process, analyzing whether the instantaneous current parameters reach the standard, generating fault signals if the instantaneous current parameters do not reach the standard, displaying the fault signals, checking by an external operator, generating abnormal signals if the instantaneous current parameters reach the standard, and displaying the abnormal signals.
Example IV
In the implementation process of this embodiment, the implementation contents of all embodiments one, two and three are included, and unified implementation is performed.
The partial data in the formula are all obtained by removing dimension and taking the numerical value for calculation, and the formula is a formula closest to the real situation obtained by simulating a large amount of collected data through software; the preset parameters and the preset threshold values in the formula are set by those skilled in the art according to actual conditions or are obtained through mass data simulation.
The above embodiments are only for illustrating the technical method of the present application and not for limiting the same, and it should be understood by those skilled in the art that the technical method of the present application may be modified or substituted without departing from the spirit and scope of the technical method of the present application.
Claims (7)
1. An automated test equipment for flash memory chips, comprising:
the test parameter acquisition end is used for acquiring basic test data generated in the test process of the flash memory chip and transmitting the acquired basic test data into the test analysis center, wherein the basic test data comprises output parameters generated in a standard test voltage state;
the parameter analysis unit is used for analyzing and confirming the basic test data according to the acquired basic test data, judging whether the corresponding flash memory chip is an abnormal chip or a normal chip, generating a comprehensive test signal if the flash memory chip is the normal chip, and generating an instant test signal if the flash memory chip is the abnormal chip;
the comprehensive testing end carries out comprehensive testing on the normal chip according to the comprehensive testing signal, the comprehensive testing end comprises a high-temperature testing unit and a voltage acceleration testing unit, the high-temperature testing unit is used for carrying out high-temperature testing on the normal chip in a normal working state, the voltage acceleration testing unit is used for carrying out acceleration adjustment on the working voltage of the normal chip in the normal working state, specific parameters generated by the normal chip are confirmed, the reliability of the normal chip is analyzed according to the comprehensive results of the high-temperature testing and the voltage acceleration testing, the corresponding signal is generated through the signal generating unit, and the display unit is used for displaying the signal;
and the ESD static testing end performs transient voltage self-adaptive test on the flash memory chip marked as the abnormal chip, analyzes and confirms the corresponding transient current, analyzes and confirms whether the corresponding transient current reaches the standard, generates a corresponding processing signal according to the analysis result, displays the processing signal through the display unit, and analyzes and confirms whether the corresponding abnormal chip is in a fault state.
2. The automated test equipment for flash memory chips of claim 1, wherein the parameter analysis unit performs the analysis and validation of the basic test data in the following specific ways:
marking the generated output parameters as SCi, wherein i represents different flash memory chips;
directly extracting a checking preset interval from the storage unit, wherein the end values of both sides of the checking preset interval are preset values, marking the corresponding flash memory chip as a normal chip when SCi epsilon is used for checking the preset interval, generating a comprehensive test signal, transmitting the comprehensive test signal to a comprehensive test end, and whenWhen checking the preset interval, marking the corresponding flash memory chip as an abnormal chip, generating an instant test signal, and transmitting the instant test signal into the ESD static test terminal.
3. The automated test equipment for flash memory chips of claim 2, wherein the high temperature test unit performs the high temperature test in the following specific manner:
the standard test voltage is kept unchanged, the temperature of the external test environment of the flash memory chip is changed, and the environment temperature is continuously increased to a specified value, wherein the specific value of the specified value is drawn up by an operator according to experience;
defining a group of monitoring periods T, wherein T is a preset value, the T is generally 5min, a plurality of groups of specific parameters output by a normal chip are recorded in the monitoring periods T, and a group of recording intervals are constructed according to the recorded maximum value and minimum value;
and comparing the recorded interval with the check preset interval, and when the recorded interval epsilon is compared with the check preset interval, not performing any processing, otherwise, generating a high-temperature unreliable signal through a signal generating unit and transmitting the high-temperature unreliable signal into a display unit for display.
4. The automated test equipment for flash memory chips of claim 2, wherein the voltage acceleration test unit performs the voltage acceleration test in the following specific manner:
confirming an original standard test voltage, changing the standard test voltage in the test process rapidly and randomly, continuously rising or falling, recording output parameters and generated in the random change process, and marking the output parameters and the output parameters as SSk, wherein k represents different time points;
marking a test voltage corresponding to the corresponding output parameter SSk as DYk, obtaining a standard change parameter BZk by DYk/SSk=BZk, binding the generated plurality of standard change parameters, and generating a data packet;
and extracting a standard change interval from the storage unit, wherein the end values at the two ends of the interval are preset values, the specific values are drawn by an operator according to experience, a plurality of standard change parameters BZk existing in the data packet are compared with the standard change interval, when all the standard change parameters BZk belong to the standard change interval, no processing is performed, otherwise, an unreliable voltage test signal is generated through the signal generation unit, and the unreliable voltage test signal is displayed through the display unit.
5. The automated test equipment for flash memory chips of claim 4, wherein said ESD electrostatic test terminal performs said transient voltage adaptation test in the following manner:
confirming an original standard test voltage, and instantly increasing the standard test voltage to a maximum test voltage parameter, wherein the maximum test voltage parameter is a preset value, and recording an instant current parameter output by a flash memory chip;
marking an instantaneous current parameter as DL, marking a maximum test voltage parameter as YD, obtaining a judgment trend value QS by adopting YD/DL=QS, comparing the QS with a standard change interval, generating an abnormal signal through a signal generating unit when the QS is epsilon from the standard change interval, displaying the abnormal signal through a display unit, and when the abnormal signal is epsilon from the standard change interval, displaying the abnormal signal by a display unitWhen the standard changes the interval, a fault signal is generated by the signal generating unit and displayed by the display unit.
6. The automated test equipment for flash memory chips of claim 1, wherein the signal generating unit generates different processing signals according to test results of the integrated test terminal and the ESD electrostatic test terminal, and displays the processing signals through the display unit.
7. An automated testing method for flash memory chips, which is applied to the automated testing agency of any one of claims 1 to 6, comprising the steps of:
step one, according to basic test data generated in the test process, confirming whether the flash memory chip to be tested is a normal chip or an abnormal chip;
step two, comprehensively testing a normal chip, keeping the original voltage value unchanged, changing the temperature of the external environment of the flash memory chip, increasing the temperature to a specified value, confirming output parameters and analyzing and evaluating after the temperature is increased to the corresponding specified value, and judging whether the flash memory chip is reliable or not in a high-temperature environment;
step three, performing voltage acceleration test processing on the normal chip, taking an original voltage value as an initial voltage, randomly changing voltage parameters to enable the voltage value to continuously rise or fall rapidly, recording randomly generated output parameters, analyzing whether the output parameters accord with regulations, and judging whether the flash memory chip is reliable under the rapid change of the voltage value according to specific results;
and fourthly, aiming at the abnormal chip, performing self-test processing by adopting an instantaneous voltage self-adaptive test signal, recording instantaneous current parameters generated in the test processing process, analyzing whether the instantaneous current parameters reach the standard, generating fault signals if the instantaneous current parameters do not reach the standard, displaying the fault signals, checking by an external operator, generating abnormal signals if the instantaneous current parameters reach the standard, and displaying the abnormal signals.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117471288A (en) * | 2023-12-20 | 2024-01-30 | 俐玛光电科技(北京)有限公司 | Test data analysis method and device, electronic equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117471288A (en) * | 2023-12-20 | 2024-01-30 | 俐玛光电科技(北京)有限公司 | Test data analysis method and device, electronic equipment and storage medium |
| CN117471288B (en) * | 2023-12-20 | 2024-03-15 | 俐玛光电科技(北京)有限公司 | Automatic analysis method and device for test data, electronic equipment and storage medium |
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