CN110888042B - Method and equipment for testing ASIC chip wafer and computer storage medium - Google Patents
Method and equipment for testing ASIC chip wafer and computer storage medium Download PDFInfo
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- CN110888042B CN110888042B CN201911255409.7A CN201911255409A CN110888042B CN 110888042 B CN110888042 B CN 110888042B CN 201911255409 A CN201911255409 A CN 201911255409A CN 110888042 B CN110888042 B CN 110888042B
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- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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Abstract
The invention discloses a test method of an ASIC chip wafer, which is applied to test equipment, wherein the test equipment is in communication connection with a test board; the test method comprises the following steps: when a chip test request is received, obtaining the test quantity corresponding to the chip test request, and connecting ASIC chips of the test quantity to a test board; sending the on-off test signal to the ASIC chip through the initialized test board to obtain on-off test data between the ASIC chip and the test board; if the on-off test data is normal, sending a performance test signal to the ASIC chip through the test board to obtain the performance test data of the ASIC chip; and analyzing the performance test data to obtain a test result of the ASIC chip. The invention also discloses a test device and a computer storage medium for the ASIC chip wafer. The invention improves the test efficiency of batch ASIC chips.
Description
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to a method and an apparatus for testing an ASIC chip wafer, and a computer storage medium.
Background
An ASIC (Integrated Circuit) chip refers to an Integrated Circuit chip designed and manufactured according to the requirements of a Specific user and the needs of a Specific electronic system.
The ASIC chip is characterized in that the ASIC chip is designed and formed, whether the ASIC chip is designed as the same as a Field Programmable Gate Array (FPGA) or not needs to be determined, so that the ASIC chip needs to be tested, the current test equipment determines a test signal according to the information of the ASIC chip and sends the test signal to the ASIC chip for carrying out ASIC chip wafer test, and the test mode is only suitable for testing a small number of ASIC chips, and if the batch of ASIC chips need to be tested, the test efficiency of the batch of ASIC chips is low.
Disclosure of Invention
The invention mainly aims to provide a method and equipment for testing an ASIC chip wafer and a computer storage medium, and aims to solve the technical problem of low test efficiency of the current batch ASIC chips.
In order to achieve the purpose, the invention provides a test method of an ASIC chip wafer, which is applied to test equipment, wherein the test equipment is in communication connection with a test board;
the test method of the ASIC chip wafer comprises the following steps:
when a chip test request is received, obtaining the test quantity corresponding to the chip test request, and connecting the ASIC chips of the test quantity to the test board;
sending an on-off test signal to the ASIC chip through the initialized test board to obtain on-off test data between the ASIC chip and the test board;
if the on-off test data is normal, sending a performance test signal to the ASIC chip through the test board to obtain performance test data of the ASIC chip;
and analyzing the performance test data to obtain a test result of the ASIC chip.
In an embodiment, after the step of obtaining a test quantity corresponding to a chip test request when the chip test request is received and connecting ASIC chips of the test quantity to the test board, the method includes:
restoring a signal control board and a relay control board in the test board to default values so as to initialize the test board;
when the initialization of the test board is completed, configuring test signals for data channels associated with the signal control board, wherein the test signals comprise on-off test signals and performance test signals;
and when the configuration of the test signal in the data channel is finished, adding a preset voltage to an operational amplifier in communication connection with the test board so as to test the ASIC chip wafer.
In an embodiment, the step of sending an on-off test signal to the ASIC chip through the initialized test board to obtain on-off test data between the ASIC chip and the test board includes any one or more of:
electrifying the ASIC chip through an initialized working voltage interface VDD in the test board, driving an output interface OUT and the working voltage interface VDD in the test board to 0V, and closing an external voltage interface VMIC in the test board to obtain first on-off test data; and/or the presence of a gas in the gas,
and electrifying the ASIC chip through the initialized output interface OUT in the test board, turning the output interface OUT and the working voltage interface VDD in the test board to 0V, and closing an external voltage interface VMIC in the test board to obtain second on-off test data.
In an embodiment, after the step of sending an on-off test signal to the ASIC chip through the initialized test board to obtain on-off test data between the ASIC chip and the test board, the method includes:
judging whether the on-off test data is in a preset interval or not;
if the on-off test data is not in the preset interval, judging that the on-off test data is abnormal, adjusting the position of the ASIC chip, and reconnecting the adjusted ASIC chip to the test board to perform secondary on-off test;
and if the on-off data is in the preset interval, judging that the on-off test data is normal.
In an embodiment, the step of sending a performance test signal to the ASIC chip through the test board to obtain the performance test data of the ASIC chip if the on-off test data is normal includes:
if the on-off test data is normal, sending a first performance test signal to the ASIC chip through the test board to obtain basic performance test data of the ASIC chip;
when the basic performance test is completed, sending a second performance test signal to the ASIC chip through the test board, and obtaining working performance test data of the ASIC chip, wherein the working performance test data comprises: gain data and/or distortion data;
and when the working performance test is finished, sending a third performance test signal to the ASIC chip through the test board to obtain anti-interference performance test data of the ASIC chip.
In an embodiment, the step of analyzing the performance test data to obtain the test result of the ASIC chip includes:
judging whether basic performance test data in the performance test data is in a preset first data interval or not;
if the basic performance test data is in the preset first data interval, judging whether the working performance test data in the performance test data is in a preset second data interval;
if the working performance test data is in the preset second data interval, judging whether anti-interference performance test data in the performance test data is in a preset third data interval or not;
and if the anti-interference performance test data is in the preset third data interval, outputting a test result that the ASIC chip passes the test.
In an embodiment, after the step of determining whether the anti-interference performance test data in the performance test data is within a preset third data interval if the working performance test data is within the preset first data interval, the method includes:
if the working performance test data is not in the preset second data interval, adjusting the second performance test signal;
and sending the adjusted second performance test signal to the ASIC chip through the test board, obtaining new working performance test data of the ASIC chip, and judging whether the new working performance test data is in a preset second data interval or not until the new working performance test data is in the preset second data interval or the test frequency exceeds the preset frequency, and outputting prompt information that the test does not pass.
In an embodiment, after the step of analyzing the performance test data to obtain the test result of the ASIC chip, the method includes:
and if the test result is that the test is not passed, calling a preset marking device, and marking the abnormal ASIC chip by the preset marking device.
In addition, in order to achieve the purpose, the invention also provides a test device of the ASIC chip wafer;
the test equipment of the ASIC chip wafer comprises: a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein:
the computer program, when executed by the processor, implements the steps of the method for testing an ASIC chip wafer as described above.
In addition, to achieve the above object, the present invention also provides a computer storage medium;
the computer storage medium stores thereon a computer program which, when executed by a processor, implements the steps of the method for testing an ASIC chip wafer as described above.
According to the embodiment of the invention, the test board is improved to be connected with a plurality of ASIC chips, the test equipment sends the test signals to the test board, and the test signals are sent to the ASIC chips through the test board to simultaneously test the ASIC chips.
Drawings
FIG. 1 is a schematic diagram of an apparatus in a hardware operating environment according to an embodiment of the present invention;
FIG. 2 is a schematic flow chart illustrating a first embodiment of a method for testing an ASIC chip wafer according to the present invention;
FIG. 3 is a schematic diagram of a test template in a first embodiment of the method for testing the ASIC chip wafer of FIG. 2;
FIG. 4 is a flowchart illustrating a second embodiment of a method for testing an ASIC chip wafer according to the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a testing apparatus (also called a terminal) of an ASIC chip wafer in a hardware operating environment according to an embodiment of the present invention, where the testing apparatus of the ASIC chip wafer may be formed by a testing device of an ASIC chip wafer alone, or may be formed by combining other devices with the testing device of the ASIC chip wafer.
The terminal of the embodiment of the invention can be a fixed terminal or a mobile terminal, such as an intelligent air conditioner with a networking function, an intelligent electric lamp, an intelligent power supply, an intelligent sound box, an automatic driving automobile, a Personal Computer (PC), a smart phone, a tablet computer, an electronic book reader, a portable computer and the like.
As shown in fig. 1, the terminal may include: a processor 1001, such as a Central Processing Unit (CPU), a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. Wherein a communication bus 1002 is used to enable connective communication between these components. The user interface 1003 may include a Display screen (Display), an input unit such as a Keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface, a wireless interface. The network interface 1004 may optionally include a standard wired interface, a WIreless interface (e.g., WIFI interface, WIreless FIdelity, WIFI interface). The memory 1005 may be a high-speed RAM memory or a non-volatile memory (e.g., a magnetic disk memory). The memory 1005 may alternatively be a storage device separate from the processor 1001.
Those skilled in the art will appreciate that the terminal structure shown in fig. 1 is not intended to be limiting and may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
As shown in fig. 1, the computer software product is stored in a storage medium (storage medium: also called computer storage medium, computer medium, readable storage medium, computer readable storage medium, or direct storage medium, etc., and the storage medium may be a non-volatile readable storage medium, such as RAM, magnetic disk, optical disk), and includes several instructions for enabling a terminal device (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the method according to the embodiments of the present invention, and a memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module, and a computer program.
In the terminal shown in fig. 1, the network interface 1004 is mainly used for connecting to a backend server and performing data communication with the backend server; the user interface 1003 is mainly used for connecting a client (user side) and performing data communication with the client; the processor 1001 may be configured to call the computer program stored in the memory 1005 and execute the steps of the method for testing the ASIC chip wafer according to the following embodiment of the present invention.
Based on the hardware structure, the embodiment of the test method of the ASIC chip wafer is provided.
Referring to fig. 2, in a first embodiment of the testing method of the ASIC chip wafer according to the present invention, the testing method of the ASIC chip wafer includes:
step S10, when a chip test request is received, obtaining the test quantity corresponding to the chip test request, and connecting the ASIC chips of the test quantity to the test board.
The test method of the ASIC chip wafer in this embodiment is applied to a test device, the test device receives a chip test request, and a trigger mode of the chip test request is not specifically limited, that is, the chip test request may be actively triggered by a user, for example, a virtual test key is set on a display screen of the test device, and the user clicks the virtual test key to actively trigger the chip test request; in addition, the chip test request may also be automatically triggered by the test equipment, for example, the trigger condition of the chip test request preset in the test equipment is: when the ASIC chip is detected in production, the test equipment automatically triggers a chip test request when the ASIC chip is detected.
When the test equipment receives a chip test request, the test equipment acquires the test quantity corresponding to the chip test request, controls the position of the mobile ASIC chip and connects the ASIC chips with the test quantity to the test board; the testing board in this embodiment is a modified testing board, the testing board includes testing units of a preset number (the preset number refers to a preset maximum testing number for a single time, for example, the preset number is 16), referring to fig. 3, fig. 3 is a structural diagram of the testing unit, the testing unit includes a testing signal input interface INPM, an external voltage interface VMIC, a ground terminal interface VSS, an output interface OUT, and a working voltage interface VDD, and the testing device utilizes the testing board to test an ASIC chip, specifically:
step S20, sending on-off test signals to the ASIC chip through the initialized test board, and obtaining on-off test data between the ASIC chip and the test board.
The test equipment sends an on-off test signal (the on-off test signal refers to a signal for testing the connection state of the ASIC chip and the test board, and the on-off test signal is a signal for powering on the ASIC chip, for example, the on-off test signal is 100uA for powering on the ASIC chip through a working voltage interface VDD in the test board) to the ASIC chip through the test board after initialization, so as to obtain on-off test data between the ASIC chip and the test board, specifically, the method includes:
step a1, electrifying the ASIC chip through the initialized working voltage interface VDD in the test board, turning on an output interface OUT and the working voltage interface VDD in the test board to 0V, and closing an external voltage interface VMIC in the test board to obtain first on-off test data; and/or the presence of a gas in the gas,
step a2, the ASIC chip is powered on through the initialized output interface OUT in the test board, the output interface OUT and the working voltage interface VDD in the test board are turned to 0V, and the external voltage interface VMIC in the test board is closed to obtain second on-off test data.
Namely, the test equipment powers on the ASIC chip through the working voltage interface VDD in the initialized test board, the output interface OUT and the working voltage interface VDD in the test board are turned to 0V by the test equipment, and the external voltage interface VMIC in the test board is closed to obtain first on-off test data; and/or the test equipment powers on the ASIC chip through the output interface OUT in the initialized test board, turns the output interface OUT and the working voltage interface VDD in the test board to 0V, and closes the external voltage interface VMIC in the test board to obtain second on-off test data.
Taking fig. 3 as an example for illustration, in the on-off test, the test equipment first pulls the pin of the output interface OUT in the test board to 0V; secondly, supplying-100 uA current (or 100uA current) to a working voltage interface VDD in the test board, and then measuring an O/S value after 10 ms; then, pulling the pin of the working voltage interface VDD in the test board to 0V, and closing the corresponding data channel of the external voltage interface VMIC; finally, the test equipment closes the data channel corresponding to the OUT pin of the output interface, and the test equipment obtains first on-off test data; and/or, the test equipment firstly pulls the pin of the working voltage interface VDD in the test board to 0V, then provides-100 uA current (or 100uA current) for the output interface OUT in the test board, and measures the OS value after about 10 ms; and the test equipment beats the OUT pin of the output interface in the test board to 0V, closes the data channel corresponding to the OUT pin of the output interface, finally closes the data channel corresponding to the VMIC, and obtains second on-off test data.
In this embodiment, the test equipment transmits the on-off test signal to the test board, and the pin of each interface in the test board is adjusted along with the on-off test signal, so as to obtain on-off test data through testing, and the test equipment determines whether the connection between the test board and the ASIC chip is normal according to the on-off test data, that is, after acquiring the on-off test data between the ASIC chip and the test board, the test equipment determines whether the on-off test data is normal, specifically, the method includes:
step b1, judging whether the on-off test data is in a preset interval;
b2, if the on-off test data is not in the preset interval, judging that the on-off test data is abnormal, adjusting the position of the ASIC chip, and reconnecting the adjusted ASIC chip to the test board to perform secondary on-off test;
and b3, if the on-off data is in the preset interval, judging that the on-off test data is normal.
That is, the test device determines whether the on-off test data is within a preset interval (the preset interval is set according to the on-off test signal); if the on-off test data is not in the preset interval, the test equipment judges that the on-off test data is abnormal, the test equipment adjusts the position of the ASIC chip, and the test equipment reconnects the adjusted ASIC chip to the test board so as to carry out secondary on-off test.
If the on-off data is in the preset interval, the test equipment judges that the on-off test data is normal, and the test equipment further tests the performance of the ASIC chip wafer, specifically:
and step S30, if the on-off test data is normal, sending a performance test signal to the ASIC chip through the test board to obtain the performance test data of the ASIC chip.
If the on-off test data is normal, the test equipment sends a performance test signal (the performance test signal refers to a test signal for testing the performance of the ASIC chip, for example, the performance test signal is a sine wave sent to the ASIC chip through the test board) to the ASIC chip through the test board, so as to obtain the performance test data of the ASIC chip, and specifically, the method includes:
and c1, if the on-off test data is normal, sending a first performance test signal to the ASIC chip through the test board to obtain basic performance test data of the ASIC chip.
Step c2, when the basic performance test is completed, sending a second performance test signal to the ASIC chip through the test board to obtain working performance test data of the ASIC chip, wherein the working performance test data includes: gain data and/or distortion data.
And c3, when the working performance test is finished, sending a third performance test signal to the ASIC chip through the test board to obtain the anti-interference performance test data of the ASIC chip.
That is, if the on-off test data is normal, the test device sends a first performance test signal to the ASIC chip through the test board (the first performance test signal is a signal for testing the basic performance of the chip, for example, a 2V or 3V working voltage is provided to a working voltage interface VDD in the test board), and obtains basic performance test data of the ASIC chip (the basic performance test data includes a working current IDD, a voltage output, and the like of the chip).
When the test equipment completes the basic performance test, the test equipment sends a second performance test signal (the second performance test signal refers to a signal for testing the working performance of the chip, for example, 2V is provided for a working voltage interface VDD in the test board, and a sine wave of 100 khz is output through the test board) to the ASIC chip through the test board, so as to obtain working performance test data of the ASIC chip, where the working performance test data includes: gain data and/or distortion data.
When the test equipment finishes the work performance test, the test equipment sends a third performance test signal (the third performance test signal refers to a signal for testing the anti-interference performance of the chip, for example, 2V is provided for a working voltage interface VDD in the test board, and 100 khz sine waves are output through the test board) to the ASIC chip through the test board, so that anti-interference performance test data of the ASIC chip are obtained.
For example, with reference to fig. 3, the step of performing, by the testing device in this embodiment, a performance test on the chip includes:
1. the basic performance test of the ASIC chip comprises the following steps: the test equipment sends a first performance test signal to the ASIC chip through VDD in the test board, wherein the first performance test signal is electrified 2V; after waiting for 30ms, the test equipment simultaneously measures the output current Idd and the output voltage Vout of the ASIC chip as basic performance test data; or the test equipment sends a first performance test signal to the ASIC chip through VDD in the test board, wherein the first performance test signal is electrified 3V; and after waiting for 30ms, the test equipment simultaneously measures the output current Idd and the output voltage Vout of the ASIC chip as basic performance test data.
2. The ASIC chip working performance test comprises the following steps: the test equipment sends a second performance test signal to the ASIC chip through the test board, wherein the second performance test signal is used for disconnecting the connection between the INPM in the test board and the ground, connecting the OUT to the test pin through the control switch, connecting the INPM to the test pin through the control switch, outputting a 100 kilohertz sine wave to the ASIC chip through the test board, cutting off VDD and reconfiguring the VDD to be 2V, and obtaining gain data and/or distortion data of the ASIC chip as working performance test data.
3. The anti-interference performance test of the ASIC chip comprises the following steps: the test equipment sends a third performance test signal to the ASIC chip through the test board, wherein the third performance test signal is 2V of power-on of the ASIC chip through the test board VDD, and 100 kilohertz sine waves are sent to the ASIC chip, so that anti-interference performance test data are obtained.
And step S40, analyzing the performance test data to obtain the test result of the ASIC chip.
In this embodiment, the test device determines to collect corresponding performance test data according to the output performance test signal, and analyzes the performance test data to obtain a test result of the ASIC chip, and specifically includes:
step d1, judging whether the basic performance test data in the performance test data is in a preset first data interval;
step d2, if the basic performance test data is in the preset first data interval, determining whether the working performance test data in the performance test data is in a preset second data interval;
step d3, if the working performance test data is in the preset second data interval, judging whether the anti-interference performance test data in the performance test data is in a preset third data interval;
and d4, if the anti-interference performance test data is in the preset third data interval, outputting a test result that the ASIC chip passes the test.
That is, the test device determines whether the basic performance test data in the performance test data is within a preset first data interval (the preset first data interval is set according to the first performance test signal); if the basic performance test data is not in a preset first data interval, the ASIC chip is marked to be abnormal, and if the basic performance test data is in the preset first data interval, the working performance test data in the performance test data is judged to be in a preset second data interval (the preset second data interval is set according to a second performance test signal) in the test; if the working performance test data is not in the preset second data interval, the test equipment marks the ASIC chip as abnormal; if the working performance test data is in the preset second data interval, the test equipment judges whether the anti-interference performance test data in the performance test data is in a preset third data interval (the preset third data interval is set according to a third performance test signal); if the anti-interference performance test data is not in the preset third data interval, the test equipment marks the ASIC chip as abnormal; and if the anti-interference performance test data is in the preset third data interval, outputting a test result that the ASIC chip passes the test.
It can be understood that, if the working performance test data is not within the preset second data interval, the test equipment adjusts the second performance test signal; the test equipment sends the adjusted second performance test signal to the ASIC chip through the test board, obtains new working performance test data of the ASIC chip, and judges whether the new working performance test data is in a preset second data interval or not until the new working performance test data is in the preset second data interval or the test frequency exceeds the preset frequency (the preset frequency can be flexibly set according to scenes, for example, 10 times), and then outputs prompt information that the test fails.
In the embodiment, the test board is improved, the test board can be connected with a plurality of ASIC chips, the test equipment sends the test signals to the test board, the test signals are sent to the ASIC chips through the test board, the ASIC chips are simultaneously tested, the simultaneous testing of the ASIC chips is realized in the embodiment, the test time of batch ASIC chips is reduced, the test efficiency of batch ASIC chips is improved, the productivity per unit time of wafer testing of the ASIC chips is improved, meanwhile, the number of the test equipment is reduced due to the fact that the test board tests the ASIC chips, and the test land use and the test labor cost are reduced.
Further, referring to fig. 4, a second embodiment of the testing method of the ASIC chip wafer according to the present invention is provided on the basis of the first embodiment of the present invention.
This embodiment is a step after step S10 in the first embodiment, and is different from the first embodiment of the present invention in that:
step S50, restoring the signal control board and the relay control board in the test board to default values to initialize the test board;
step S60, when the test board is initialized, configuring a test signal for the data channel associated with the signal control board, where the test signal includes an on-off test signal and a performance test signal.
Step S70, when the test signal configuration in the data channel is completed, adding a preset voltage to the operational amplifier communicatively connected to the test board to perform the ASIC chip wafer test.
The testing equipment restores a signal control board and a relay control board in a testing board to default values to initialize the signal control board and the relay control board in the testing board, and when the initialization of the testing board is completed, the testing equipment configures testing data for a data channel associated with the signal control board, wherein the testing data comprises on-off testing data and performance testing data, and when the configuration of the testing signal in the data channel is completed, the testing equipment adds preset voltage (the preset voltage can be set according to the number of testing units in the testing board, for example, the preset voltage is 15v) to an operational amplifier (refer to fig. 3, and the operational amplifier can also be identified by OPA) in communication connection with the testing board so as to test an ASIC chip wafer. In this embodiment, before the test device sends the test signal to the ASIC chip, the test board is initialized, so that the test result of the ASIC chip is more accurate.
Further, a third embodiment of the testing method of the ASIC chip wafer according to the present invention is provided on the basis of the above embodiments.
This embodiment is a step after step S40 in the first embodiment, and is different from the above-described embodiments in that:
and if the test result is that the test is not passed, calling a preset marking device, and marking the abnormal ASIC chip by the preset marking device.
If the test result is that the test fails, the test equipment calls a preset marking device (the preset marking device is a device for adding colors), and the test equipment marks the abnormal ASIC chip through the preset marking device. That is, in the prior art, when the ASIC chip wafer is tested, the test data is displayed on the test equipment, so that a user is required to determine abnormal equipment according to the test data.
In addition, the embodiment of the invention also provides a computer storage medium.
The computer storage medium having stored thereon a computer program that, when executed by a processor, performs the steps of:
when a chip test request is received, obtaining the test quantity corresponding to the chip test request, and connecting the ASIC chips of the test quantity to the test board;
sending an on-off test signal to the ASIC chip through the initialized test board to obtain on-off test data between the ASIC chip and the test board;
if the on-off test data is normal, sending a performance test signal to the ASIC chip through the test board to obtain performance test data of the ASIC chip;
and analyzing the performance test data to obtain a test result of the ASIC chip.
In an embodiment, the step of obtaining, by the processor, a test quantity corresponding to the chip test request when the chip test request is received, and connecting the ASIC chips of the test quantity to the test board includes:
restoring a signal control board and a relay control board in the test board to default values so as to initialize the test board;
when the initialization of the test board is completed, configuring test signals for data channels associated with the signal control board, wherein the test signals comprise on-off test signals and performance test signals;
and when the configuration of the test signal in the data channel is finished, adding a preset voltage to an operational amplifier in communication connection with the test board so as to test the ASIC chip wafer.
In an embodiment, the step of sending, by the processor, an on-off test signal to the ASIC chip through the initialized test board to obtain on-off test data between the ASIC chip and the test board includes any one or more of:
electrifying the ASIC chip through an initialized working voltage interface VDD in the test board, driving an output interface OUT and the working voltage interface VDD in the test board to 0V, and closing an external voltage interface VMIC in the test board to obtain first on-off test data; and/or the presence of a gas in the gas,
and electrifying the ASIC chip through the initialized output interface OUT in the test board, turning the output interface OUT and the working voltage interface VDD in the test board to 0V, and closing an external voltage interface VMIC in the test board to obtain second on-off test data.
In an embodiment, after the step of sending an on-off test signal to the ASIC chip through the initialized test board and obtaining on-off test data between the ASIC chip and the test board is executed by the processor, the method includes:
judging whether the on-off test data is in a preset interval or not;
if the on-off test data is not in the preset interval, judging that the on-off test data is abnormal, adjusting the position of the ASIC chip, and reconnecting the adjusted ASIC chip to the test board to perform secondary on-off test;
and if the on-off data is in the preset interval, judging that the on-off test data is normal.
In an embodiment, the step of the computer program executed by the processor, if the on-off test data is normal, sending a performance test signal to the ASIC chip through the test board to obtain the performance test data of the ASIC chip, includes:
if the on-off test data is normal, sending a first performance test signal to the ASIC chip through the test board to obtain basic performance test data of the ASIC chip;
when the basic performance test is completed, sending a second performance test signal to the ASIC chip through the test board, and obtaining working performance test data of the ASIC chip, wherein the working performance test data comprises: gain data and/or distortion data;
and when the working performance test is finished, sending a third performance test signal to the ASIC chip through the test board to obtain anti-interference performance test data of the ASIC chip.
In one embodiment, the step of analyzing the performance test data to obtain the test result of the ASIC chip is executed by a processor, and includes:
judging whether basic performance test data in the performance test data is in a preset first data interval or not;
if the basic performance test data is in the preset first data interval, judging whether the working performance test data in the performance test data is in a preset second data interval;
if the working performance test data is in the preset second data interval, judging whether anti-interference performance test data in the performance test data is in a preset third data interval or not;
and if the anti-interference performance test data is in the preset third data interval, outputting a test result that the ASIC chip passes the test.
In an embodiment, after the step of determining whether the anti-interference performance test data in the performance test data is within a preset third data interval if the working performance test data is within the preset first data interval, the step of executing by the processor the computer program includes:
if the working performance test data is not in the preset second data interval, adjusting the second performance test signal;
and sending the adjusted second performance test signal to the ASIC chip through the test board, obtaining new working performance test data of the ASIC chip, and judging whether the new working performance test data is in a preset second data interval or not until the new working performance test data is in the preset second data interval or the test frequency exceeds the preset frequency, and outputting prompt information that the test does not pass.
In one embodiment, the computer program, after being executed by the processor to analyze the performance test data to obtain the test result of the ASIC chip, comprises:
and if the test result is that the test is not passed, calling a preset marking device, and marking the abnormal ASIC chip by the preset marking device.
The steps implemented by the computer storage medium for installing the test program may refer to various embodiments of the method for testing the ASIC chip wafer of the present invention, and are not described herein again.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity/action/object from another entity/action/object without necessarily requiring or implying any actual such relationship or order between such entities/actions/objects; the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
For the apparatus embodiment, since it is substantially similar to the method embodiment, it is described relatively simply, and reference may be made to some descriptions of the method embodiment for relevant points. The above-described apparatus embodiments are merely illustrative, in that elements described as separate components may or may not be physically separate. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of the invention. One of ordinary skill in the art can understand and implement it without inventive effort.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) as described above and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (6)
1. The method for testing the ASIC chip wafer is characterized in that the method for testing the ASIC chip wafer is applied to test equipment, and the test equipment is in communication connection with a test board;
the test method of the ASIC chip wafer comprises the following steps:
when a chip test request is received, obtaining the test quantity corresponding to the chip test request, and connecting the ASIC chips of the test quantity to the test board;
sending an on-off test signal to the ASIC chip through the initialized test board to obtain on-off test data between the ASIC chip and the test board;
if the on-off test data is normal, sending a performance test signal to the ASIC chip through the test board to obtain performance test data of the ASIC chip;
if the on-off test data is normal, sending a performance test signal to the ASIC chip through the test board, and obtaining the performance test data of the ASIC chip comprises the following steps:
if the on-off test data is normal, sending a first performance test signal to the ASIC chip through the test board to obtain basic performance test data of the ASIC chip;
when the basic performance test is completed, sending a second performance test signal to the ASIC chip through the test board, and obtaining working performance test data of the ASIC chip, wherein the working performance test data comprises: gain data and/or distortion data;
when the working performance test is finished, sending a third performance test signal to the ASIC chip through the test board to obtain anti-interference performance test data of the ASIC chip;
analyzing the performance test data to obtain a test result of the ASIC chip;
the step of sending an on-off test signal to the ASIC chip through the initialized test board to obtain on-off test data between the ASIC chip and the test board includes any one or more of the following steps:
electrifying the ASIC chip through an initialized working voltage interface VDD in the test board, driving an output interface OUT and the working voltage interface VDD in the test board to 0V, and closing an external voltage interface VMIC in the test board to obtain first on-off test data; and/or the presence of a gas in the gas,
and electrifying the ASIC chip through the initialized output interface OUT in the test board, turning the output interface OUT and the working voltage interface VDD in the test board to 0V, and closing an external voltage interface VMIC in the test board to obtain second on-off test data.
2. The method for testing the ASIC chip wafer of claim 1, wherein the step of obtaining the test quantity corresponding to the chip test request when the chip test request is received, and connecting the ASIC chips of the test quantity to the test board includes:
restoring a signal control board and a relay control board in the test board to default values so as to initialize the test board;
when the initialization of the test board is completed, configuring test signals for data channels associated with the signal control board, wherein the test signals comprise on-off test signals and performance test signals;
and when the configuration of the test signal in the data channel is finished, adding a preset voltage to an operational amplifier in communication connection with the test board so as to test the ASIC chip wafer.
3. The method for testing the ASIC chip wafer according to claim 1, wherein the step of sending an on-off test signal to the ASIC chip through the initialized test board to obtain the on-off test data between the ASIC chip and the test board comprises:
judging whether the on-off test data is in a preset interval or not;
if the on-off test data is not in the preset interval, judging that the on-off test data is abnormal, adjusting the position of the ASIC chip, and reconnecting the adjusted ASIC chip to the test board to perform secondary on-off test;
and if the on-off test data is in the preset interval, judging that the on-off test data is normal.
4. The method of claim 1, wherein the step of analyzing the performance test data to obtain the test results of the ASIC chips comprises:
judging whether basic performance test data in the performance test data is in a preset first data interval or not;
if the basic performance test data is in the preset first data interval, judging whether the working performance test data in the performance test data is in a preset second data interval;
if the working performance test data is in the preset second data interval, judging whether anti-interference performance test data in the performance test data is in a preset third data interval or not;
and if the anti-interference performance test data is in the preset third data interval, outputting a test result that the ASIC chip passes the test.
5. The method according to claim 4, wherein the step of determining whether the anti-interference performance test data in the performance test data is within a preset third data interval if the working performance test data is within the preset first data interval comprises:
if the working performance test data is not in the preset second data interval, adjusting the second performance test signal;
and sending the adjusted second performance test signal to the ASIC chip through the test board, obtaining new working performance test data of the ASIC chip, and judging whether the new working performance test data is in a preset second data interval or not until the new working performance test data is in the preset second data interval or the test frequency exceeds the preset frequency, and outputting prompt information that the test fails.
6. The method of claim 1, wherein the step of analyzing the performance test data to obtain the test results of the ASIC chips is followed by the step of:
and if the test result is that the test is not passed, calling a preset marking device, and marking the abnormal ASIC chip by the preset marking device.
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| CN201911255409.7A CN110888042B (en) | 2019-12-09 | 2019-12-09 | Method and equipment for testing ASIC chip wafer and computer storage medium |
| PCT/CN2020/134664 WO2021115288A1 (en) | 2019-12-09 | 2020-12-08 | Asic chip wafer testing method and device, and computer storage medium |
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| CN110888042B (en) * | 2019-12-09 | 2022-02-25 | 青岛歌尔微电子研究院有限公司 | Method and equipment for testing ASIC chip wafer and computer storage medium |
| CN113740703B (en) * | 2021-07-28 | 2023-11-10 | 苏州浪潮智能科技有限公司 | Test board and test system of Retimer chip |
| CN115629300B (en) * | 2022-12-22 | 2023-03-17 | 北京怀美科技有限公司 | Chip detection method and chip detection system |
| CN117012258B (en) * | 2023-09-26 | 2024-01-02 | 合肥康芯威存储技术有限公司 | Analysis device, method and medium for storing chip state data |
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| WO2021115288A1 (en) | 2021-06-17 |
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