本发明的实施方式Embodiments of the present invention
应当理解,此处所描述的具体实施例仅仅用以解释本申请,并不用于限定本申请。It should be understood that the specific embodiments described here are only used to explain the present application, and are not used to limit the present application.
如图1所示,图1是本申请实施例方案涉及的硬件运行环境的ASIC芯片晶圆的测试设备(又叫终端,其中,ASIC芯片晶圆的测试设备可以是由单独的ASIC芯片晶圆的测试装置构成,也可以是由其他装置与ASIC芯片晶圆的测试装置组合形成)结构示意图。As shown in FIG. 1, FIG. 1 is a test equipment (also called a terminal) of an ASIC chip wafer in the hardware operating environment involved in the embodiment of the application. The test equipment of the ASIC chip wafer can be a separate ASIC chip wafer. The structure of the test device can also be formed by combining other devices and the test device of the ASIC chip wafer).
本申请实施例终端可以固定终端,也可以是移动终端,如,带联网功能的智能空调、智能电灯、智能电源、智能音箱、自动驾驶汽车、PC (personal computer)个人计算机、智能手机、平板电脑、电子书阅读器、便携计算机等。The terminal in the embodiments of this application can be a fixed terminal or a mobile terminal, such as smart air conditioners with networking functions, smart lights, smart power supplies, smart speakers, autonomous vehicles, PC (personal computer) personal computers, smart phones, and tablet computers , E-book readers, portable computers, etc.
如图1所示,该终端可以包括:处理器1001,例如,中央处理器Central Processing Unit,CPU),网络接口1004,用户接口1003,存储器1005,通信总线1002。其中,通信总线1002用于实现这些组件之间的连接通信。用户接口1003可以包括显示屏(Display)、输入单元比如键盘(Keyboard),可选用户接口1003还可以包括标准的有线接口、无线接口。网络接口1004可选的可以包括标准的有线接口、无线接口(如无线保真WIreless-FIdelity,WIFI接口)。存储器1005可以是高速RAM存储器,也可以是稳定的存储器(non-volatile
memory),例如,磁盘存储器。存储器1005可选的还可以是独立于前述处理器1001的存储装置。As shown in FIG. 1, the terminal may include: a processor 1001, for example, a central processing unit (CPU), a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002. Among them, the communication bus 1002 is used to implement connection and communication between these components. The user interface 1003 may include a display screen (Display) and an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as WIreless-FIdelity, WIFI interface). The memory 1005 can be a high-speed RAM memory or a stable memory (non-volatile
memory), for example, disk storage. Optionally, the memory 1005 may also be a storage device independent of the aforementioned processor 1001.
本领域技术人员可以理解,图1中示出的终端结构并不构成对终端的限定,可以包括比图示更多或更少的部件,或者组合某些部件,或者不同的部件布置。Those skilled in the art can understand that the terminal structure shown in FIG. 1 does not constitute a limitation on the terminal, and may include more or less components than shown in the figure, or combine some components, or arrange different components.
如图1所示,该计算机软件产品存储在一个存储介质(存储介质:又叫计算机存储介质、计算机介质、可读介质、可读存储介质、计算机可读存储介质或者直接叫介质等,存储介质可以是非易失性可读存储介质,如RAM、磁碟、光盘)中,包括若干指令用以使得一台终端设备(可以是手机,计算机,服务器,空调器,或者网络设备等)执行本申请各个实施例所述的方法,作为一种计算机存储介质的存储器1005中可以包括操作系统、网络通信模块、用户接口模块以及计算机程序。As shown in Figure 1, the computer software product is stored in a storage medium (storage medium: also called computer storage medium, computer medium, readable medium, readable storage medium, computer readable storage medium, or directly called medium, etc., storage medium It can be a non-volatile readable storage medium, such as RAM, magnetic disk, optical disk, and includes several instructions to make a terminal device (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute this application In the method described in each embodiment, the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module, and a computer program.
在图1所示的终端中,网络接口1004主要用于连接后台服务器,与后台服务器进行数据通信;用户接口1003主要用于连接客户端(用户端),与客户端进行数据通信;而处理器1001可以用于调用存储器1005中存储的计算机程序,并执行本申请以下实施例提供的ASIC芯片晶圆的测试方法中的步骤。In the terminal shown in FIG. 1, the network interface 1004 is mainly used to connect to the back-end server and communicate with the back-end server; the user interface 1003 is mainly used to connect to the client (user side) and communicate with the client; and the processor 1001 can be used to call a computer program stored in the memory 1005 and execute the steps in the ASIC chip wafer testing method provided in the following embodiments of the present application.
基于上述硬件结构,提出了本申请ASIC芯片晶圆的测试方法的实施例。Based on the above hardware structure, an embodiment of the test method of the ASIC chip wafer of the present application is proposed.
参照图2,在本申请一种ASIC芯片晶圆的测试方法的第一实施例中,所述ASIC芯片晶圆的测试方法包括:2, in the first embodiment of the test method of an ASIC chip wafer of the present application, the test method of the ASIC chip wafer includes:
步骤S10,在接收到芯片测试请求时,获取所述芯片测试请求对应的测试数量,将所述测试数量的ASIC芯片连接到所述测试板上。In step S10, when a chip test request is received, the test quantity corresponding to the chip test request is obtained, and the ASIC chip of the test quantity is connected to the test board.
本实施例中ASIC芯片晶圆的测试方法应用于测试设备,测试设备接收芯片测试请求,芯片测试请求的触发方式不做具体限定,即,芯片测试请求可以是用户主动触发的,例如,测试设备的显示屏上设置虚拟测试按键,用户点击虚拟测试按键,主动触发芯片测试请求;此外,芯片测试请求还可以是测试设备自动触发的,例如,测试设备中预设芯片测试请求的触发条件为:生产检测到ASIC芯片时,则测试设备在检测到ASIC芯片时,自动触发芯片测试请求。The test method of the ASIC chip wafer in this embodiment is applied to the test equipment. The test equipment receives the chip test request. The triggering method of the chip test request is not specifically limited, that is, the chip test request can be triggered by the user, for example, the test device A virtual test button is set on the display screen of the, and the user clicks the virtual test button to actively trigger the chip test request; in addition, the chip test request can also be automatically triggered by the test device. For example, the trigger condition of the preset chip test request in the test device is: When the ASIC chip is detected in the production, the test equipment automatically triggers the chip test request when the ASIC chip is detected.
测试设备在接收到芯片测试请求时,测试设备获取芯片测试请求对应的测试数量,测试设备控制移动ASIC芯片的位置,并将测试数量的ASIC芯片连接到测试板上;本实施例中的测试板为改装过的测试板,测试板包括预设数量(预设数量是指预先设置的单次最大测试数量,例如,预设数量为16)的测试单元,参照图3,图3为一个测试单元的结构图,测试单元包括测试信号输入接口INPM、外接电压接口VMIC、接地端接口VSS、输出接口OUT和工作电压接口VDD,测试设备利用测试板对ASIC芯片进行测试,具体地:When the test device receives the chip test request, the test device obtains the test quantity corresponding to the chip test request, the test device controls the position of the mobile ASIC chip, and connects the tested number of ASIC chips to the test board; the test board in this embodiment For the modified test board, the test board includes a preset number of test units (the preset number refers to the maximum number of single tests set in advance, for example, the preset number is 16). Refer to Figure 3, which is a test unit. The test unit includes the test signal input interface INPM, the external voltage interface VMIC, the ground terminal interface VSS, the output interface OUT and the working voltage interface VDD. The test equipment uses the test board to test the ASIC chip, specifically:
步骤S20,通过初始化后的所述测试板将通断测试信号发送至所述ASIC芯片,获得所述ASIC芯片与所述测试板之间的通断测试数据。In step S20, the continuity test signal is sent to the ASIC chip through the initialized test board, and the continuity test data between the ASIC chip and the test board is obtained.
测试设备通过初始化后的测试板将通断测试信号(通断测试信号是指用于测试ASIC芯片与测试板连接状态的信号,通断测试信号是给ASIC芯片上电的信号,例如,通断测试信号为通过测试板中的工作电压接口VDD给ASIC芯片上电100uA)发送至ASIC芯片,获得ASIC芯片与测试板之间的通断测试数据,具体地,包括:The test equipment passes the initialized test board and will turn on and off the test signal (the on-off test signal refers to the signal used to test the connection state of the ASIC chip and the test board, and the on-off test signal is the signal to power on the ASIC chip, for example, on-off The test signal is sent to the ASIC chip through the working voltage interface VDD in the test board to power up the ASIC chip (100uA) to obtain the continuity test data between the ASIC chip and the test board. Specifically, it includes:
步骤a1,通过初始化后的所述测试板中的工作电压接口VDD给所述ASIC芯片上电,将所述测试板中的输出接口OUT和工作电压接口VDD打到0V,并将所述测试板中的外接电压接口VMIC关闭,获得第一通断测试数据;和/或,Step a1, power on the ASIC chip through the working voltage interface VDD in the test board after initialization, set the output interface OUT and working voltage interface VDD in the test board to 0V, and set the test board The external voltage interface VMIC in the device is closed, and the first on-off test data is obtained; and/or,
步骤a2,通过初始化后的所述测试板中的输出接口OUT给所述ASIC芯片上电,将所述测试板中的输出接口OUT和工作电压接口VDD打到0V,并将所述测试板中的外接电压接口VMIC关闭,获得第二通断测试数据。Step a2, the ASIC chip is powered on through the output interface OUT in the test board after initialization, the output interface OUT and the working voltage interface VDD in the test board are set to 0V, and the test board is The external voltage interface VMIC is closed, and the second on-off test data is obtained.
即,测试设备通过初始化后的测试板中的工作电压接口VDD给ASIC芯片上电测试设备将测试板中的输出接口OUT和工作电压接口VDD打到0V,并将测试板中的外接电压接口VMIC关闭,获得第一通断测试数据;和/或,测试设备通过初始化后的测试板中的输出接口OUT给ASIC芯片上电,测试设备将测试板中的输出接口OUT和工作电压接口VDD打到0V,并将测试板中的外接电压接口VMIC关闭,获得第二通断测试数据。That is, the test device powers on the ASIC chip through the working voltage interface VDD in the initialized test board. The test device turns the output interface OUT and the working voltage interface VDD in the test board to 0V, and connects the external voltage interface VMIC in the test board. Close to obtain the first continuity test data; and/or, the test device powers on the ASIC chip through the output interface OUT in the initialized test board, and the test device turns the output interface OUT and the working voltage interface VDD in the test board to 0V, and turn off the external voltage interface VMIC in the test board to obtain the second on-off test data.
以图3为例说明,通断测试时测试设备首先将测试板中输出接口OUT的引脚拉到0V;其次给测试板中工作电压接口VDD提供-100uA电流(或者100uA电流),然后在10ms后测量O/S值;再将测试板中工作电压接口VDD的引脚拉到0V,并关闭外接电压接口VMIC对应数据通道;最后,测试设备关闭输出接口 OUT引脚对应数据通道,测试设备获得第一通断测试数据;和/或,测试设备首先将测试板中工作电压接口VDD的引脚拉到0V,再给测试板中输出接口OUT提供-100uA电流(或者100uA电流),约10ms后测量OS值;测试设备将测试板中输出接口 OUT引脚打到0V,并关闭输出接口 OUT引脚对应数据通道,最后测试设备关闭外接电压接口VMIC对应数据通道,测试设备获得第二通断测试数据。Take Figure 3 as an example. During the continuity test, the test equipment first pulls the pin of the output interface OUT in the test board to 0V; secondly, it provides the working voltage interface VDD in the test board with a current of -100uA (or 100uA), and then in 10ms Then measure the O/S value; then pull the VDD pin of the working voltage interface in the test board to 0V, and close the data channel corresponding to the external voltage interface VMIC; finally, the test equipment closes the data channel corresponding to the OUT pin of the output interface, and the test equipment obtains The first continuity test data; and/or, the test equipment first pulls the pin of the working voltage interface VDD in the test board to 0V, and then provides the output interface OUT in the test board with -100uA current (or 100uA current), about 10ms later Measure the OS value; the test equipment turns the OUT pin of the output interface on the test board to 0V, and closes the data channel corresponding to the OUT pin of the output interface. Finally, the test equipment closes the data channel corresponding to the external voltage interface VMIC, and the test equipment obtains the second continuity test data.
本实施例中测试设备对测试板中传输通断测试信号,测试板中各个接口的引脚随着通断测试信号进行调整,可以测试得到通断测试数据,测试设备根据通断测试数据确定测试板与ASIC芯片之间的连接是否正常,即,在获取到ASIC芯片与测试板之间的通断测试数据之后,测试设备判断通断测试数据是否正常,具体地,包括:In this embodiment, the test equipment transmits the continuity test signal to the test board, and the pins of each interface in the test board are adjusted with the continuity test signal to obtain the continuity test data. The test equipment determines the test according to the continuity test data. Whether the connection between the board and the ASIC chip is normal, that is, after obtaining the continuity test data between the ASIC chip and the test board, the test equipment determines whether the continuity test data is normal, specifically, including:
步骤b1,判断所述通断测试数据是否在预设区间内;Step b1, judging whether the continuity test data is within a preset interval;
步骤b2,若所述通断测试数据不在所述预设区间内,则判定所述通断测试数据异常,并调整所述ASIC芯片的位置将调整后的所述ASIC芯片重新连接到所述测试板,以进行二次通断测试;Step b2, if the continuity test data is not within the preset interval, determine that the continuity test data is abnormal, and adjust the position of the ASIC chip to reconnect the adjusted ASIC chip to the test Board for the second continuity test;
步骤b3,若所述通断数据在所述预设区间内,则判定所述通断测试数据正常。In step b3, if the on-off data is within the preset interval, it is determined that the on-off test data is normal.
即,测试设备判断通断测试数据是否在预设区间(预设区间是根据通断测试信号设置的)内;若通断测试数据不在预设区间内,则测试设备判定通断测试数据异常,测试设备调整ASIC芯片的位置,测试设备将调整后的ASIC芯片重新连接到测试板,以进行二次通断测试。That is, the test equipment determines whether the continuity test data is within a preset interval (the preset interval is set according to the continuity test signal); if the continuity test data is not within the preset interval, the test equipment determines that the continuity test data is abnormal, The test equipment adjusts the position of the ASIC chip, and the test equipment reconnects the adjusted ASIC chip to the test board to perform a secondary on-off test.
若通断数据在预设区间内,测试设备判定通断测试数据正常,测试设备进一步地对ASIC芯片晶圆的性能进行测试,具体地:If the continuity data is within the preset interval, the test equipment determines that the continuity test data is normal, and the test equipment further tests the performance of the ASIC chip wafer, specifically:
步骤S30,若所述通断测试数据正常,则通过所述测试板将性能测试信号发送至所述ASIC芯片,获得所述ASIC芯片的性能测试数据。Step S30: If the continuity test data is normal, the performance test signal is sent to the ASIC chip through the test board to obtain the performance test data of the ASIC chip.
若通断测试数据正常,测试设备通过测试板将性能测试信号(性能测试信号是指用于测试ASIC芯片性能的测试信号,例如,性能测试信号为通过测试板给ASIC芯片发送正弦波)发送至ASIC芯片,获得ASIC芯片的性能测试数据,具体地,包括:If the continuity test data is normal, the test equipment sends the performance test signal (the performance test signal refers to the test signal used to test the performance of the ASIC chip, for example, the performance test signal sends a sine wave to the ASIC chip through the test board) through the test board ASIC chip, to obtain the performance test data of the ASIC chip, specifically, including:
步骤c1,若所述通断测试数据正常,则通过所述测试板将第一性能测试信号发送至所述ASIC芯片,获得所述ASIC芯片的基础性能测试数据。Step c1: If the continuity test data is normal, the first performance test signal is sent to the ASIC chip through the test board to obtain the basic performance test data of the ASIC chip.
步骤c2,在所述基础性能测试完成时,通过所述测试板将第二性能测试信号发送至所述ASIC芯片,获得所述ASIC芯片的工作性能测试数据,其中,所述工作性能测试数据包括:增益数据和/或失真数据。Step c2: When the basic performance test is completed, a second performance test signal is sent to the ASIC chip through the test board to obtain work performance test data of the ASIC chip, where the work performance test data includes : Gain data and/or distortion data.
步骤c3,在所述工作性能测试完成时,通过所述测试板将第三性能测试信号发送至所述ASIC芯片,获得所述ASIC芯片的抗干扰性能测试数据。Step c3: When the work performance test is completed, a third performance test signal is sent to the ASIC chip through the test board to obtain the anti-interference performance test data of the ASIC chip.
即,若通断测试数据正常,测试设备通过所述测试板将第一性能测试信号发送至ASIC芯片(第一性能测试信号是指对芯片基础性能测试的信号,例如给测试板中工作电压接口VDD提供2V或者3V的工作电压),获得ASIC芯片的基础性能测试数据(基础性能测试数据包括芯片的工作电流IDD、电压输出等)。That is, if the continuity test data is normal, the test device sends the first performance test signal to the ASIC chip through the test board (the first performance test signal refers to the signal for the basic performance test of the chip, for example, to the working voltage interface in the test board VDD provides 2V or 3V working voltage) to obtain basic performance test data of ASIC chip (basic performance test data includes chip working current IDD, voltage output, etc.).
测试设备在基础性能测试完成时,测试设备通过测试板将第二性能测试信号(第二性能测试信号是指对芯片工作性能测试的信号,例如给测试板中工作电压接口VDD提供2V,并通过测试板输出100千赫兹的正弦波)发送至ASIC芯片,获得ASIC芯片的工作性能测试数据,其中,工作性能测试数据包括:增益数据和/或失真数据。When the basic performance test of the test equipment is completed, the test equipment sends the second performance test signal through the test board (the second performance test signal refers to the signal for testing the performance of the chip, for example, provides 2V to the working voltage interface VDD in the test board, and passes The test board outputs a 100 kHz sine wave) and sends it to the ASIC chip to obtain work performance test data of the ASIC chip. The work performance test data includes gain data and/or distortion data.
测试设备在工作性能测试完成时,测试设备通过测试板将第三性能测试信号(第三性能测试信号是指对芯片抗干扰性能测试的信号,例如给测试板中工作电压接口VDD提供2V,并通过测试板输出100千赫兹的正弦波)发送至ASIC芯片,获得ASIC芯片的抗干扰性能测试数据。When the working performance test of the test equipment is completed, the test equipment sends the third performance test signal through the test board (the third performance test signal refers to the signal for the anti-interference performance test of the chip, for example, provides 2V to the working voltage interface VDD in the test board, and Through the test board, output a 100 kHz sine wave) and send it to the ASIC chip to obtain the anti-jamming performance test data of the ASIC chip.
例如,结合图3,本实施例中测试设备对芯片进行性能测试的步骤包括:For example, with reference to Figure 3, the steps of the testing device in this embodiment to perform performance testing on the chip include:
1、ASIC芯片基础性能测试包括:测试设备通过测试板中的VDD给ASIC芯片发送第一性能测试信号,第一性能测试信号为上电2V;测试设备等待30ms后同时测量ASIC芯片输出电流Idd和输出电压 Vout作为基础性能测试数据;或者测试设备通过测试板中的VDD给ASIC芯片第一性能测试信号,第一性能测试信号为上电3V;测试设备等待30ms后同时测量ASIC芯片输出电流Idd和输出电压 Vout作为基础性能测试数据。1. The basic performance test of the ASIC chip includes: the test equipment sends the first performance test signal to the ASIC chip through the VDD in the test board, and the first performance test signal is 2V when the power is on; the test equipment waits for 30ms and measures the output current Idd and the ASIC chip at the same time. The output voltage Vout is used as the basic performance test data; or the test equipment sends the first performance test signal to the ASIC chip through VDD in the test board, and the first performance test signal is power-on 3V; the test equipment waits for 30ms and simultaneously measures the ASIC chip output current Idd and The output voltage Vout is used as the basic performance test data.
2、ASIC芯片工作性能测试包括:测试设备通过测试板给ASIC芯片发送第二性能测试信号,其中第二性能测试信号为断开测试板中INPM到地的连接,并将控制开关使OUT连接到测试引脚,控制开关使INPM连接到测试引脚,测试板给ASIC芯片输出100千赫兹的正弦波,断电VDD并重新配置VDD为2V,获取ASIC芯片增益数据和/或失真数据,作为工作性能测试数据。2. The ASIC chip performance test includes: the test equipment sends a second performance test signal to the ASIC chip through the test board, where the second performance test signal is to disconnect the INPM from the test board to the ground, and connect the control switch to OUT. Test pin, control the switch to connect INPM to the test pin, the test board outputs a 100KHz sine wave to the ASIC chip, power off VDD and reconfigure VDD to 2V, get ASIC chip gain data and/or distortion data, as work Performance test data.
3、ASIC芯片抗干扰性能测试包括:测试设备通过测试板给ASIC芯片发送第三性能测试信号,其中第三性能测试信号为通过测试板VDD给ASIC芯片上电2V,给ASIC芯片发送100千赫兹的正弦波,获取抗干扰性能测试数据。3. ASIC chip anti-jamming performance test includes: the test equipment sends the third performance test signal to the ASIC chip through the test board, where the third performance test signal is to power up the ASIC chip by 2V through the test board VDD and send 100 kHz to the ASIC chip Sine wave to obtain the anti-jamming performance test data.
步骤S40,分析所述性能测试数据,获得所述ASIC芯片的测试结果。Step S40: Analyze the performance test data to obtain the test result of the ASIC chip.
本实施例中测试设备根据输出的性能测试信号,确定采集对应的性能测试数据,并分析性能测试数据,获得ASIC芯片的测试结果,具体地,包括:According to the output performance test signal, the test equipment in this embodiment determines to collect the corresponding performance test data, analyzes the performance test data, and obtains the test result of the ASIC chip, which specifically includes:
步骤d1,判断所述性能测试数据中的基础性能测试数据是否在预设第一数据区间内;Step d1, judging whether the basic performance test data in the performance test data is within a preset first data interval;
步骤d2,若所述基础性能测试数据在所述预设第一数据区间内,则判断所述性能测试数据中的工作性能测试数据是否在预设第二数据区间内;Step d2, if the basic performance test data is within the preset first data interval, determine whether the work performance test data in the performance test data is within the preset second data interval;
步骤d3,若所述工作性能测试数据在所述预设第二数据区间内,则判断所述性能测试数据中的抗干扰性能测试数据是否在预设第三数据区间内;Step d3, if the work performance test data is within the preset second data interval, determine whether the anti-interference performance test data in the performance test data is within the preset third data interval;
步骤d4,若所述抗干扰性能测试数据在所述预设第三数据区间内,则输出ASIC芯片测试通过的测试结果。Step d4: If the anti-interference performance test data is within the preset third data interval, output the test result of the ASIC chip test passing.
即,测试设备判断性能测试数据中的基础性能测试数据是否在预设第一数据区间(预设第一数据区间根据第一性能测试信号设置)内;若基础性能测试数据不在预设第一数据区间,则标记该ASIC芯片异常,若基础性能测试数据在所述预设第一数据区间内,则测试中单判断性能测试数据中的工作性能测试数据是否在预设第二数据区间内(预设第二数据区间根据第二性能测试信号设置);若工作性能测试数据不在预设第二数据区间内,则测试设备标记该ASIC芯片异常;若工作性能测试数据在所述预设第二数据区间内,则测试设备判断性能测试数据中的抗干扰性能测试数据是否在预设第三数据区间(预设第三数据区间根据第三性能测试信号设置)内;若抗干扰性能测试数据不在预设第三数据区间内,则测试设备标记该ASIC芯片异常;若抗干扰性能测试数据在预设第三数据区间内,则输出ASIC芯片测试通过的测试结果。That is, the test equipment determines whether the basic performance test data in the performance test data is within the preset first data interval (the preset first data interval is set according to the first performance test signal); if the basic performance test data is not in the preset first data If the basic performance test data is within the preset first data interval, the test only determines whether the work performance test data in the performance test data is within the preset second data interval (preset Suppose that the second data interval is set according to the second performance test signal); if the work performance test data is not within the preset second data interval, the test equipment marks the ASIC chip as abnormal; if the work performance test data is in the preset second data In the interval, the test equipment judges whether the anti-interference performance test data in the performance test data is within the preset third data interval (the preset third data interval is set according to the third performance test signal); Assuming that it is in the third data interval, the test equipment marks the ASIC chip as abnormal; if the anti-interference performance test data is in the preset third data interval, the test result that the ASIC chip has passed is output.
可以理解的是,若工作性能测试数据不在预设第二数据区间内,测试设备则调整第二性能测试信号;测试设备通过所述测试板将调整后的第二性能测试信号发送至所述ASIC芯片,获得所述ASIC芯片新的工作性能测试数据,并判断新的工作性能测试数据是否在预设第二数据区间内,直至新的工作性能测试数据在预设第二数据区间内,或测试次数超过预设次数(预设次数可以根据场景灵活设置,例如设置为10次)时输出测试不通过的提示信息。It is understandable that if the work performance test data is not within the preset second data interval, the test device adjusts the second performance test signal; the test device sends the adjusted second performance test signal to the ASIC through the test board The chip obtains new work performance test data of the ASIC chip, and determines whether the new work performance test data is within the preset second data interval, until the new work performance test data is within the preset second data interval, or the test When the number of times exceeds the preset number (the preset number can be flexibly set according to the scene, for example, set to 10 times), a prompt message indicating that the test failed is output.
本实施例中对测试板进行改进,使得测试板可以连接多个ASIC芯片,测试设备通过发送测试信号至测试板,通过测试板将测试信号发送至ASIC芯片,以对多个ASIC芯片进行同时测试,本实施例中实现了多个ASIC芯片同时测试,减少了批量ASIC芯片的测试时间,提高了批量ASIC芯片的测试效率,使得ASIC芯片晶圆测试的单位时间产能提升,与此同时,由于一个测试板上对多个ASIC芯片进行测试,减少了测试设备的数量,从而减少了测试用地和测试人力成本。In this embodiment, the test board is improved so that the test board can be connected to multiple ASIC chips. The test equipment sends test signals to the test board and the test board sends the test signals to the ASIC chip to test multiple ASIC chips at the same time. In this embodiment, multiple ASIC chips are tested at the same time, the test time of batch ASIC chips is reduced, the test efficiency of batch ASIC chips is improved, and the unit time productivity of ASIC chip wafer testing is increased. At the same time, due to one Testing multiple ASIC chips on the test board reduces the number of test equipment, thereby reducing test land and test labor costs.
进一步地,参照图4,在本申请第一实施例的基础上,提出了本申请ASIC芯片晶圆的测试方法的第二实施例。Further, referring to FIG. 4, on the basis of the first embodiment of the present application, a second embodiment of the testing method of the ASIC chip wafer of the present application is proposed.
本实施例是第一实施例中步骤S10之后的步骤,本实施例与本申请第一实施例的区别在于:This embodiment is a step after step S10 in the first embodiment. The difference between this embodiment and the first embodiment of this application lies in:
步骤S50,将所述测试板中的信号控制板和继电器控制板恢复至默认值,以对所述测试板进行初始化;Step S50, restoring the signal control board and the relay control board in the test board to default values to initialize the test board;
步骤S60,在所述测试板初始化完成时,为所述信号控制板关联的数据通道配置测试信号,其中,所述测试信号包括通断测试信号和性能测试信号。Step S60, when the initialization of the test board is completed, configure a test signal for the data channel associated with the signal control board, where the test signal includes an on-off test signal and a performance test signal.
步骤S70,在所述数据通道中的测试信号配置完成时,对与所述测试板通信连接的运算放大器添加预设电压,以进行ASIC芯片晶圆测试。In step S70, when the configuration of the test signal in the data channel is completed, a preset voltage is added to the operational amplifier communicatively connected with the test board to perform ASIC chip wafer test.
测试设备将测试板中的信号控制板和继电器控制板恢复至默认值,以初始化测试板中的信号控制板和继电器控制板,在测试板初始化完成时,测试设备为信号控制板关联的数据通道配置测试数据,其中,测试数据包括通断测试数据和性能测试数据,测试设备在数据通道中的测试信号配置完成时,对与所述测试板通信连接的运算放大器(参考图3,运算放大器还可以用OPA标识)添加预设电压(预设电压可以根据测试板中测试单元的数量设置,例如预设电压为15v),以进行ASIC芯片晶圆测试。在本实施例中测试设备在给ASIC芯片发送测试信号之前,先对测试板进行初始化,使得ASIC芯片的测试结果更加准确。The test equipment restores the signal control board and the relay control board in the test board to the default values to initialize the signal control board and the relay control board in the test board. When the initialization of the test board is completed, the test device is the data channel associated with the signal control board Configure test data, where the test data includes continuity test data and performance test data. When the test signal configuration in the data channel is completed by the test equipment, the operational amplifier (refer to Figure 3, the operational amplifier is also connected to the test board) You can use the OPA logo) to add a preset voltage (the preset voltage can be set according to the number of test units in the test board, for example, the preset voltage is 15v) for ASIC chip wafer testing. In this embodiment, the test device initializes the test board before sending the test signal to the ASIC chip, so that the test result of the ASIC chip is more accurate.
进一步地,在上述实施例的基础上提出了本申请ASIC芯片晶圆的测试方法的第三实施例。Further, on the basis of the foregoing embodiments, a third embodiment of the test method for ASIC chip wafers of the present application is proposed.
本实施例是第一实施例中步骤S40之后的步骤,本实施例与上述实施例的区别在于:This embodiment is a step after step S40 in the first embodiment. The difference between this embodiment and the foregoing embodiment lies in:
若所述测试结果为测试不通过,则调用预设标记装置,通过所述预设标记装置标记异常的ASIC芯片。If the test result is that the test fails, the preset marking device is invoked, and the abnormal ASIC chip is marked by the preset marking device.
若测试结果为测试不通过,测试设备则调用预设标记装置(预设标记装置是指用于添加颜色的装置),测试设备通过预设标记装置标记异常的ASIC芯片。即,现有技术中在ASIC芯片晶圆测试时,会将测试数据在测试设备上进行显示,这样需要用户根据测试数据确定异常设备,而本申请实施例中,在判定ASIC芯片异常时,直接标记异常ASIC芯片,使得异常ASIC芯片查找更加快速。If the test result is that the test fails, the test equipment calls the preset marking device (the preset marking device refers to a device for adding colors), and the test equipment marks the abnormal ASIC chip through the preset marking device. That is, in the prior art, during the ASIC chip wafer test, the test data will be displayed on the test equipment, which requires the user to determine the abnormal equipment according to the test data. In the embodiment of the present application, when the ASIC chip is abnormal, the test data is directly displayed. Mark abnormal ASIC chips to make finding abnormal ASIC chips faster.
此外,本申请实施例还提出一种计算机存储介质。In addition, the embodiment of the present application also proposes a computer storage medium.
所述计算机存储介质上存储有计算机程序,所述计算机程序被处理器执行时运行以下步骤:A computer program is stored on the computer storage medium, and the following steps are executed when the computer program is executed by a processor:
在接收到芯片测试请求时,获取所述芯片测试请求对应的测试数量,将所述测试数量的ASIC芯片连接到所述测试板上;When a chip test request is received, obtain the test quantity corresponding to the chip test request, and connect the tested quantity of ASIC chips to the test board;
通过初始化后的所述测试板将通断测试信号发送至所述ASIC芯片,获得所述ASIC芯片与所述测试板之间的通断测试数据;Sending a continuity test signal to the ASIC chip through the initialized test board to obtain continuity test data between the ASIC chip and the test board;
若所述通断测试数据正常,则通过所述测试板将性能测试信号发送至所述ASIC芯片,获得所述ASIC芯片的性能测试数据;If the continuity test data is normal, sending a performance test signal to the ASIC chip through the test board to obtain the performance test data of the ASIC chip;
分析所述性能测试数据,获得所述ASIC芯片的测试结果。The performance test data is analyzed to obtain the test result of the ASIC chip.
在一实施例中,所述计算机程序被处理器执行所述在接收到芯片测试请求时,获取所述芯片测试请求对应的测试数量,将所述测试数量的ASIC芯片连接到所述测试板上的步骤之后,包括:In an embodiment, the computer program is executed by the processor. When a chip test request is received, the test quantity corresponding to the chip test request is acquired, and the tested quantity of ASIC chips are connected to the test board. After the steps, include:
将所述测试板中的信号控制板和继电器控制板恢复至默认值,以对所述测试板进行初始化;Restore the signal control board and the relay control board in the test board to default values to initialize the test board;
在所述测试板初始化完成时,为所述信号控制板关联的数据通道配置测试信号,其中,所述测试信号包括通断测试信号和性能测试信号;When the initialization of the test board is completed, configure a test signal for the data channel associated with the signal control board, where the test signal includes a continuity test signal and a performance test signal;
在所述数据通道中的测试信号配置完成时,对与所述测试板通信连接的运算放大器添加预设电压,以进行ASIC芯片晶圆测试。When the configuration of the test signal in the data channel is completed, a preset voltage is added to the operational amplifier communicatively connected with the test board to perform an ASIC chip wafer test.
在一实施例中,所述计算机程序被处理器执行所述通过初始化后的所述测试板将通断测试信号发送至所述ASIC芯片,获得所述ASIC芯片与所述测试板之间的通断测试数据的步骤,包括以下任意一个或多个:In an embodiment, the computer program is executed by the processor, and the test board that has passed the initialization sends a continuity test signal to the ASIC chip to obtain the communication between the ASIC chip and the test board. The steps to break test data include any one or more of the following:
通过初始化后的所述测试板中的工作电压接口VDD给所述ASIC芯片上电,将所述测试板中的输出接口OUT和工作电压接口VDD打到0V,并将所述测试板中的外接电压接口VMIC关闭,获得第一通断测试数据;和/或,The ASIC chip is powered on through the working voltage interface VDD in the test board after initialization, the output interface OUT and the working voltage interface VDD in the test board are set to 0V, and the external connection in the test board is set to 0V. The voltage interface VMIC is closed, and the first on-off test data is obtained; and/or,
通过初始化后的所述测试板中的输出接口OUT给所述ASIC芯片上电,将所述测试板中的输出接口OUT和工作电压接口VDD打到0V,并将所述测试板中的外接电压接口VMIC关闭,获得第二通断测试数据。The ASIC chip is powered on through the output interface OUT in the test board after initialization, the output interface OUT and the working voltage interface VDD in the test board are set to 0V, and the external voltage in the test board is set to 0V. The interface VMIC is closed, and the second on-off test data is obtained.
在一实施例中,所述计算机程序被处理器执行所述通过初始化后的所述测试板将通断测试信号发送至所述ASIC芯片,获得所述ASIC芯片与所述测试板之间的通断测试数据的步骤之后,包括:In an embodiment, the computer program is executed by the processor, and the test board that has passed the initialization sends a continuity test signal to the ASIC chip to obtain the communication between the ASIC chip and the test board. After the steps of breaking the test data, include:
判断所述通断测试数据是否在预设区间内;Judging whether the on-off test data is within a preset interval;
若所述通断测试数据不在所述预设区间内,则判定所述通断测试数据异常,并调整所述ASIC芯片的位置将调整后的所述ASIC芯片重新连接到所述测试板,以进行二次通断测试;If the continuity test data is not within the preset interval, it is determined that the continuity test data is abnormal, and the position of the ASIC chip is adjusted to reconnect the adjusted ASIC chip to the test board to Carry out the second continuity test;
若所述通断数据在所述预设区间内,则判定所述通断测试数据正常。If the on-off data is within the preset interval, it is determined that the on-off test data is normal.
在一实施例中,所述计算机程序被处理器执行所述若所述通断测试数据正常,则通过所述测试板将性能测试信号发送至所述ASIC芯片,获得所述ASIC芯片的性能测试数据的步骤,包括:In an embodiment, the computer program is executed by the processor. If the continuity test data is normal, the performance test signal is sent to the ASIC chip through the test board to obtain the performance test of the ASIC chip. The data steps include:
若所述通断测试数据正常,则通过所述测试板将第一性能测试信号发送至所述ASIC芯片,获得所述ASIC芯片的基础性能测试数据;If the continuity test data is normal, sending a first performance test signal to the ASIC chip through the test board to obtain basic performance test data of the ASIC chip;
在所述基础性能测试完成时,通过所述测试板将第二性能测试信号发送至所述ASIC芯片,获得所述ASIC芯片的工作性能测试数据,其中,所述工作性能测试数据包括:增益数据和/或失真数据;When the basic performance test is completed, a second performance test signal is sent to the ASIC chip through the test board to obtain work performance test data of the ASIC chip, wherein the work performance test data includes: gain data And/or distorted data;
在所述工作性能测试完成时,通过所述测试板将第三性能测试信号发送至所述ASIC芯片,获得所述ASIC芯片的抗干扰性能测试数据。When the work performance test is completed, a third performance test signal is sent to the ASIC chip through the test board to obtain the anti-interference performance test data of the ASIC chip.
在一实施例中,所述计算机程序被处理器执行所述分析所述性能测试数据,获得所述ASIC芯片的测试结果的步骤,包括:In an embodiment, the step of analyzing the performance test data to obtain the test result of the ASIC chip by the processor executing the computer program includes:
判断所述性能测试数据中的基础性能测试数据是否在预设第一数据区间内;Judging whether the basic performance test data in the performance test data is within a preset first data interval;
若所述基础性能测试数据在所述预设第一数据区间内,则判断所述性能测试数据中的工作性能测试数据是否在预设第二数据区间内;If the basic performance test data is within the preset first data interval, determining whether the work performance test data in the performance test data is within the preset second data interval;
若所述工作性能测试数据在所述预设第二数据区间内,则判断所述性能测试数据中的抗干扰性能测试数据是否在预设第三数据区间内;If the work performance test data is within the preset second data interval, determining whether the anti-interference performance test data in the performance test data is within the preset third data interval;
若所述抗干扰性能测试数据在所述预设第三数据区间内,则输出ASIC芯片测试通过的测试结果。If the anti-interference performance test data is within the preset third data interval, the test result of the ASIC chip test passing is output.
在一实施例中,所述计算机程序被处理器执行所述若所述工作性能测试数据在所述预设第一数据区间内,则判断所述性能测试数据中的抗干扰性能测试数据是否在预设第三数据区间内的步骤之后,包括:In an embodiment, the computer program is executed by the processor. If the work performance test data is within the preset first data interval, it is determined whether the anti-interference performance test data in the performance test data is in the After the steps in the third data interval are preset, the steps include:
若所述工作性能测试数据不在所述预设第二数据区间内,则调整所述第二性能测试信号;If the work performance test data is not within the preset second data interval, adjusting the second performance test signal;
通过所述测试板将调整后的第二性能测试信号发送至所述ASIC芯片,获得所述ASIC芯片新的工作性能测试数据,并判断新的工作性能测试数据是否在预设第二数据区间内,直至新的工作性能测试数据在所述预设第二数据区间内,或所述测试次数超过预设次数时输出测试不通过的提示信息。Send the adjusted second performance test signal to the ASIC chip through the test board, obtain new work performance test data of the ASIC chip, and determine whether the new work performance test data is within a preset second data interval , Until the new work performance test data is within the preset second data interval, or when the number of tests exceeds the preset number of times, a prompt message indicating that the test fails is output.
在一实施例中,所述计算机程序被处理器执行所述分析所述性能测试数据,获得所述ASIC芯片的测试结果的步骤之后,包括:In an embodiment, after the computer program is executed by the processor, the step of analyzing the performance test data and obtaining the test result of the ASIC chip includes:
若所述测试结果为测试不通过,则调用预设标记装置,通过所述预设标记装置标记异常的ASIC芯片。If the test result is that the test fails, the preset marking device is invoked, and the abnormal ASIC chip is marked by the preset marking device.
其中,安装测试程序的计算机存储介质实现的步骤可参照本申请ASIC芯片晶圆的测试方法的各个实施例,此处不再赘述。Among them, the steps implemented by the computer storage medium for installing the test program can refer to the various embodiments of the ASIC chip wafer test method of the present application, which will not be repeated here.
需要说明的是,在本文中,诸如第一和第二等之类的关系术语仅仅用来将一个实体/操作/对象与另一个实体/操作/对象区分开来,而不一定要求或者暗示这些实体/操作/对象之间存在任何这种实际的关系或者顺序;术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者系统不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者系统所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括该要素的过程、方法、物品或者系统中还存在另外的相同要素。It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity/operation/object from another entity/operation/object, and do not necessarily require or imply these There is any such actual relationship or order between entities/operations/objects; the terms "include", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, and sequence of a series of elements are included. An article or system includes not only those elements, but also other elements that are not explicitly listed, or include elements inherent to the process, method, article, or system. If there are no more restrictions, the element defined by the sentence "including a..." does not exclude the existence of other identical elements in the process, method, article, or system that includes the element.
对于装置实施例而言,由于其基本相似于方法实施例,所以描述得比较简单,相关之处参见方法实施例的部分说明即可。以上所描述的装置实施例仅仅是示意性的,其中作为分离部件说明的单元可以是或者也可以不是物理上分开的。可以根据实际的需要选择中的部分或者全部模块来实现本申请方案的目的。本领域普通技术人员在不付出创造性劳动的情况下,即可以理解并实施。As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for related parts, please refer to the part of the description of the method embodiment. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate. Some or all of the modules can be selected according to actual needs to achieve the objectives of the solution of the present application. Those of ordinary skill in the art can understand and implement it without creative work.
上述本申请实施例序号仅仅为了描述,不代表实施例的优劣。The serial numbers of the foregoing embodiments of the present application are for description only, and do not represent the superiority or inferiority of the embodiments.
通过以上的实施方式的描述,本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现,当然也可以通过硬件,但很多情况下前者是更佳的实施方式。基于这样的理解,本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来,该计算机软件产品存储在如上所述的一个存储介质(如ROM/RAM、磁碟、光盘)中,包括若干指令用以使得一台终端设备(可以是手机,计算机,服务器,空调器,或者网络设备等)执行本申请各个实施例所述的方法。Through the description of the above implementation manners, those skilled in the art can clearly understand that the above-mentioned embodiment method can be implemented by means of software plus the necessary general hardware platform, of course, it can also be implemented by hardware, but in many cases the former is better.的实施方式。 Based on this understanding, the technical solution of this application essentially or the part that contributes to the existing technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as ROM/RAM) as described above. , Magnetic disks, optical disks), including several instructions to make a terminal device (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute the method described in each embodiment of the present application.
以上仅为本申请的优选实施例,并非因此限制本申请的专利范围,凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换,或直接或间接运用在其他相关的技术领域,均同理包括在本申请的专利保护范围内。The above are only the preferred embodiments of the application, and do not limit the scope of the patent for this application. Any equivalent structure or equivalent process transformation made using the content of the description and drawings of the application, or directly or indirectly applied to other related technical fields , The same reason is included in the scope of patent protection of this application.