WO2021115288A1 - Procédé et dispositif de contrôle de plaquette de puces asic, et support d'informations informatique - Google Patents

Procédé et dispositif de contrôle de plaquette de puces asic, et support d'informations informatique Download PDF

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Publication number
WO2021115288A1
WO2021115288A1 PCT/CN2020/134664 CN2020134664W WO2021115288A1 WO 2021115288 A1 WO2021115288 A1 WO 2021115288A1 CN 2020134664 W CN2020134664 W CN 2020134664W WO 2021115288 A1 WO2021115288 A1 WO 2021115288A1
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WIPO (PCT)
Prior art keywords
test
data
asic chip
board
performance test
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PCT/CN2020/134664
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English (en)
Chinese (zh)
Inventor
宋友奎
陈建超
卞洛珍
刘栋星
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青岛歌尔微电子研究院有限公司
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Publication of WO2021115288A1 publication Critical patent/WO2021115288A1/fr

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections

Definitions

  • This application relates to the field of electronic technology, in particular to ASIC chip wafer testing methods, equipment and computer storage media.
  • ASIC Application Specific Integrated Circuit, integrated circuit
  • ASIC chip The characteristic of ASIC chip is to face the needs of specific users. After the ASIC chip is designed and formed, it is necessary to determine whether the ASIC chip is the same as the one designed on FPGA (Field-Programmable Gate Array). Testing, the current testing equipment determines the test signal according to the ASIC chip information and sends the test signal to the ASIC chip for ASIC chip wafer testing. This test method is only suitable for testing a small number of ASIC chips. If you need to test a batch of ASIC chips, only a small number of ASIC chips can be tested. Repeated testing results in low efficiency of batch ASIC chip testing.
  • FPGA Field-Programmable Gate Array
  • the main purpose of this application is to provide a testing method, equipment and computer storage medium for ASIC chip wafers, aiming to solve the current technical problem of low batch ASIC chip testing efficiency.
  • the present application provides a testing method for ASIC chip wafers.
  • the testing method for ASIC chip wafers is applied to a test device, and the test device is in communication connection with a test board;
  • the test method of the ASIC chip wafer includes the following steps:
  • the performance test data is analyzed to obtain the test result of the ASIC chip.
  • the method includes:
  • test signal for the data channel associated with the signal control board, where the test signal includes a continuity test signal and a performance test signal;
  • a preset voltage is added to the operational amplifier communicatively connected with the test board to perform an ASIC chip wafer test.
  • the step of sending a continuity test signal to the ASIC chip by the test board after initialization to obtain the continuity test data between the ASIC chip and the test board includes the following Any one or more:
  • the ASIC chip is powered on through the working voltage interface VDD in the test board after initialization, the output interface OUT and the working voltage interface VDD in the test board are set to 0V, and the external connection in the test board is set to 0V.
  • the voltage interface VMIC is closed, and the first on-off test data is obtained; and/or,
  • the ASIC chip is powered on through the output interface OUT in the test board after initialization, the output interface OUT and the working voltage interface VDD in the test board are set to 0V, and the external voltage in the test board is set to 0V.
  • the interface VMIC is closed, and the second on-off test data is obtained.
  • the method includes :
  • the step of sending a performance test signal to the ASIC chip through the test board to obtain the performance test data of the ASIC chip includes:
  • a second performance test signal is sent to the ASIC chip through the test board to obtain work performance test data of the ASIC chip, where the work performance test data includes: gain data And/or distorted data;
  • a third performance test signal is sent to the ASIC chip through the test board to obtain the anti-interference performance test data of the ASIC chip.
  • the step of analyzing the performance test data to obtain the test result of the ASIC chip includes:
  • the test result of the ASIC chip test passing is output.
  • the steps include:
  • the method includes:
  • the preset marking device is invoked, and the abnormal ASIC chip is marked by the preset marking device.
  • the present application also provides a testing device for ASIC chip wafers
  • the testing equipment for the ASIC chip wafer includes: a memory, a processor, and a computer program stored on the memory and running on the processor, wherein:
  • this application also provides a computer storage medium
  • a computer program is stored on the computer storage medium, and when the computer program is executed by a processor, the steps of the above-mentioned ASIC chip wafer test method are realized.
  • An ASIC chip wafer testing method, equipment, and computer storage medium are proposed in the embodiments of the application.
  • the test board is improved so that the test board can be connected to multiple ASIC chips, and the test device sends test signals to The test board sends test signals to the ASIC chip through the test board to test multiple ASIC chips at the same time.
  • multiple ASIC chips are tested at the same time, which reduces the test time of batch ASIC chips and improves the batch ASIC.
  • the test efficiency of the chip increases the productivity per unit time of ASIC chip wafer test.
  • the number of test equipment is reduced, thereby reducing the test land and test labor costs. .
  • FIG. 1 is a schematic diagram of a device structure of a hardware operating environment involved in a solution of an embodiment of the present application
  • FIG. 2 is a schematic flowchart of a first embodiment of a test method for ASIC chip wafers according to this application;
  • FIG. 3 is a schematic diagram of a test template in the first embodiment of the ASIC chip wafer test method in FIG. 2;
  • FIG. 4 is a schematic flowchart of a second embodiment of a test method for an ASIC chip wafer according to this application.
  • FIG. 1 is a test equipment (also called a terminal) of an ASIC chip wafer in the hardware operating environment involved in the embodiment of the application.
  • the test equipment of the ASIC chip wafer can be a separate ASIC chip wafer.
  • the structure of the test device can also be formed by combining other devices and the test device of the ASIC chip wafer).
  • the terminal in the embodiments of this application can be a fixed terminal or a mobile terminal, such as smart air conditioners with networking functions, smart lights, smart power supplies, smart speakers, autonomous vehicles, PC (personal computer) personal computers, smart phones, and tablet computers , E-book readers, portable computers, etc.
  • smart air conditioners with networking functions such as smart lights, smart power supplies, smart speakers, autonomous vehicles, PC (personal computer) personal computers, smart phones, and tablet computers , E-book readers, portable computers, etc.
  • the terminal may include: a processor 1001, for example, a central processing unit (CPU), a network interface 1004, a user interface 1003, a memory 1005, and a communication bus 1002.
  • the communication bus 1002 is used to implement connection and communication between these components.
  • the user interface 1003 may include a display screen (Display) and an input unit such as a keyboard (Keyboard), and the optional user interface 1003 may also include a standard wired interface and a wireless interface.
  • the network interface 1004 may optionally include a standard wired interface and a wireless interface (such as WIreless-FIdelity, WIFI interface).
  • the memory 1005 can be a high-speed RAM memory or a stable memory (non-volatile memory), for example, disk storage.
  • the memory 1005 may also be a storage device independent of the aforementioned processor 1001.
  • terminal structure shown in FIG. 1 does not constitute a limitation on the terminal, and may include more or less components than shown in the figure, or combine some components, or arrange different components.
  • the computer software product is stored in a storage medium (storage medium: also called computer storage medium, computer medium, readable medium, readable storage medium, computer readable storage medium, or directly called medium, etc., storage medium
  • storage medium can be a non-volatile readable storage medium, such as RAM, magnetic disk, optical disk, and includes several instructions to make a terminal device (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute this application
  • the memory 1005 as a computer storage medium may include an operating system, a network communication module, a user interface module, and a computer program.
  • the network interface 1004 is mainly used to connect to the back-end server and communicate with the back-end server; the user interface 1003 is mainly used to connect to the client (user side) and communicate with the client; and the processor 1001 can be used to call a computer program stored in the memory 1005 and execute the steps in the ASIC chip wafer testing method provided in the following embodiments of the present application.
  • the test method of the ASIC chip wafer includes:
  • step S10 when a chip test request is received, the test quantity corresponding to the chip test request is obtained, and the ASIC chip of the test quantity is connected to the test board.
  • the test method of the ASIC chip wafer in this embodiment is applied to the test equipment.
  • the test equipment receives the chip test request.
  • the triggering method of the chip test request is not specifically limited, that is, the chip test request can be triggered by the user, for example, the test device A virtual test button is set on the display screen of the, and the user clicks the virtual test button to actively trigger the chip test request; in addition, the chip test request can also be automatically triggered by the test device.
  • the trigger condition of the preset chip test request in the test device is: When the ASIC chip is detected in the production, the test equipment automatically triggers the chip test request when the ASIC chip is detected.
  • the test device When the test device receives the chip test request, the test device obtains the test quantity corresponding to the chip test request, the test device controls the position of the mobile ASIC chip, and connects the tested number of ASIC chips to the test board; the test board in this embodiment
  • the test board includes a preset number of test units (the preset number refers to the maximum number of single tests set in advance, for example, the preset number is 16).
  • the preset number refers to the maximum number of single tests set in advance, for example, the preset number is 16).
  • the test unit includes the test signal input interface INPM, the external voltage interface VMIC, the ground terminal interface VSS, the output interface OUT and the working voltage interface VDD.
  • the test equipment uses the test board to test the ASIC chip, specifically:
  • step S20 the continuity test signal is sent to the ASIC chip through the initialized test board, and the continuity test data between the ASIC chip and the test board is obtained.
  • the test equipment passes the initialized test board and will turn on and off the test signal
  • the on-off test signal refers to the signal used to test the connection state of the ASIC chip and the test board
  • the on-off test signal is the signal to power on the ASIC chip, for example, on-off
  • the test signal is sent to the ASIC chip through the working voltage interface VDD in the test board to power up the ASIC chip (100uA) to obtain the continuity test data between the ASIC chip and the test board.
  • the test signal is sent to the ASIC chip through the working voltage interface VDD in the test board to power up the ASIC chip (100uA) to obtain the continuity test data between the ASIC chip and the test board.
  • VDD working voltage interface
  • the test board to power up the ASIC chip (100uA) to obtain the continuity test data between the ASIC chip and the test board.
  • it includes:
  • Step a1 power on the ASIC chip through the working voltage interface VDD in the test board after initialization, set the output interface OUT and working voltage interface VDD in the test board to 0V, and set the test board
  • the external voltage interface VMIC in the device is closed, and the first on-off test data is obtained; and/or,
  • Step a2 the ASIC chip is powered on through the output interface OUT in the test board after initialization, the output interface OUT and the working voltage interface VDD in the test board are set to 0V, and the test board is The external voltage interface VMIC is closed, and the second on-off test data is obtained.
  • the test device powers on the ASIC chip through the working voltage interface VDD in the initialized test board.
  • the test device turns the output interface OUT and the working voltage interface VDD in the test board to 0V, and connects the external voltage interface VMIC in the test board. Close to obtain the first continuity test data; and/or, the test device powers on the ASIC chip through the output interface OUT in the initialized test board, and the test device turns the output interface OUT and the working voltage interface VDD in the test board to 0V, and turn off the external voltage interface VMIC in the test board to obtain the second on-off test data.
  • the test equipment first pulls the pin of the output interface OUT in the test board to 0V; secondly, it provides the working voltage interface VDD in the test board with a current of -100uA (or 100uA), and then in 10ms Then measure the O/S value; then pull the VDD pin of the working voltage interface in the test board to 0V, and close the data channel corresponding to the external voltage interface VMIC; finally, the test equipment closes the data channel corresponding to the OUT pin of the output interface, and the test equipment obtains The first continuity test data; and/or, the test equipment first pulls the pin of the working voltage interface VDD in the test board to 0V, and then provides the output interface OUT in the test board with -100uA current (or 100uA current), about 10ms later Measure the OS value; the test equipment turns the OUT pin of the output interface on the test board to 0V, and closes the data channel corresponding to the OUT pin of the output interface.
  • the test equipment transmits the continuity test signal to the test board, and the pins of each interface in the test board are adjusted with the continuity test signal to obtain the continuity test data.
  • the test equipment determines the test according to the continuity test data. Whether the connection between the board and the ASIC chip is normal, that is, after obtaining the continuity test data between the ASIC chip and the test board, the test equipment determines whether the continuity test data is normal, specifically, including:
  • Step b1 judging whether the continuity test data is within a preset interval
  • Step b2 if the continuity test data is not within the preset interval, determine that the continuity test data is abnormal, and adjust the position of the ASIC chip to reconnect the adjusted ASIC chip to the test Board for the second continuity test;
  • step b3 if the on-off data is within the preset interval, it is determined that the on-off test data is normal.
  • the test equipment determines whether the continuity test data is within a preset interval (the preset interval is set according to the continuity test signal); if the continuity test data is not within the preset interval, the test equipment determines that the continuity test data is abnormal, The test equipment adjusts the position of the ASIC chip, and the test equipment reconnects the adjusted ASIC chip to the test board to perform a secondary on-off test.
  • the test equipment determines that the continuity test data is normal, and the test equipment further tests the performance of the ASIC chip wafer, specifically:
  • Step S30 If the continuity test data is normal, the performance test signal is sent to the ASIC chip through the test board to obtain the performance test data of the ASIC chip.
  • the test equipment sends the performance test signal (the performance test signal refers to the test signal used to test the performance of the ASIC chip, for example, the performance test signal sends a sine wave to the ASIC chip through the test board) through the test board ASIC chip, to obtain the performance test data of the ASIC chip, specifically, including:
  • Step c1 If the continuity test data is normal, the first performance test signal is sent to the ASIC chip through the test board to obtain the basic performance test data of the ASIC chip.
  • Step c2 When the basic performance test is completed, a second performance test signal is sent to the ASIC chip through the test board to obtain work performance test data of the ASIC chip, where the work performance test data includes : Gain data and/or distortion data.
  • Step c3 When the work performance test is completed, a third performance test signal is sent to the ASIC chip through the test board to obtain the anti-interference performance test data of the ASIC chip.
  • the test device sends the first performance test signal to the ASIC chip through the test board (the first performance test signal refers to the signal for the basic performance test of the chip, for example, to the working voltage interface in the test board VDD provides 2V or 3V working voltage) to obtain basic performance test data of ASIC chip (basic performance test data includes chip working current IDD, voltage output, etc.).
  • the first performance test signal refers to the signal for the basic performance test of the chip, for example, to the working voltage interface in the test board VDD provides 2V or 3V working voltage
  • basic performance test data includes chip working current IDD, voltage output, etc.
  • the test equipment sends the second performance test signal through the test board (the second performance test signal refers to the signal for testing the performance of the chip, for example, provides 2V to the working voltage interface VDD in the test board, and passes The test board outputs a 100 kHz sine wave) and sends it to the ASIC chip to obtain work performance test data of the ASIC chip.
  • the work performance test data includes gain data and/or distortion data.
  • the test equipment sends the third performance test signal through the test board (the third performance test signal refers to the signal for the anti-interference performance test of the chip, for example, provides 2V to the working voltage interface VDD in the test board, and Through the test board, output a 100 kHz sine wave) and send it to the ASIC chip to obtain the anti-jamming performance test data of the ASIC chip.
  • the third performance test signal refers to the signal for the anti-interference performance test of the chip, for example, provides 2V to the working voltage interface VDD in the test board, and Through the test board, output a 100 kHz sine wave
  • the steps of the testing device in this embodiment to perform performance testing on the chip include:
  • the basic performance test of the ASIC chip includes: the test equipment sends the first performance test signal to the ASIC chip through the VDD in the test board, and the first performance test signal is 2V when the power is on; the test equipment waits for 30ms and measures the output current Idd and the ASIC chip at the same time.
  • the output voltage Vout is used as the basic performance test data; or the test equipment sends the first performance test signal to the ASIC chip through VDD in the test board, and the first performance test signal is power-on 3V; the test equipment waits for 30ms and simultaneously measures the ASIC chip output current Idd and The output voltage Vout is used as the basic performance test data.
  • the ASIC chip performance test includes: the test equipment sends a second performance test signal to the ASIC chip through the test board, where the second performance test signal is to disconnect the INPM from the test board to the ground, and connect the control switch to OUT. Test pin, control the switch to connect INPM to the test pin, the test board outputs a 100KHz sine wave to the ASIC chip, power off VDD and reconfigure VDD to 2V, get ASIC chip gain data and/or distortion data, as work Performance test data.
  • ASIC chip anti-jamming performance test includes: the test equipment sends the third performance test signal to the ASIC chip through the test board, where the third performance test signal is to power up the ASIC chip by 2V through the test board VDD and send 100 kHz to the ASIC chip Sine wave to obtain the anti-jamming performance test data.
  • Step S40 Analyze the performance test data to obtain the test result of the ASIC chip.
  • the test equipment in this embodiment determines to collect the corresponding performance test data, analyzes the performance test data, and obtains the test result of the ASIC chip, which specifically includes:
  • Step d1 judging whether the basic performance test data in the performance test data is within a preset first data interval
  • Step d2 if the basic performance test data is within the preset first data interval, determine whether the work performance test data in the performance test data is within the preset second data interval;
  • Step d3 if the work performance test data is within the preset second data interval, determine whether the anti-interference performance test data in the performance test data is within the preset third data interval;
  • Step d4 If the anti-interference performance test data is within the preset third data interval, output the test result of the ASIC chip test passing.
  • the test equipment determines whether the basic performance test data in the performance test data is within the preset first data interval (the preset first data interval is set according to the first performance test signal); if the basic performance test data is not in the preset first data If the basic performance test data is within the preset first data interval, the test only determines whether the work performance test data in the performance test data is within the preset second data interval (preset Suppose that the second data interval is set according to the second performance test signal); if the work performance test data is not within the preset second data interval, the test equipment marks the ASIC chip as abnormal; if the work performance test data is in the preset second data In the interval, the test equipment judges whether the anti-interference performance test data in the performance test data is within the preset third data interval (the preset third data interval is set according to the third performance test signal); Assuming that it is in the third data interval, the test equipment marks the ASIC chip as abnormal; if the anti-interference performance test data is in the preset third data interval, the test result that the A
  • the test device adjusts the second performance test signal; the test device sends the adjusted second performance test signal to the ASIC through the test board
  • the chip obtains new work performance test data of the ASIC chip, and determines whether the new work performance test data is within the preset second data interval, until the new work performance test data is within the preset second data interval, or the test
  • the number of times exceeds the preset number the preset number can be flexibly set according to the scene, for example, set to 10 times
  • a prompt message indicating that the test failed is output.
  • the test board is improved so that the test board can be connected to multiple ASIC chips.
  • the test equipment sends test signals to the test board and the test board sends the test signals to the ASIC chip to test multiple ASIC chips at the same time.
  • multiple ASIC chips are tested at the same time, the test time of batch ASIC chips is reduced, the test efficiency of batch ASIC chips is improved, and the unit time productivity of ASIC chip wafer testing is increased.
  • due to one Testing multiple ASIC chips on the test board reduces the number of test equipment, thereby reducing test land and test labor costs.
  • This embodiment is a step after step S10 in the first embodiment.
  • the difference between this embodiment and the first embodiment of this application lies in:
  • Step S50 restoring the signal control board and the relay control board in the test board to default values to initialize the test board
  • Step S60 when the initialization of the test board is completed, configure a test signal for the data channel associated with the signal control board, where the test signal includes an on-off test signal and a performance test signal.
  • step S70 when the configuration of the test signal in the data channel is completed, a preset voltage is added to the operational amplifier communicatively connected with the test board to perform ASIC chip wafer test.
  • the test equipment restores the signal control board and the relay control board in the test board to the default values to initialize the signal control board and the relay control board in the test board.
  • the test device is the data channel associated with the signal control board Configure test data, where the test data includes continuity test data and performance test data.
  • the operational amplifier (refer to Figure 3, the operational amplifier is also connected to the test board) You can use the OPA logo) to add a preset voltage (the preset voltage can be set according to the number of test units in the test board, for example, the preset voltage is 15v) for ASIC chip wafer testing.
  • the test device initializes the test board before sending the test signal to the ASIC chip, so that the test result of the ASIC chip is more accurate.
  • This embodiment is a step after step S40 in the first embodiment.
  • the difference between this embodiment and the foregoing embodiment lies in:
  • the preset marking device is invoked, and the abnormal ASIC chip is marked by the preset marking device.
  • the test equipment calls the preset marking device (the preset marking device refers to a device for adding colors), and the test equipment marks the abnormal ASIC chip through the preset marking device. That is, in the prior art, during the ASIC chip wafer test, the test data will be displayed on the test equipment, which requires the user to determine the abnormal equipment according to the test data. In the embodiment of the present application, when the ASIC chip is abnormal, the test data is directly displayed. Mark abnormal ASIC chips to make finding abnormal ASIC chips faster.
  • the embodiment of the present application also proposes a computer storage medium.
  • a computer program is stored on the computer storage medium, and the following steps are executed when the computer program is executed by a processor:
  • the performance test data is analyzed to obtain the test result of the ASIC chip.
  • the computer program is executed by the processor.
  • the test quantity corresponding to the chip test request is acquired, and the tested quantity of ASIC chips are connected to the test board. After the steps, include:
  • test signal for the data channel associated with the signal control board, where the test signal includes a continuity test signal and a performance test signal;
  • a preset voltage is added to the operational amplifier communicatively connected with the test board to perform an ASIC chip wafer test.
  • the computer program is executed by the processor, and the test board that has passed the initialization sends a continuity test signal to the ASIC chip to obtain the communication between the ASIC chip and the test board.
  • the steps to break test data include any one or more of the following:
  • the ASIC chip is powered on through the working voltage interface VDD in the test board after initialization, the output interface OUT and the working voltage interface VDD in the test board are set to 0V, and the external connection in the test board is set to 0V.
  • the voltage interface VMIC is closed, and the first on-off test data is obtained; and/or,
  • the ASIC chip is powered on through the output interface OUT in the test board after initialization, the output interface OUT and the working voltage interface VDD in the test board are set to 0V, and the external voltage in the test board is set to 0V.
  • the interface VMIC is closed, and the second on-off test data is obtained.
  • the computer program is executed by the processor, and the test board that has passed the initialization sends a continuity test signal to the ASIC chip to obtain the communication between the ASIC chip and the test board.
  • the steps of breaking the test data include:
  • the computer program is executed by the processor. If the continuity test data is normal, the performance test signal is sent to the ASIC chip through the test board to obtain the performance test of the ASIC chip.
  • the data steps include:
  • a second performance test signal is sent to the ASIC chip through the test board to obtain work performance test data of the ASIC chip, wherein the work performance test data includes: gain data And/or distorted data;
  • a third performance test signal is sent to the ASIC chip through the test board to obtain the anti-interference performance test data of the ASIC chip.
  • the step of analyzing the performance test data to obtain the test result of the ASIC chip by the processor executing the computer program includes:
  • the test result of the ASIC chip test passing is output.
  • the computer program is executed by the processor. If the work performance test data is within the preset first data interval, it is determined whether the anti-interference performance test data in the performance test data is in the After the steps in the third data interval are preset, the steps include:
  • the step of analyzing the performance test data and obtaining the test result of the ASIC chip includes:
  • the preset marking device is invoked, and the abnormal ASIC chip is marked by the preset marking device.
  • the steps implemented by the computer storage medium for installing the test program can refer to the various embodiments of the ASIC chip wafer test method of the present application, which will not be repeated here.
  • the description is relatively simple, and for related parts, please refer to the part of the description of the method embodiment.
  • the device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate. Some or all of the modules can be selected according to actual needs to achieve the objectives of the solution of the present application. Those of ordinary skill in the art can understand and implement it without creative work.
  • the technical solution of this application essentially or the part that contributes to the existing technology can be embodied in the form of a software product, and the computer software product is stored in a storage medium (such as ROM/RAM) as described above. , Magnetic disks, optical disks), including several instructions to make a terminal device (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) execute the method described in each embodiment of the present application.
  • a terminal device which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.

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Abstract

L'invention concerne un procédé et un dispositif de contrôle de plaquette de puces ASIC, et un support d'informations informatique, le procédé de contrôle de plaquette de puces ASIC étant utilisé par un dispositif de contrôle, et le dispositif de contrôle formant une connexion de communication avec une carte de contrôle. Les étapes du procédé de contrôle consistent : en ce que, lors de la réception d'une requête de contrôle de puce, une quantité de contrôle correspondant à la requête de contrôle de puce est obtenue, et ladite quantité de contrôle de puces ASIC est connectée sur la carte de contrôle (S10) ; en ce que des signaux de contrôle d'activation/désactivation sont envoyés aux puces ASIC au moyen de la carte de contrôle initialisée, et que des données de contrôle d'activation/désactivation entre les puces ASIC et la carte de contrôle sont obtenues (S20) ; en ce que, si les données de contrôle d'activation/désactivation sont normales, des signaux de contrôle de performance sont envoyés aux puces ASIC au moyen de la carte de contrôle, et des données de contrôle de performance pour les puces ASIC sont obtenues (S30) ; en ce que les donnéess de contrôle de performance sont analysées, et que des résultats de contrôle pour les puces ASIC sont obtenus (S40).
PCT/CN2020/134664 2019-12-09 2020-12-08 Procédé et dispositif de contrôle de plaquette de puces asic, et support d'informations informatique WO2021115288A1 (fr)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113740703A (zh) * 2021-07-28 2021-12-03 苏州浪潮智能科技有限公司 一种Retimer芯片的测试板及测试系统
CN115629300A (zh) * 2022-12-22 2023-01-20 北京怀美科技有限公司 芯片检测方法及芯片检测系统

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110888042B (zh) * 2019-12-09 2022-02-25 青岛歌尔微电子研究院有限公司 Asic芯片晶圆的测试方法、设备和计算机存储介质
CN117012258B (zh) * 2023-09-26 2024-01-02 合肥康芯威存储技术有限公司 一种存储芯片状态数据的分析装置、方法及介质

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7042237B2 (en) * 2004-03-11 2006-05-09 Winbond Electronics Corporation Semiconductor test system having a tester and a prober and test method thereof
CN2872379Y (zh) * 2005-11-25 2007-02-21 普诚科技股份有限公司 可同时测试多个待测芯片的测试装置以及单颗芯片测试机
CN101713812A (zh) * 2009-11-26 2010-05-26 北京中星微电子有限公司 一种ic设计电路板的测试系统、方法及一种测试接口板
CN203786219U (zh) * 2014-01-28 2014-08-20 霍尼韦尔腾高电子系统（广州）有限公司 一种多功能自动化测试系统
CN104425306A (zh) * 2013-09-05 2015-03-18 致茂电子股份有限公司 具有开路测试的半导体封装构件测试系统和方法
CN205210257U (zh) * 2015-10-30 2016-05-04 广东利扬芯片测试股份有限公司 一种带自检功能的集成电路测试板
CN106251907A (zh) * 2016-08-04 2016-12-21 武汉新芯集成电路制造有限公司 内建自测系统及方法
CN207851236U (zh) * 2017-11-13 2018-09-11 北京集创北方科技股份有限公司 一种芯片测试板及芯片测试系统
CN109633417A (zh) * 2019-01-31 2019-04-16 上海华虹宏力半导体制造有限公司 多芯片同测结构及方法
CN110888042A (zh) * 2019-12-09 2020-03-17 青岛歌尔微电子研究院有限公司 Asic芯片晶圆的测试方法、设备和计算机存储介质

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5629876A (en) * 1992-07-10 1997-05-13 Lsi Logic Corporation Method and apparatus for interim in-situ testing of an electronic system with an inchoate ASIC
JPH08254570A (ja) * 1995-03-16 1996-10-01 Fujitsu Ltd 半導体集積回路
US6016563A (en) * 1997-12-30 2000-01-18 Fleisher; Evgeny G. Method and apparatus for testing a logic design of a programmable logic device
KR100272503B1 (ko) * 1998-01-26 2000-11-15 김영환 고속테스트기능의램버스주문형집적회로및그를이용한테스트방법
US7576551B2 (en) * 2007-09-20 2009-08-18 Visera Technologies Company Limited Test socket and test board for wafer level semiconductor testing
CN203732574U (zh) * 2014-03-24 2014-07-23 成都先进功率半导体股份有限公司 一种用于sod882芯片测试的pcb测试板
CN104505125B (zh) * 2014-12-04 2018-07-13 中国科学院微电子研究所 一种多通道sram单粒子测试方法及装置
CN105717439B (zh) * 2016-02-24 2019-07-12 上海东软载波微电子有限公司 芯片测试方法及系统
CN108519938B (zh) * 2018-04-13 2021-12-28 珠海全志科技股份有限公司 存储芯片兼容性测试方法、系统和测试主机
CN208766207U (zh) * 2018-08-24 2019-04-19 西门子数控（南京）有限公司 Pcb测试夹具
CN109342928B (zh) * 2018-11-01 2021-10-26 南京工业大学 一种芯片测试装置及方法
CN109633413A (zh) * 2018-12-28 2019-04-16 芯海科技（深圳）股份有限公司 一种32位mcu芯片测试系统及其测试方法

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7042237B2 (en) * 2004-03-11 2006-05-09 Winbond Electronics Corporation Semiconductor test system having a tester and a prober and test method thereof
CN2872379Y (zh) * 2005-11-25 2007-02-21 普诚科技股份有限公司 可同时测试多个待测芯片的测试装置以及单颗芯片测试机
CN101713812A (zh) * 2009-11-26 2010-05-26 北京中星微电子有限公司 一种ic设计电路板的测试系统、方法及一种测试接口板
CN104425306A (zh) * 2013-09-05 2015-03-18 致茂电子股份有限公司 具有开路测试的半导体封装构件测试系统和方法
CN203786219U (zh) * 2014-01-28 2014-08-20 霍尼韦尔腾高电子系统（广州）有限公司 一种多功能自动化测试系统
CN205210257U (zh) * 2015-10-30 2016-05-04 广东利扬芯片测试股份有限公司 一种带自检功能的集成电路测试板
CN106251907A (zh) * 2016-08-04 2016-12-21 武汉新芯集成电路制造有限公司 内建自测系统及方法
CN207851236U (zh) * 2017-11-13 2018-09-11 北京集创北方科技股份有限公司 一种芯片测试板及芯片测试系统
CN109633417A (zh) * 2019-01-31 2019-04-16 上海华虹宏力半导体制造有限公司 多芯片同测结构及方法
CN110888042A (zh) * 2019-12-09 2020-03-17 青岛歌尔微电子研究院有限公司 Asic芯片晶圆的测试方法、设备和计算机存储介质

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113740703A (zh) * 2021-07-28 2021-12-03 苏州浪潮智能科技有限公司 一种Retimer芯片的测试板及测试系统
CN113740703B (zh) * 2021-07-28 2023-11-10 苏州浪潮智能科技有限公司 一种Retimer芯片的测试板及测试系统
CN115629300A (zh) * 2022-12-22 2023-01-20 北京怀美科技有限公司 芯片检测方法及芯片检测系统

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