CN102999140A - Power-on timing sequence control system and method of PCIE (Peripheral Component Interface Express) board card - Google Patents
Power-on timing sequence control system and method of PCIE (Peripheral Component Interface Express) board card Download PDFInfo
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Abstract
The invention provides a power-on timing sequence control system and method of a PCIE (Peripheral Component Interface Express) board card. The system comprises a self-adaptation circuit, a delaying circuit, an overheating protection unit and a recovering circuit. The method is used for carrying out delaying control on other direct-current power supplies through a direct-current power supply 1 (P1). According to the power-on timing sequence control system and method of the PCIE board card, the board card can be powered on in a shorter time T and each power supply needed by a sub-card can be powered on according to a certain sequence; a sub-card support slot and a self-adaptation manner of supplying power by double power supplies of external power supplies are adopted to support a heat resetting function; and after overheating protection is carried out and the temperature of the sub-card is reduced to a safe range, the sub-card automatically recovers the normal work and a main board does not need to be started again.
Description
Technical field
The invention belongs to computer realm, be specifically related to a kind of electrifying timing sequence control system and method for PCIE integrated circuit board.
Background technology
More existing PCIE subcards are because the electrifying timing sequence design problem causes subcard not happened occasionally by the situation of the normal identification of mainboard, but the reboot mainboard just can recognize, it is slow that reason just is that subcard powered on, it is undesired to reset, at present a lot of subcards slow reason that powers on also is following reason: along with the subcard functional requirement becomes increasingly complex, the subcard design is complicated gradually, power type on the subcard also is on the increase, and the electric sequence requirement is arranged between each power supply on the subcard, after the common electric sequence control of most people way is P1ok, allowing P1 remove to control P2 begins to power on, P2 control P3 goes to power on, Pn is controlled by P (n-1) by that analogy, like this, the time-to-climb that the final power-on time of Pn module being the power supply of P1+P2+P3+...+P (n-1)+Pn, add again P1 to the delay control time of P2, P2 to the delay of P3 until P (n-1) to control time of Pn, often because P1, P2, the P3...Pn power module total the time-to-climb oversize to cause subcard to power on slow, the reset_L that final mainboard is issued subcard has drawn high inefficacy, and the subcard power supply is not yet stable, thereby can't finish normal reset_L, cause the abnormal problem of function.
At present a lot of PCIE subcards are not generally all done overheating protection; integrated circuit board not damaged (Chip temperature in fan failure or the abominable situation of environment on the integrated circuit board raises and will damage when surpassing the scope that Chip can stand) can be effectively protected in this overheating protection; even some subcard has been done overheating protection in addition; but because after the overheated power-off protection of subcard; the PCIE link of Chip and mainboard has disconnected; subcard will work on; necessary reboot mainboard; like this; if also have other application need to continue running on the mainboard, obviously the reboot mainboard is not too suitable.
In the situation about increasing gradually along with the chip power-consumption on the present PCIE card; only be that PCIE groove 75W power supply may be not enough to satisfy power requirement; and during some motherboard design because all limiting factors can't provide the 75W power supply; thereby cause some can't work according to the PCIE subcard electricity shortage of Specification Design; and the way of some subcard is to reserve a power connector at subcard usually; when main board power supply is not enough by outer power supply; way is to do switching between the power connector of PCIE golden finger and reservation; usually use the different path of welding and do selection; or the mode of use wire jumper; this dual mode has obvious defective; the mode of choosing weldering is dumb; may need to adjust for different main board power supply abilities; consistance is poor; and troublesome poeration; forming the words of going again to weld behind the product can make troubles; use the mode of wire jumper; need first to electricity under the mainboard; take off subcard and also since the subcard power consumption large; need electric current larger; thereby need multiplex several wire jumper in parallel; the PCB layout impact is larger; and can make equally the assembling of some subcards inconsistent; be with inconvenience to commercialization, or even subcard can cause confusion to be made mistakes when inconsistent, the technical support trouble; the shortcomings such as it is also not too convenient to use, and service efficiency is low.If all unify to use the external cable power supply of power connector, do not accomplish also that sometimes because very do not make things convenient for the wiring cable on the equipment of the slotting PCIE card that has, so self-adaptation seems important.
Summary of the invention
For overcoming defects; the invention provides a kind of electrifying timing sequence control system and method for PCIE integrated circuit board; allowing integrated circuit board finish in short period T (such as 50ms) powers on; each power supply that the assurance subcard needs is finished in a certain order and is powered on; adopt subcard to support slot and external power supply dual power supply adaptive mode, support the hot reset function, and after overheating protection; after the subcard temperature dropped to safe range, subcard automatically recovered normal operation and need not to restart mainboard.
For achieving the above object, the invention provides a kind of electrifying timing sequence control system of PCIE integrated circuit board, it comprises: direct supply (P1, P4) and chip (1,2); Its improvements are that described electrifying timing sequence control system comprises: electric unit, overheating protection unit and restoring circuit in adaptive circuit, the time-delay; Described adaptive circuit one end accesses respectively 12V external power supply and 12V PCIE power supply, the other end respectively with described direct supply (P1) be connected direct supply (P4) and be connected; Described chip (1) respectively with described direct supply (P1), described time-delay on electric unit, described restoring circuit, described chip (2) be connected the overheating protection unit and be connected; Described chip (2) respectively be connected direct supply (P4) be connected restoring circuit and connect.
In the optimal technical scheme provided by the invention, described adaptive circuit comprises: the bleeder circuit, triode and the electronic switch that connect successively; Described bleeder circuit is connected with the 12V external power supply; Described electronic switch accesses 12V external power supply and 12V PCIE power supply, and is connected with the Vin input of described direct supply (P1).
In the second optimal technical scheme provided by the invention, electric unit comprises in the described time-delay: delay circuit (1,2), electronic switch (2,3) and direct supply (P2, P3); Described delay circuit (1), electronic switch (2) are connected P2 with direct supply) connect successively; Described delay circuit (2), electronic switch (3) are connected P3 with direct supply) connect successively; Described delay circuit (1) be connected delay circuit (2) and be connected with described direct supply (P1) respectively; Described direct supply (P2) and described direct supply (P3) receive respectively the 12V voltage of described adaptive circuit transmission, and described direct supply (P2) is connected with described chip (1).
In the 3rd optimal technical scheme provided by the invention, described delay circuit comprises: resistance (R490, R491, R492, R683, R881, R882, R883), electric capacity (C812, C814), triode (Q79, Q81) and power module; Described power module arranges link (1,2,3,4,5,6,7,8); R491 one termination is received data-signal, and the other end and C812 are connected the base stage of parallel-connection structure and Q79 and are connected the other end of the parallel-connection structure of C812 and R492 and the grounded emitter of Q79 with R492; The collector of Q79 is connected with the 3.3V direct supply by R490, and is connected with the base stage of Q81 by R882; The grounded emitter of Q81, collector are connected with the end of R883; The other end of R883 is connected an end with the end of C814 respectively and is connected with R683; The end that C814 is connected with R883 also is connected with the end (3) of described power module; In described power module, end (1) is the power supply input pin, end (4) is unsettled pin, and end (5) connects regulating resistor R881, R881 other end ground connection, end (6) reaches indicator signal after the desired stationary value for out-put supply, can be unsettled, end (2,7) ground connection, end (8) is the power module output pin, and end (3) is that power module enables control end.
In the 4th optimal technical scheme provided by the invention, described overheating protection unit comprises: thermal sensor, overheating protection circuit and thermal sensor control chip; Described thermal sensor respectively be connected chip (1), described overheating protection circuit and the thermal sensor control chip of being connected and connect; Described thermal sensor control chip is controlled described thermal sensor by control bus.
In the 5th optimal technical scheme provided by the invention, it is the chip of TLR36480 that described thermal sensor control chip adopts model; Described control bus is iic bus.
In the 6th optimal technical scheme provided by the invention, described overheating protection circuit comprises that model is the power module of PMR5118 and the chip of connected model LM95235QEIMM/NOPb; The chip of described model PMR5118 is connected with described thermal sensor.
In the 7th optimal technical scheme provided by the invention, described restoring circuit comprise PCIE Switch chip, PCIE connector and with door; Described PCIE Switch chip by the PCIE passage respectively be connected chip (1) and the PCIE connector connection of being connected; Describedly receive respectively the Reset_L signal that described PCIE Switch chip and described PCIE connector send with door, and according to the signal that receives to described chip (1) control that resets.
In the 8th optimal technical scheme provided by the invention, described PCIE Switch chip is provided with the GPIO port that sends restoring signal to described chip (1); Described PCIE switch chip has the hot reset function.
In the 9th optimal technical scheme provided by the invention, described chip (1) and described chip (2) are the chip with the PCIE interface.
In the tenth optimal technical scheme provided by the invention, provide a kind of power-on time sequence control method of PCIE integrated circuit board, its improvements are that described method comprises the steps:
(1). by direct supply (P1) chip (1) is powered on;
(2). the opening time tsi (1＜=i＜=n, n＜=3) of test direct supply Pi;
(3). calculate to the direct supply (P2, P3) of chip (1) power supply and finish the time interval Ti (1＜i＜=n, n＜=3) that powers on direct supply (P1) power supply respectively;
(4). calculate the delay time td3 of the delay circuit between direct supply (P3) and direct supply (P1);
(5). the parameter of computation delay circuit 2;
(6). calculate the delay time td2 of the delay circuit between direct supply (P2) and direct supply (P1);
(7). the parameter of computation delay circuit 1;
(8). according to the opening time tsi of the time interval Ti that obtains and direct supply, to calculating (1＜i＜=n, n＜=3) time delay of the delay circuit of direct supply Pi;
(9). according to result of calculation, operation powers on to direct supply Pi (1＜i＜=n, n＜=3).
In the more preferably technical scheme provided by the invention, after described step 9, described method comprises the steps:
(a). whether the temperature of surveying the chip (1) that powers on is too high, if then with chip (1) outage, and carries out overheating protection;
(b). survey whether returned to normal working temperature by the temperature of the chip of overheating protection, if then to chip power, recover the normal operation of chip.
Provided by the invention second more preferably in the technical scheme, and in described step 4, the computing formula of Ti is as follows:
Ti＝(T-10-ts1)*(i-1)/(n-1)
Wherein, Ti is denoted as in i power supply and the 1st time interval that power supply is finished to power on, then:
Ti＝tdi+tsi＝(T-10-ts1)*(i-1)/(n-1)(1＜i＜n，n＜＝3)
T-10 represents that all power supplys have all gone up electricity in t-10ms; (T-10-ts1)/(n-1) be per two interval times that adjacent direct supply is finished to power in n the direct supply; (T-10-ts1) * (i-1)/(n-1) is the time interval of finishing to power between i power supply and first power supply P1; Tdi is that P1 is to the delay time of the delay circuit of Pi, tsi is the opening time of i power module, after namely the Vin of i power module reaches the input voltage claimed range, drawn high the needed required time of P1 magnitude of voltage that enables stable output from the RC pin; The power-on time of i power supply is denoted as Tio=Ti+ts1; The power-on time Tno of last direct supply Pn need satisfy the ms of Tno=Tn+ts1＜(T-10).
The provided by the invention the 3rd more preferably in the technical scheme, in described step 5:
Obtain following relation: Vo/K2i+Ci*dVo/dt=(P1-Vo)/Ki1 by the KCL philosophy,
Finding the solution the differential equation obtains: t=tdi=(K2i//K1i) * Ci*In[V ∞/(V ∞-Vo)] (1)
V∞＝P1*K2i/(K1i+K2i) (2)
Make Vo=VBEsat (3)
Make t=tdi=(T-10) * (i-1)/(n-1)-tsi-ts1 (4)
Wherein, (K2i//K1i) parallel connection of expression R492 and R491, P1 is first direct supply magnitude of voltage that powers on; VBEsat is Q79 saturation conduction voltage; T is the time of upper complete all electricity of chip requirement; I finishes and powers on for i in order; N is the number that chip has the power supply of electrifying timing sequence requirement; Ts1 is after the 1st power module Vin reaches the input voltage claimed range, is drawn high the needed required time of P1 magnitude of voltage that enables stable output from the RC pin.
The provided by the invention the 4th more preferably in the technical scheme, in described step a, alarm temperature T1 is set, outage temperature T 2, and the concrete steps of overheating protection are as follows:
(a-1). the chip of normal operation (1) overheat sensor reads the temperature of oneself, and when working temperature surpassed alarm temperature T1, described chip (1) sent alarm signal;
(a-2). when the temperature of chip (1) surpassed outage temperature T 2, chip (1) sent power-off signal by overheating protection circuit to direct supply 1 (P1);
(a-3). direct supply (P1) outage, also can cut off the power supply respectively by the direct supply (P2, P3) of its control, chip (1) is also cut off the power supply, chip (1) quits work.
The provided by the invention the 5th more preferably in the technical scheme, and in described step b, the concrete steps of recovering the chip normal operation are as follows:
(b-1). after heat detecting sensor recovered normally to the temperature of chip (1), (P1) sent enable signal to direct supply, recovers the power supply to chip;
(b-2). the GPIO port that utilizes the driver of the PCIE card on the mainboard to remove to control PCIE Switch chip sends restoring signal and removes reset chip (1), the hot reset function of removing to finish PCIE Switch chip by the PCIE card on the mainboard simultaneously makes between chip (1) and chip (2) to be recovered to communicate by letter, and recycling software is again to PCIE card Resources allocation.
Compared with the prior art, electrifying timing sequence control system and the method for a kind of PCIE integrated circuit board provided by the invention, with low cost, PCB layout is easy, can allow integrated circuit board finish in short period T (such as 50ms) powers on, each power supply that the assurance subcard needs is finished in a certain order and is powered on, subcard is supported slot and external power supply dual power supply adaptive mode, when subcard is inserted on the mainboard, when not having external power supply, subcard is powered by golden finger, automatically switches to external power supply when subcard is plugged circumscripted power line; And support the hot reset function, and when the unpredictable fault that occurs burst behind the subcard long-play or program fleet, can carry out hot reset by the antithetical phrase card, allow subcard reenter normal condition; Support overheat protective function, when the subcard excess Temperature, can do overheating protection, such as coming off appears in heat radiator, the fan failure stall causes the subcard excess Temperature in the abominable situation of environment, if do not do the heat protection, then chip is burnt easily, and can play defencive function after having added overheating protection circuit, if temperature surpasses the safe range of chip, then holding circuit can be cut off the electricity supply and be protected; Moreover after overheating protection, after the subcard temperature dropped to safe range, subcard automatically recovered normal operation and need not to restart mainboard; Use automatic switch-over circuit, when the PCIE of mainboard slot power is not enough, plug circumscripted power line then that feed circuit automatically switch to the power supply by external power supply connector place, good product consistency, easy and simple to handle, technical support is easy, uses facility.
Description of drawings
Fig. 1 is the power-on time sequence control circuit block diagram of PCIE integrated circuit board.
Fig. 2 is external 12V_OUT detection circuit structure synoptic diagram.
Fig. 3 is the structural representation of adaptive circuit.
Fig. 4 is the principle design figure of delay circuit.
Fig. 5 is the principle design figure of overheating protection circuit.
Fig. 6 is the structural representation of restoring circuit.
Fig. 7 is the circuit theory diagrams after temperature is recovered normally automatically to power on after the overheating protection.
The sequential chart that Fig. 8 powers on for time-delay.
Embodiment
The present invention utilizes same control power supply P1 to remove to control P2, P3, Pn, the time that P1 is stable is made as t1=P1, the stable time of P2 power supply is t2=P1+P2+t12, the stable time of the power supply of P3 is t3=P1+P3+t13, the stable time of the power supply of Pn is tn=P1+Pn+t1n, P1 wherein, P2, the time-to-climb that Pn representing the power supply of each power module, t1n is that the P1 power supply is when stablizing and the interval time of the enable of Pn power supply between opening, if assurance t1＜t2＜t3＜...＜tn and tn=P1+Pn+t1n＜T becomes to meet design requirement immediately, in fact P1+Pn+t1n is exactly the power supply that last powers on, total power-on time is tn=P1+Pn+t1n namely, the P1+P2+P3+ that obtains much smaller than the control method of the method for designing recursion of a lot of integrated circuit boards ... + P (n-1)+Pn time, the method of recursion that most of integrated circuit boards are taked control be each power module the time-to-climb added up at next stage, the present invention goes control with P1, quite and P2, P3, the Pn power supply needn't be waited for that another power supply climbs fully and begin to climb behind the ok again, but climb together or wait for that previous power supply climbs for a moment but namely begin to climb behind the ok that also needless to say climbs fully, as long as guarantee P1, P2, P3, Pn has climbed successively and has got final product, utilize P1 to remove to control the enable (RC or inhibit) of Pi (i is the module of i power supply), the time-to-climb speed of the delay time tdi compensation different electrical power intermodule between P1 and enable guarantees P1, P2, P3, Pn powers on successively, set first the time tn=t1+tdi+tn that the slowest power supply Pn climbs stable, retrodict out successively the more stable time of climbing of front several power supplys, thereby set delay time between the enable of P1 and Pi.The present invention adopts simple RC capacitance-resistance to do delay control circuit in addition, and cost is lower, and use FPGA/CPLD also can be as the method for control delay, but cost is relatively high, and occupy larger PCB area, with low cost because the present invention has, PCB layout is easy to advantage.
Realize that at first 12V switches adaptive circuit, concrete steps are as follows:
The first step: design external 12V_OUT circuit for detecting: design an external 12V circuit for detecting, whether be used for detecting external 12V_OUT accesses, be called 12V_out_Sensor_L, 12V_out_Sensor_L was not a high level state when external 12V accessed, when external 12V access, it is a low level state, can accomplish with the switching characteristic of a triode variation of state, parameter selection method is as follows:
12V_OUT*R849/(R849+R819)＝V∞-----------------------------------(1)
(datasheet that VBesat looks into Q9017 gets final product)
Get according to the KCL law:
VBE/R849+C744*dVBE/dt＝(12V_OUT-VBE)/R819
The solution differential equation gets: dt=C744* (R849//R819) In[V ∞/(V ∞-VBE)]-------(2)
The effect of C744 is to do time-lag action, guarantees that 12V_OUT is stable
---------------(3) that make VBE=VBEsat----------------------------------------------
VBesat is the saturation conduction voltage of Q9017, checks that the datasheet of Q9017 device gets final product.
---------------(4) that make dt=10ms-------------------------------------------------
In conjunction with actual common resistance, it is suitable that capacitance can be selected according to above-mentioned (1) (2) (3) (4)
C744, R819, the value of R849.The specific implementation circuit as shown in Figure 2.
As shown in Figure 3, adaptive circuit: when utilizing different these 12V_out_Sensor_L for low level 12V_out (12V_ is external) is linked into main circuit as the 12V power supply, when 12V_out_Sensor_L is high level, 12V_PCIE is linked into main circuit as the 12V power supply, the specific implementation circuit is as follows: the implementation method of chose namely goes up the circuit of Fig. 2, when chose is 0, be that 12V_out_Sensor_L is when being low level (detecting 12V_OUT inserts), then allowing electronic switch switch to 12V_ external (12V_OUT) supplies to conduct to subcard power supply 12V with 12V, when chose is 1, be 12V_out_Sensor_L when being high level (not detecting 12V_OUT inserts), then allow electronic switch switch to 12V_PCIE and 12V for conducting to the subcard 12V that powers.
12V is received on each Power Module.
The circuit of that power supply P1 of powering at first of design: will require the enable pin of the used power circuit of that power supply of powering at first (generally to be called RUN, RC, the titles such as Inhibit) directly draw high (the unsettled high level that is of the enable pin of most power modules), first power supply is denoted as P1.(the subsequent design overheating protection also needs the enable pin of P1 is received the alert pin of overheating protection IC, sees below continuous step, wouldn't design this function, follow-up again design)
Powering on the successively time interval of every adjacent two power supplys of calculating and setting: suppose that chip requires to have gone up in the T ms time electricity, we leave certain safe range, gone up electricity in (T-10) the ms time of selection, P1, P2, ... P (n-1), every adjacent two power supply electrifyings of P (n) are interval (T-10-ts1) ms/ (n-1) successively.
The power circuit of calculating Pn is followed the delay time tdn between P1:
Finish all requirements that powers on according to (T-10) ms that selects, tdn=delay between P1 and Pn (n-1)=(T-10)-ts1-tsn, adopt RC to do the delay circuit, select the needs of P1 and Pn power module to satisfy the ms of the ms of following requirement: ts1+tdn+tsn＜=(T-10) and ts1+tsn＜(T-10).
Annotate: after the 1st power module Vin reaches the input voltage claimed range, being drawn high the required time of needed P1 magnitude of voltage that enables stable output from the RC pin is ts1 ms, after last power module Vin reaches the input voltage claimed range, being drawn high the required time of needed Pn magnitude of voltage that enables stable output from the RC pin is tsn ms, then the delay between P1 and Pn (n) is T-10-ts1-tsn ms to the maximum, ts gets final product referring to the datasheet of power Module, if the power module of designed, designed, then can measure first the power-on time ts of power, what PCIE card majority used is module (being subject to the PCB layout space).
Calculate other each power supplys Pi (Pi is i power supply) reaches requirement stationary value (namely finish and power on) with the P1 power supply time interval Ti:(T-10-ts1) * (i-1)/(n-1),
Ti is denoted as in i power supply and the 1st time interval that power supply is finished to power on, then:
Ti=tdi+tsi+ts1=(T-10-ts1) * (i-1)/(n-1) (1＜i＜n) wherein
Annotate: (1) is that all power supplys have all been gone up electricity in t-10ms (T-10)
(2) (T-10-ts1) ms/ (n-1) is n power supply per two interval times that adjacent power supply is finished to power on
(3) (T-10-ts1) * (i-1)/(n-1) is time interval of finishing to power between i power supply and first power supply P1.
(4) tdi be P1 to the delay circuit delay of Pi, delay1,
Delay2 ... delayn, this value does not comprise the ts rise time of power module.
The power-on time of (a 5) i power supply is denoted as Tio=Ti+ts1
(6) power-on time of last power supply need satisfy the ms of Tno=Tn+ts1＜(T-10).
Delay circuit: tdi=(T-10-ts1) * (i-1)/(n-1)-tsi, constraint condition is tdi＞0.
At first select a triode, be used for doing switch control, the forward voltage of supposing triode is Vo, then selects the P1 delay time between each power supply of following to control following Fig. 4 by RC and triode,
Obtain following relation: Vo/K2i+Ci*dVo/dt=(P1-Vo)/Ki1 by the KCL philosophy,
Finding the solution the differential equation obtains: t=tdi=(K2i//K1i) * Ci*In[V ∞/(V ∞-Vo)]-----1.
(K2i//K1i) parallel connection of expression K2i and K1i, P1 is first supply voltage value that powers on.
V∞＝P1*K2i/(K1i+K2i)---------------------------------------------------②
Make Vo=VBEsat--------------------------------------------------------------3.
VBEsat is BJT (the saturation conduction voltage of Q79), and the datasheet that looks into device gets final product.
Make that t=tdi=(T-10-ts1) * (i-1)/(n-1)-tsi--------------------------------------4.
Parameter declaration: (1) T is the time of upper complete all electricity of chip requirement
(2) i finishes and powers on for i in order
(3) n is the number that chip has the power supply of electrifying timing sequence requirement
(4) ts1 is the opening time of the 1st the selected power module of power supply that powers on, namely from
Power module is opened the beginning out-put supply by enable and is stabilized to time of the voltage pi value that required arrival is set to Pi, gets final product referring to the ts of the datasheet of power module.
(5). after the Vin of power module 1 reaches the input voltage claimed range, drawn high the needed required time of P1 magnitude of voltage that enables stable output from the RC pin.
Fig. 8 is electrifying timing sequence figure.
Above comprehensive 1. 2. 3. 4. three equations can obtain Ci, K1i, the value of K2i
Fine setting Ci, K1i, the value of K2i: because actual capacitance-resistance value is not continuous, but discrete value, according to the C that finds the solution out, the K value goes for close capacitance, resistance substitution t=tdi=(K2i//K1i) * Ci*In[V ∞/(V ∞-Vo)]----1. try to achieve P1 to the delay opening time of Pi power supply, last only need satisfy simultaneously following 5. 6. relation get final product:
Tdi+ts1+tsi＜td (i+1)+ts1+ts (i+1)---go up first than i+1 electricity by-------5. i.e. i electricity
6. ts1+td (n)+ts (n)＜(T-10) ms--------------------------namely establishes the time that begin to climb n (last electricity) climbed by cable from first and get final product ((T-10) ms is the surplus capacity of having reserved 10ms) in chip requires the time T scope, Pi (following Fig. 4 of schematic diagram design method of delay circuit of 1＜i＜=n), the RC pin of power module is that enable enables pin, some power module is Inhibit pin, and function is identical.
Overheating protection circuit:
When chip temperature arrives the safe range warning line; need alarm; if temperature continues soaring; the circuit of then directly cutting off the electricity supply; method is to use a temperature of removing to detect chip with the thermal sensor of IIC interface; chip is read the temperature of oneself from thermal sensor by the IIC interface; when reaching warning temperature T 1 (such as 100 ℃), the temperature of reading then on screen, gets Warning information by software code realization; when reading temperature and continue to be elevated to T2 (such as 110 ℃); directly the alert pin (T_CRIT_A_L) with Thermal sensor drags down; this signal is given the enable (inhibit) of P1; following Fig. 5; P1 one power down; then the enable pin of all power supply Pi (RC pin) is all dragged down by control among Fig. 4; thereby so that overheated power-off protection function is accomplished in all non-transformer output of Pi power module.Realize schematic diagram See Figure 5.
Restoring circuit: subcard recovered the circuit that works automatically after the overheating protection temperature reduced:
The temperature that thermal sensor among Fig. 5 detects master chip is recovered alertpin (T_CRIT_A_L) to be drawn high again after normal, this signal is given the enable (inhibit) of P1, so that the P1 power module begins normal output voltage P1, then the Pi of Fig. 4 begins output voltage to master chip, master chip power supply this moment ok all, need to finish to Reset# signal of master chip and reset, subcard then can restart to work together, and this Reset# signal is realized by the reset time control circuit among lower Fig. 7.Because master chip outage after the protection of subcard heat; the PCIE link link of master chip and mainboard disconnects; (namely removing PCIE equipment can identify automatically with insertion PCIE equipment mainboard if mainboard does not possess hot plug PCIE functions of the equipments; then subcard can't obtain corresponding software and hardware resources and can't work; therefore need to add a PCIE Switch as a bridge joint, guarantee that subcard and mainboard have the PCIE link of physics all the time.Subcard overheating protection temperature recover normal after the subcard following Fig. 6 of circuit block diagram that automatically recovers to work.
The hot reset functional circuit when integrated circuit board moves the unpredictable fault of rear appearance burst or program fleet for a long time, can be done hot reset to integrated circuit board, allows integrated circuit board reenter normal condition.
Implementation method is: the GPIO of PCIE_switch is connected to Board_PERST_L among Fig. 7; when program fleet after; subcard driver that can be by the mainboard end drags down first the GPIO of PCIE_switch; then postpone to draw high behind the certain hour; through behind the U34 master chip is resetted again; namely realize hot reset; with the reset time control circuit connect together realize and relation; instant heating reset function, subcard overheating protection temperature recover normal after the subcard function of automatically recovering to work can all support simultaneously.
A kind of power-on time sequence control method of PCIE integrated circuit board, described method comprises the steps:
(1). by direct supply (P1) chip (1) is powered on;
(2). the opening time tsi (1＜=i＜=n, n＜=3) of test direct supply Pi;
(3). calculate to the direct supply (P2, P3) of chip (1) power supply and finish the time interval Ti (1＜i＜=n, n＜=3) that powers on direct supply (P1) power supply respectively;
(4). calculate the delay time td3 of the delay circuit between direct supply (P3) and direct supply (P1);
(5). the parameter of computation delay circuit 2;
(6). calculate the delay time td2 of the delay circuit between direct supply (P2) and direct supply (P1);
(7). the parameter of computation delay circuit 1;
(8). according to the opening time tsi of the time interval Ti that obtains and direct supply, to calculating (1＜i＜=n, n＜=3) time delay of the delay circuit of direct supply Pi;
(9). according to result of calculation, operation powers on to direct supply Pi (1＜i＜=n, n＜=3).After described step 9, described method comprises the steps:
(a). whether the temperature of surveying the chip (1) that powers on is too high, if then with chip (1) outage, and carries out overheating protection;
(b). survey whether returned to normal working temperature by the temperature of the chip of overheating protection, if then to chip power, recover the normal operation of chip.
In described step 3, the computing formula of Ti is as follows:
Ti＝(T-10-ts1)*(i-1)/(n-1)
Wherein, Ti is denoted as in i power supply and the 1st time interval that power supply is finished to power on, then:
Ti＝tdi+tsi＝(T-10-ts1)*(i-1)/(n-1)(1＜i＜n，n＜＝3)
T-10 represents that all power supplys have all gone up electricity in t-10ms; T-10ms guarantees to finish in Tms and powers in order to leave certain surplus capacity, and Tms gets final product in theory, (T-10-ts1)/(n-1) is per two interval times that adjacent direct supply is finished to power in n the direct supply; (T-10-ts1) * (i-1)/(n-1) is the time interval of finishing to power between i power supply and first power supply P1; Tdi be P1 to the delay time of Pi, tsi is the opening time (ts) of the direct supply that powers on of i; The power-on time of i power supply is denoted as Tio=Ti+ts1; The power-on time Tno of last direct supply Pn need satisfy the ms of Tno=Tn+ts1＜(T-10).
In described step 8:
Obtain following relation: Vo/K2i+Ci*dVo/dt=(P1-Vo)/Ki1 by the KCL philosophy,
Finding the solution the differential equation obtains: t=tdi=(K2i//K1i) * Ci*In[V ∞/(V ∞-Vo)] (1)
V∞＝P1*K2i/(K1i+K2i) (2)
Make Vo=VBEsat (3)
Make t=tdi=(T-10-ts1) * (i-1)/(n-1)-tsi (4)
Wherein, (K2i//K1i) parallel connection of expression R492 and R491, P1 is first direct supply magnitude of voltage that powers on; VBEsat is Q79 saturation conduction voltage; T is the time of upper complete all electricity of chip requirement; I finishes and powers on for i in order; N is the number that chip has the power supply of electrifying timing sequence requirement; Ts1 be the 1st direct supply that powers on from be opened to output satisfactory stationary value time.
In described step a, alarm temperature T1 is set, outage temperature T 2, the concrete steps of overheating protection are as follows:
(a-1). the chip of normal operation (1) overheat sensor reads the temperature of oneself, and when working temperature surpassed alarm temperature T1, described chip (1) sent alarm signal;
(a-2). when the temperature of chip (1) surpassed outage temperature T 2, chip (1) sent power-off signal by overheating protection circuit to direct supply 1 (P1);
(a-3). direct supply (P1) outage, also can cut off the power supply respectively by the direct supply (P2, P3) of its control, chip (1) is also cut off the power supply, chip (1) quits work.
In described step b, the concrete steps of recovering the chip normal operation are as follows:
(b-1). after thermal sensor recovered normally to the temperature that detects chip (1), (P1) sent enable signal to direct supply, recovers the power supply to chip;
(b-2). the GPIO port that utilizes the driver software of the PCIE card on the mainboard to remove to control PCIE Switch chip sends restoring signal and removes reset chip (1), the hot reset function of removing to finish PCIE Switch chip by the driver software of the PCIE card on the mainboard simultaneously makes between chip (1) and chip (2) to be recovered to communicate by letter, reset circuit after perhaps utilizing the Pn power supply through time-delay removes reset chip (1), then the PCIE passage between chip (1) and chip (2) will oneself rebulid path, and recycling software is again to can normally using after the PCIE card Resources allocation.
The power-on time sequence control method of described PCIE integrated circuit board also can be to n direct supply (P1...Pi...Pn); Wherein, P1 represents the direct supply that first powers on, and Pn represents the direct supply that last powers on.
The power-on time sequence control method of the PCIE integrated circuit board of described electrifying timing sequence control system, described method comprises the steps:
(1). by direct supply (P1) chip (1) is powered on;
(2). calculate to each direct supply (Pi) of chip (1) power supply and finish respectively the time interval Ti that powers on direct supply (P1);
(3). calculate last power supply of giving chip (1) power supply and finish the direct supply (Pn) that powers on tdn time delay between direct supply (P1);
(4). according to the time interval that obtains (Ti) and Tsi, Tsi represents the opening time of i direct supply, and according to the Ti that obtains and Pi, P1 is the tsi of direct supply separately, ts1; To calculating the time delay except the delay circuit of each direct supply (Pi...Pn) of P1;
(5). according to result of calculation, to the operation that powers on except each direct supply (Pi...Pn) of P1.
What need statement is that content of the present invention and embodiment are intended to prove the practical application of technical scheme provided by the present invention, should not be construed as the restriction to protection domain of the present invention.Those skilled in the art can do various modifications, be equal to and replace or improve inspired by the spirit and principles of the present invention.But these changes or modification are all in the protection domain that application is awaited the reply.
Claims (16)
1. the electrifying timing sequence control system of a PCIE integrated circuit board, it comprises: direct supply (P1, P4) and chip (1,2); It is characterized in that described electrifying timing sequence control system comprises: electric unit, overheating protection unit and restoring circuit in adaptive circuit, the time-delay; Described adaptive circuit one end accesses respectively 12V external power supply and 12V PCIE power supply, the other end respectively with described direct supply (P1) be connected direct supply (P4) and be connected; Described chip (1) respectively with described direct supply (P1), described time-delay on electric unit, described restoring circuit, described chip (2) be connected the overheating protection unit and be connected; Described chip (2) respectively be connected direct supply (P4) be connected restoring circuit and connect.
2. electrifying timing sequence control system according to claim 1 is characterized in that, described adaptive circuit comprises: the bleeder circuit, triode and the electronic switch that connect successively; Described bleeder circuit is connected with the 12V external power supply; Described electronic switch accesses 12V external power supply and 12V PCIE power supply, and is connected with the Vin input of described direct supply (P1).
3. electrifying timing sequence control system according to claim 1 is characterized in that, electric unit comprises in the described time-delay: delay circuit (1,2), electronic switch (2,3) and direct supply (P2, P3); Described delay circuit (1), electronic switch (2) are connected P2 with direct supply) connect successively; Described delay circuit (2), electronic switch (3) are connected P3 with direct supply) connect successively; Described delay circuit (1) be connected delay circuit (2) and be connected with described direct supply (P1) respectively; Described direct supply (P2) and described direct supply (P3) receive respectively the 12V voltage of described adaptive circuit transmission, and described direct supply (P2) is connected with described chip (1).
4. electrifying timing sequence control system according to claim 3, it is characterized in that described delay circuit comprises: resistance (R490, R491, R492, R683, R881, R882, R883), electric capacity (C812, C814), triode (Q79, Q81) and power module; Described power module arranges link (1,2,3,4,5,6,7,8); R491 one termination is received data-signal, and the other end and C812 are connected the base stage of parallel-connection structure and Q79 and are connected the other end of the parallel-connection structure of C812 and R492 and the grounded emitter of Q79 with R492; The collector of Q79 is connected with the 3.3V direct supply by R490, and is connected with the base stage of Q81 by R882; The grounded emitter of Q81, collector are connected with the end of R883; The other end of R883 is connected an end with the end of C814 respectively and is connected with R683; The end that C814 is connected with R883 also is connected with the end (3) of described power module; In described power module, end (1) is the power supply input pin, end (4) is unsettled pin, and end (5) connects regulating resistor R881, R881 other end ground connection, end (6) reaches indicator signal after the desired stationary value for out-put supply, can be unsettled, end (2,7) ground connection, end (8) is the power module output pin, and end (3) is that power module enables control end.
5. electrifying timing sequence control system according to claim 1 is characterized in that, described overheating protection unit comprises: thermal sensor, overheating protection circuit and thermal sensor control chip; Described thermal sensor respectively be connected chip (1), described overheating protection circuit and the thermal sensor control chip of being connected and connect; Described thermal sensor control chip is controlled described thermal sensor by control bus.
6. electrifying timing sequence control system according to claim 5 is characterized in that, it is the chip of TLR36480 that described thermal sensor control chip adopts model; Described control bus is iic bus.
7. electrifying timing sequence control system according to claim 5 is characterized in that, described overheating protection circuit comprises that model is the power module of PMR5118 and the chip of connected model LM95235QEIMM/NOPb; The chip of described model PMR5118 is connected with described thermal sensor.
8. electrifying timing sequence control system according to claim 1 is characterized in that, described restoring circuit comprise PCIE Switch chip, PCIE connector and with door; Described PCIE Switch chip by the PCIE passage respectively be connected chip (1) and the PCIE connector connection of being connected; Describedly receive respectively the Reset_L signal that described PCIE Switch chip and described PCIE connector send with door, and according to the signal that receives to described chip (1) control that resets.
9. electrifying timing sequence control system according to claim 8 is characterized in that, described PCIE Switch chip is provided with the GPIO port that sends restoring signal to described chip (1); Described PCIE switch chip has the hot reset function.
10. electrifying timing sequence control system according to claim 1 is characterized in that, described chip (1) and described chip (2) are the chip with the PCIE interface.
11. the power-on time sequence control method according to the PCIE integrated circuit board of each described electrifying timing sequence control system of 1-10 item claim is characterized in that described method comprises the steps:
(1). by direct supply (P1) chip (1) is powered on;
(2). the opening time tsi (1＜=i＜=n, n＜=3) of test direct supply Pi;
(3). calculate to the direct supply (P2, P3) of chip (1) power supply and finish the time interval Ti (1＜i＜=n, n＜=3) that powers on direct supply (P1) power supply respectively;
(4). calculate the delay time td3 of the delay circuit between direct supply (P3) and direct supply (P1);
(5). the parameter of computation delay circuit 2;
(6). calculate the delay time td2 of the delay circuit between direct supply (P2) and direct supply (P1);
(7). the parameter of computation delay circuit 1;
(8). according to the opening time tsi of the time interval Ti that obtains and direct supply, to calculating (1＜i＜=n, n＜=3) time delay of the delay circuit of direct supply Pi;
(9). according to result of calculation, operation powers on to direct supply Pi (1＜i＜=n, n＜=3).
12. power-on time sequence control method according to claim 11 is characterized in that, after described step 9, described method comprises the steps:
(a). whether the temperature of surveying the chip (1) that powers on is too high, if then with chip (1) outage, and carries out overheating protection;
(b). survey whether returned to normal working temperature by the temperature of the chip of overheating protection, if then to chip power, recover the normal operation of chip.
13. power-on time sequence control method according to claim 11 is characterized in that, in described step 3, the computing formula of Ti is as follows:
Ti＝(T-10-ts1)*(i-1)/(n-1)
Wherein, Ti is denoted as in i power supply and the 1st time interval that power supply is finished to power on, then:
Ti＝tdi+tsi＝(T-10-ts1)*(i-1)/(n-1)(1＜i＜＝n，n＜＝3)
T-10 represents that all power supplys have all gone up electricity in t-10ms; (T-10-ts1)/(n-1) be per two interval times that adjacent direct supply is finished to power in n the direct supply; (T-10-ts1) * (i-1)/(n-1) is the time interval of finishing to power between i power supply and first power supply P1; Tdi is that P1 is to the delay time of the delay circuit of Pi, tsi is the opening time of i power module, after namely the Vin of i power module reaches the input voltage claimed range, drawn high the needed required time of P1 magnitude of voltage that enables stable output from the RC pin, to explain tsi with the opening time of i power module among the present invention, implication is namely described herein; The power-on time of i power supply is denoted as Tio=Ti+ts1; The power-on time Tno of last direct supply Pn need satisfy the ms of Tno=Tn+ts1＜(T-10).
14. according to claim 11,13 described power-on time sequence control methods, it is characterized in that, in described step 8:
Obtain following relation: Vo/K2i+Ci*dVo/dt=(P1-Vo)/Ki1 by the KCL philosophy,
Finding the solution the differential equation obtains: t=tdi=(K2i//K1i) * Ci*In[V ∞/(V ∞-Vo)] (1)
V∞＝P1*K2i/(K1i+K2i) (2)
Make Vo=VBEsat (3)
Make t=tdi=(T-10) * (i-1)/(n-1)-tsi-ts1 (4)
Wherein, (K2i//K1i) parallel connection of expression R492 and R491, P1 is first direct supply magnitude of voltage that powers on; VBEsat is Q79 saturation conduction voltage; T is the time of upper complete all electricity of chip requirement; I finishes and powers on for i in order; N is the number that chip has the power supply of electrifying timing sequence requirement; Ts1 is after the 1st power module Vin reaches the input voltage claimed range, is drawn high the needed required time of P1 magnitude of voltage that enables stable output from the RC pin.
15. power-on time sequence control method according to claim 12 is characterized in that, in described step a, alarm temperature T1 is set, outage temperature T 2, and the concrete steps of overheating protection are as follows:
(a-1). the chip of normal operation (1) overheat sensor reads the temperature of oneself, and when working temperature surpassed alarm temperature T1, described chip (1) sent alarm signal;
(a-2). when the temperature of chip (1) surpassed outage temperature T 2, chip (1) sent power-off signal by overheating protection circuit to direct supply 1 (P1);
(a-3). direct supply (P1) outage, also can cut off the power supply respectively by the direct supply (P2, P3) of its control, chip (1) is also cut off the power supply, chip (1) quits work.
16. power-on time sequence control method according to claim 12 is characterized in that, in described step b, the concrete steps of recovering the chip normal operation are as follows:
(b-1). after heat detecting sensor recovered normally to the temperature of chip (1), (P1) sent enable signal to direct supply, recovers the power supply to chip;
(b-2). the GPIO port that utilizes the driver of the PCIE card on the mainboard to remove to control PCIE Switch chip sends restoring signal and removes reset chip (1), the hot reset function of removing to finish PCIE Switch chip by the PCIE card on the mainboard simultaneously makes between chip (1) and chip (2) to be recovered to communicate by letter, and recycling software is again to PCIE card Resources allocation.
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