CN102750189B - Overheating protection and restoring circuit of peripheral component interface express (PCIE) board card - Google Patents

Abstract

The invention provides an overheating protection and restoring circuit of a peripheral component interface express (PCIE) board card. The overheating protection and restoring circuit comprises a delay power-on unit, an overheating protection unit and a restoring circuit. The overheating protection and restoring circuit of the PCIE board card enables the board card to achieve power on in a short time T, ensures power sources required by a sub-card to achieve power on according to a certain sequence, adopts a sub-card supporting slot and external power double-power-supply self-adaptive mode, supports a heat restoring function, and enables the sub-card to automatically resume normal work without starting a mainboard again when the temperature of the sub-card is reduced to a safe range after the overheating protection.

Description

A kind of overtemperature protection of PCIE boards and restoring circuit

Technical field

The invention belongs to computer realm, and in particular to a kind of overtemperature protection of PCIE boards and restoring circuit.

Background technology

Existing some PCIE subcards cause the feelings that subcard can not normally recognize by mainboard due to electrifying timing sequence design problem Condition happens occasionally, but reboot mainboards just can be recognized, and reason is that on subcard that electricity is excessively slow, resets abnormal, at present The reason for electricity is slow on many subcards also resides in following reason：As subcard functional requirement becomes increasingly complex, subcard design is gradually multiple Hydridization, the power type on subcard is also on the increase, and has electric sequence requirement between each power supply on subcard, greatly The common electric sequence control way of majority is after P1ok, to allow P1 to go control P2 to start power up, and P2 control P3 remove electricity, with this Analogize Pn to be controlled by P (n-1), like this, the final power-on time of Pn modules is the electricity of P1+P2+P3+...+P (n-1)+Pn Source time-to-climb, then add the delay control times of P1 to P2, the delay of P2 to P3 is past until the control time of P (n-1) to Pn Toward due to P1, P2, P3...Pn power module total time-to-climb is oversize to cause on subcard that electricity is excessively slow, and final mainboard issues subcard Reset_L drawn high failure, and subcard power supply is not yet stable, so as to complete normal reset_L, causes function not Normal problem.

At present many PCIE subcards typically all do not do overtemperature protection, and this overtemperature protection energy effective protection board is not damaged by (when the Chip temperature on board in the case of fan failure or bad environments increases to over the scope that Chip can stand just Can damage), even if in addition some subcards have done overtemperature protection, but due to the overheated power-off protection of subcard after, Chip and mainboard PCIE links are disconnected, and subcard will work on, it is necessary to reboot mainboards, like this, if there is other answering on mainboard With need continue running if, it is clear that reboot mainboards are less suitable.

The content of the invention

To overcome drawbacks described above, the invention provides a kind of overtemperature protection of PCIE boards and restoring circuit, allow board to exist Upper electricity is completed in short period T (such as 50ms), it is ensured that each power supply that subcard needs completes in a certain order electricity, adopt Subcard supports slot and external power supply dual power supply adaptive mode, supports hot reset function, and after overtemperature protection, subcard Temperature is dropped to after safety range, and subcard recovers normal work and need not restart mainboard automatically.

For achieving the above object, the present invention provides a kind of overtemperature protection and the restoring circuit of PCIE boards, and it includes：Direct current Power supply (P1, P4) and chip (1,2)；It thes improvement is that the overtemperature protection and restoring circuit include：Electricity is single in time delay Unit, overtemperature protection unit and restoring circuit；The DC source (P1) and the DC source (P4) are respectively connected to the external electricity of 12V Source and 12V PCIE power supplys；The chip (1) respectively with electric unit, the recovery in the DC source (P1), the time delay The connection of circuit, the chip (2) and the overtemperature protection unit；The chip (2) respectively with the DC source (P4) and institute State restoring circuit connection.

In the optimal technical scheme that the present invention is provided, electric unit includes in the time delay：Delay circuit (1,2), electronic cutting Close (2,3) with DC source (P2, P3)；The delay circuit (1), electrical switch (2) and DC source (P2) are sequentially connected；Institute State delay circuit (2), electrical switch (3) and DC source (P3) to be sequentially connected；The delay circuit (1) and the delay circuit (2) it is connected with the DC source (P1) respectively；It is electric that the DC source (P2) and the DC source (P3) receive respectively 12V Pressure, the DC source (P2) is connected with the chip (1).

In the second optimal technical scheme that the present invention is provided, the delay circuit includes：Resistance (R490, R491, R492, R683, R881, R882, R883), electric capacity (C812, C814), audion (Q79, Q81) and power module；The power module sets Put connection end (1,2,3,4,5,6,7,8)；The parallel-connection structure of R491 one end receiving data signal, the other end and C812 and R492, And the base stage connection of Q79, the other end of the parallel-connection structure of C812 and R492 and the grounded emitter of Q79；The colelctor electrode of Q79 leads to The connection of R490 and 3.3V DC sources is crossed, and is connected with the base stage of Q81 by R882；The grounded emitter of Q81, colelctor electrode with One end connection of R883；The other end of R883 is connected respectively with one end of C814 and one end of R683；C814 is connected with R883 One end is also connected with the end (3) of the power module；In the power module, end (1) is power input pin, and end (4) is Hanging pin, end (5) connection regulating resistor R881, R881 other ends ground connection is held (6) for out-put supply and reaches required stablizing Indication signal after value, can be hanging, and end (2,7) it is grounded, end (8) is power module output pin, and end (3) is that power module makes Can control end.

In the 3rd optimal technical scheme that the present invention is provided, the overtemperature protection unit includes：Heat sensor, overtemperature protection Circuit and heat sensor control chip；The heat sensor respectively with the chip (1), the overheating protection circuit and the heat Sensor control chip connects；The heat sensor control chip is controlled by controlling bus to the heat sensor.

In the 4th optimal technical scheme that the present invention is provided, the heat sensor control chip adopts model TLR36480 Chip；The controlling bus are iic bus.

In the 5th optimal technical scheme that the present invention is provided, the overheating protection circuit includes the electricity of model PMR5118 The chip of source module and connected model LM95235QEIMM/NOPb；The chip of model U3625 and the heat sensing Device connects.

In the 6th optimal technical scheme that the present invention is provided, the restoring circuit includes that PCIE Switch chips, PCIE connect Connect device and with door；The PCIE Switch chips are connected respectively by PCIE channel with the chip (1) and the PCIE adapters Connect；It is described to receive the Reset_L signals that the PCIE Switch chips and the PCIE adapters send, and root respectively with door Reset control is carried out to the chip (1) according to the signal for receiving.

In the 7th optimal technical scheme that the present invention is provided, the PCIE Switch chips arrange the oriented chip (1) Send the GPIO port for recovering signal；The PCIE switch chips have hot reset function.

In the 8th optimal technical scheme that the present invention is provided, the chip (1) and the chip (2) are with PCIE interfaces Chip.

Compared with the prior art, a kind of overtemperature protection of PCIE boards that the present invention is provided and restoring circuit, with low cost, PCB layout easily, can allow board to complete upper electricity in short period T (such as 50ms), it is ensured that each power supply that subcard needs according to Certain order completes electricity, and subcard supports slot and external power supply dual power supply adaptive mode, when subcard is inserted in mainboard On, without during external power supply, subcard is powered by golden finger, and external power supply is automatically switched to when subcard plugs circumscripted power line； And hot reset function is supported, when the unpredictable failure or program fleet that occur happening suddenly after subcard long-play, Hot reset can be carried out with antithetical phrase card, allow subcard to reenter normal condition；Overheat protective function is supported, when subcard temperature is too high Overtemperature protection can be done, such as coming off occurs in fin, fan failure stalling, and subcard temperature mistake is caused in the case of bad environments Height, if not doing Thermal protection, chip is easily burned out, and has added and can play after overheating protection circuit defencive function, if warm Degree exceedes the safety range of chip, then protection circuit can cut off the electricity supply and be protected；Furthermore, after overtemperature protection, subcard temperature After dropping to safety range, subcard recovers normal work and need not restart mainboard automatically.

Description of the drawings

Fig. 1 is the power-on time sequence control circuit block diagram of PCIE boards.

Fig. 2 is the principle design figure of delay circuit.

Fig. 3 is the principle design figure of overheating protection circuit.

Fig. 4 is the structural representation of restoring circuit.

Fig. 5 is the circuit theory diagrams that temperature recovers after normal automatically upper electricity after overtemperature protection.

Fig. 6 is electrifying timing sequence figure.

Specific embodiment

The present invention is to go to control P2 using same control power supply P1, and P3 ... Pn, the P1 stable time is set to t1=P1, The time of P2 power goods is t2=P1+P2+t12, and the time of the power good of P3 is t3=P1+P3+t13, and the power supply of Pn is steady The fixed time is tn=P1+Pn+t1n, and wherein P1, P2 ... Pn represent the power supply time-to-climb of each power module, and t1n is P1 Interval time during power good and between the enable unlatchings of Pn power supplys, as long as ensureing t1 ＜ t2 ＜ t3 ＜ ... ＜ tn and tn= Into meeting design requirement immediately, actually P1+Pn+t1n is exactly the power supply of electricity on last to P1+Pn+t1n ＜ T, total upper electricity Time i.e. tn=P1+Pn+t1n, much smaller than the P1+P2+P3 that the control method of the method for designing recursion of many boards is obtained + ...+P (the n-1)+Pn times, the method for the recursion control that most of boards are taken is the time-to-climb of each power module It is cumulatively added in next stage, and the present invention is then to go control with P1, quite need not be waited separately with P2, P3 ... Pn power supplys One power supply climbs start to climb again after ok completely, but climbs together or be to wait for previous power supply and do not climb for a moment but also not Start to climb after the ok that climbs completely, as long as ensureing P1, P2, P3 ... Pn climbed successively, (i is to remove to control Pi using P1 The module of i-th power supply) enable (RC or inhibit), between P1 and enable delay times tdi compensation different electrical power The time-to-climb speed of intermodule goes up successively electricity ensureing P1, P2, P3 ... Pn, first sets most slow power supply Pn and climbs to steady Fixed time tn=t1+tdi+tn, then front several power supplys of retrodicting out successively climb to the stable time, so as to set P1 and The delay times between the enable of Pi.In addition the present invention is to do delay control circuit using simple RC capacitance-resistances, and cost is relatively low, Also can be as the method for control delay using FPGA/CPLD, but cost is of a relatively high, and larger PCB surface product is occupied, because Have with low cost for the present invention, the easy advantage of PCB layout.

The circuit of that power supply P1 for going up electricity at first is designed first：To require to go up the power supply used by that power supply of electricity at first The enable pin (title such as generally referred to as RUN, RC, Inhibit) of circuit directly draw high (most power modules Enable pin are vacantly high level), first power supply is denoted as P1.(subsequent design overtemperature protection is also needed the enable of P1 Pin is connected to the alert pin of overtemperature protection IC, sees subsequent step, wouldn't design this function, follow-up redesign)

Upper electric priority time interval of the calculating and setting per two neighboring power supply：Assume that chip requires to have been gone up in the T ms times Electricity, we are to leave certain safety range, select to have gone up electricity in (T-10) ms times, P1, P2 ... P (n-1), P (n) are per phase Adjacent two power supply electrifyings are successively spaced (T-10-ts1) ms/ (n-1).

The power circuit of Pn is calculated with the delay time tdn between P1：

(T-10) ms according to selecting completes all of power up requirement, tdn=delay (n-1)=(T- between P1 and Pn 10)-ts1-tsn, using RC delay circuits are done, and the needs for selecting P1 and Pn power modules meet following requirement：ts1+tdn+ Tsn ＜=(T-10) ms and ts1+tsn ＜ (T-10) ms.

Note：1st power module Vin is reached after input voltage claimed range, is driven high enable from RC pins steady to output Time needed for fixed required P1 magnitudes of voltage is ts1ms, and last power module Vin reaches input voltage claimed range Afterwards, the time being driven high needed for Pn magnitudes of voltage of the enable to output required for stable from RC pins is tsn ms, then P1 and Pn Between delay (n) be T-10-ts1-tsn ms to the maximum, ts is referring to the datasheet of power Module, and below figure is red Color round frame is illustrated, if the power module of designed, designed, then can first measure the power-on time ts of power, PCIE Card majority uses module (being limited to PCB layout space).

Calculate other each power supplys Pi (Pi is i-th power supply) and reach requirement stationary value (completing upper electricity) with P1 power supplys Time interval Ti：(T-10-ts1) * (i-1)/(n-1),

Ti is that the time interval that i-th power supply completes upper electricity with the 1st power supply is denoted as, then：

Ti=tdi+tsi+ts1=(T-10-ts1) * (i-1)/(n-1) (wherein 1 ＜ i ＜ n)

Note：(1) (T-10) for all power supplys electricity has all been gone up in t-10ms

(2) (T-10-ts1) ms/ (n-1) is the interval time that n power supply each two adjacent power completes electricity

(3) (T-10-ts1) * (i-1)/(n-1) is the time for completing electricity between i-th power supply and first power supply P1 Interval.

(4) tdi for P1 to Pi delay circuit delay, delay1, the delay2 in See Figure ... delayn, this Ts rise time of the value not comprising power module.

The power-on time of (5) i-th power supply is denoted as Tio=Ti+ts1

(6) power-on time of last power supply need to meet Tno=Tn+ts1 ＜ (T-10) ms.

Delay circuit：Tdi=(T-10-ts1) * (i-1)/(n-1)-tsi, constraints is tdi ＞ 0.

First select an audion, for doing on-off control, it is assumed that the conducting voltage of audion be Vo, then select P1 with The delay times between each power supply control following Fig. 2 by RC and audion,

Following relation is obtained by KCL philosophys：Vo/K2i+Ci*dVo/dt=(P1-Vo)/Ki1, solves the differential equation Obtain：T=tdi=(K2i//K1i) * Ci*In [V ∞/(V ∞-Vo)] --- -- 1. (K2i//K1i) represent K2i and K1i's and Connection, P1 is the supply voltage value of first upper electricity.

V ∞=P1*K2i/ (K1i+K2i) --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- -2.

Make Vo=VBEsat----------------------------------------------- --- -- 3.

VBEsat is BJT (the saturation conduction voltage of Q79), looks into the datasheet of device.

Make t=tdi=(T-10-ts1) * (i-1)/(n-1)-tsi----------------------------- 4.

Parameter declaration：(1) T is the time of the upper complete all of electricity that chip is required

(2) i is to complete electricity i-th in order

(3) n has the number of the power supply of electrifying timing sequence requirement for chip

(4) ts1 be the 1st upper electricity power supply selected by power module opening time, i.e., from

Power module by enable open start out-put supply to Pi stabilize to arrange needed for reach voltage pi values when Between, referring to the ts of the datasheet of power module.

(5). the Vin of power module 1 is reached after input voltage claimed range, is driven high enable from RC pins stable to output Required P1 magnitudes of voltage needed for time.

Fig. 6 is electrifying timing sequence figure.

Above synthesis 1. 2. 3. 4. three equations are obtained Ci, the value of K1i, K2i

Fine setting Ci, the value of K1i, K2i：Because actual capacitance-resistance value is not continuous, but centrifugal pump, according to solve come C, K value, goes for close capacitance, and resistance substitutes into t=tdi=(K2i//K1i) * Ci*In [V ∞/(V ∞-Vo)] --- -1. ask P1 to Pi power supplys the delay opening times, it is last only simultaneously to meet as follows 5. 6. relation：

Tdi+ts1+tsi ＜ td (i+1)+ts1+ts (i+1) --- --- --- -5. it is that i-th electricity is first gone up than i+1 electricity

6. ts1+td (n)+ts (n) ＜ (T-10) ms--------------------------- establishes by cable from first Climbing beginning, time for having climbed to n-th (last electricity), ((T-10) ms was reserved by chip want in seeking time T range The surplus capacity of 10ms), the following Fig. 2 of schematic diagram design method, the RC of power module of Pi (1 ＜ i ＜=n) delay circuit Pin is that enable enables pin, and some power modules are Inhibit pin, and function phase is same.

Overheating protection circuit：

When chip temperature reaches safety range warning line, alarm is needed, if temperature continues soaring, directly cut off electricity Source circuit, method is to go to detect the temperature of chip using a thermal sensor with IIC interfaces, and chip passes through IIC Interface reads the temperature of oneself from thermal sensor, by software code realization when the temperature read reaches warning temperature T1 (such as 100 DEG C) then gets Warning information toward on screen, and when temperature is read T2 (such as 110 DEG C) is continued to rise to When, directly the alert pin (T_CRIT_A_L) of Thermal sensor are dragged down, give the enable of P1 by this signal (inhibit), following Fig. 5, P1 mono- power down, then the enable pins (RC pins) of all of power supply Pi are all drawn by control in Fig. 4 It is low, so that all non-transformer output of Pi power modules, accomplishes overheated power-off protection function.Realize that schematic diagram sees below Fig. 3.

Restoring circuit：Subcard recovers normal work circuit automatically after overtemperature protection temperature is reduced：

Thermal sensor in Fig. 3 are detected again can be by alert pin (T_ after the temperature of master chip is recovered normally CRIT_A_L) draw high, give the enable (inhibit) of P1 by this signal so that P1 power modules start normal output voltage P1, then the Pi of Fig. 4 all start output voltage to master chip, now master chip power supply ok are needed to master chip one Reset# signals complete to reset, and subcard then can restart to work together, and this Reset# signal is by the reset in lower Fig. 5 Time control circuit is realized.Due to master chip power-off after subcard Thermal protection, master chip disconnects with the PCIE link links of mainboard, (remove PCIE device and insertion PCIE device mainboard can be certainly if mainboard does not possess hot plug PCIE device function Dynamic identification, then subcard cannot obtain corresponding software and hardware resources and will be unable to work, it is therefore desirable to plus a PCIE Switch conduct One bridge joint, it is ensured that subcard and mainboard have all the time the PCIE links of physics.Subcard overtemperature protection temperature recovers normal rear subcard certainly It is dynamic to recover the following Fig. 4 of normal work circuit block diagram.

, there is unpredictable failure or the program race for happening suddenly after board runs for a long time in hot reset functional circuit When winged, hot reset can be done to board, allow board to reenter normal condition.

Implementation method is：The Board_PERST_L GPIO of PCIE_switch being connected in Fig. 5, when program fleet Afterwards, the GPIO of PCIE_switch can first be dragged down by the subcard driver at mainboard end, then postpones certain hour post-tensioning Height, resets again after U34 to master chip, that is, realize hot reset, with reset time control circuits connect together realize and Relation, i.e. hot reset function, subcard overtemperature protection temperature recover it is normal after subcard recover normal work function automatically while can be with All support.

It is to be understood that, present invention and specific embodiment are intended to prove the reality of technical scheme provided by the present invention Border is applied, and should not be construed as limiting the scope of the present invention.Those skilled in the art open in spirit and principles of the present invention Give, can various modifications may be made, equivalent or improve.But these changes are changed in the pending protection domain of application.

Claims (6)

1. a kind of overtemperature protection of PCIE boards and restoring circuit, it includes：DC source P1, DC source P4 and chip 1, core Piece 2；Characterized in that, the overtemperature protection and restoring circuit include：Electric unit, overtemperature protection unit and recovery electricity in time delay Road；The DC source P1 and the DC source P4 respectively access 12V external power supplys and 12V PCIE power supplys；The chip 1 respectively with electric unit, the restoring circuit, the chip 2 and the overtemperature protection list in the DC source P1, the time delay Unit's connection；The chip 2 connects respectively with the DC source P4 with the restoring circuit；

Electric unit includes in the time delay：Delay circuit 1, delay circuit 2, electrical switch 2, electrical switch 3 and DC source P2, DC source P3；The delay circuit 1, electrical switch 2 and DC source P2 are sequentially connected；The delay circuit 2, electrical switch 3 and DC source P3 are sequentially connected；The delay circuit 1 and the delay circuit 2 are connected respectively with the DC source P1；Institute State the DC source P2 and DC source P3 and respectively access the 12V external power supplys and 12V PCIE power supplys reception 12V voltages, the DC source P2, the DC source P3 are connected with the chip 1；

The overtemperature protection unit includes：Heat sensor, overheating protection circuit and heat sensor control chip；The heat sensor Connect with the chip 1, the overheating protection circuit and the heat sensor control chip respectively；The heat sensor controls core Piece is controlled by controlling bus to the heat sensor；

The restoring circuit include PCIE Switch chips, PCIE adapters and with door；The PCIE Switch chips pass through PCIE channel connects respectively with the chip 1 and the PCIE adapters；It is described to receive the PCIE Switch cores respectively with door The Reset_L signals that piece and the PCIE adapters send, and reset control is carried out to the chip 1 according to the signal for receiving System.

2. overtemperature protection according to claim 1 and restoring circuit, it is characterised in that the delay circuit includes：Resistance R490, resistance R491, resistance R492, resistance R683, resistance R881, resistance R882, resistance R883, electric capacity C812, electric capacity C814, Audion Q79, audion Q81 and power module；The power module arranges connection end 1, connection end 2, connection end 3, connection end 4, connection end 5, connection end 6, connection end 7, connection end 8；Resistance R491 one end receiving data signal, the other end and electric capacity C812 and The base stage connection of the parallel-connection structure of resistance R492 and audion Q79, the parallel-connection structure of electric capacity C812 and resistance R492 it is another End and the grounded emitter of audion Q79；The colelctor electrode of audion Q79 is connected by resistance R490 and 3.3V DC source, and It is connected with the base stage of audion Q81 by resistance R882；The one of the grounded emitter of audion Q81, colelctor electrode and resistance R883 End connection；The other end of resistance R883 is connected respectively with one end of electric capacity C814 and one end of resistance R683；Resistance R683 is another Termination 3.3V DC sources；The electric capacity C814 other ends are grounded；One end that electric capacity C814 is connected with resistance R883 also with the power supply The connection end 3 of module connects；In the power module, connection end 1 is power input pin, and connection end 4 is hanging pin, even Connect end 5 and connect regulating resistor R881, the regulating resistor R881 other ends are grounded, connection end 6 reaches required for out-put supply Stationary value after indication signal, vacantly, connection end 2, connection 7 be grounded, connection end 8 be power module output pin, connection end 3 It is that power module enables control end, 3.3V DC sources is connected by resistance R683.

3. overtemperature protection according to claim 1 and restoring circuit, it is characterised in that the heat sensor control chip is adopted With the chip of model TLR36480；The controlling bus are iic bus.

4. overtemperature protection according to claim 1 and restoring circuit, it is characterised in that the overheating protection circuit includes type Number for PMR5118 power module and connected model LM95235QEIMM/NOPb chip；The model The power module of PMR5118 is connected with the heat sensor.

5. overtemperature protection according to claim 1 and restoring circuit, it is characterised in that the PCIESwitch chips are arranged The oriented chip 1 sends the GPIO port for recovering signal；The PCIE Switch chips have hot reset function.

6. overtemperature protection according to claim 1 and restoring circuit, it is characterised in that the chip 1 and the chip 2 are Chip with PCIE interfaces.