CN110399027B - Reset circuit - Google Patents
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- CN110399027B CN110399027B CN201910656878.3A CN201910656878A CN110399027B CN 110399027 B CN110399027 B CN 110399027B CN 201910656878 A CN201910656878 A CN 201910656878A CN 110399027 B CN110399027 B CN 110399027B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
Abstract
The embodiment of the invention discloses a reset circuit, which comprises a cable connector, a cable state detector and a reset chip, wherein the cable connector is connected with the cable state detector; the reset chip is connected with the enabling end of the cable state detector and used for controlling enabling of the cable state detector. The input end of the cable state detector is connected with the cable connector, and the output end of the cable state detector is connected with the reset port of the reset chip and used for controlling the reset port to execute reset operation according to the number of cables connected into the cable connector. After the reset port executes the reset operation, the reset chip can adjust the data bandwidth of the reset port according to the number of cables accessed by the cable interface, so that the consistency of the data bandwidth provided by the reset port and the total bandwidth of the cables is ensured. The reset circuit realizes the reset operation of the reset port through the mutual matching of hardware equipment, the hardware circuit is not influenced by network signals, and the stability of port reset is improved.
Description
Technical Field
The invention relates to the technical field of port reset, in particular to a reset circuit.
Background
The reset circuit is a circuit device for restoring the circuit to the initial state, and the operation principle of the reset circuit is different from that of a calculator, and only the starting principle and means are different. The reset circuit is used to restore the circuit to the initial state. The method acts as a zero clearing button of the calculator so as to return to the original state and carry out calculation again.
Non-transparent Bridging (NTB) functions similarly to a transparent bridge, with only one major difference being that there are intelligent devices or processors on both sides of the Non-transparent bridge, and they have independent address spaces. And hosts on one side of the non-transparent bridge cannot see the full address or I/O space on the other side of the bridge. Each processor sees the other side of the non-transparent bridge as an end point (endpoint) and maps it to its own address space. Typically, a PCIE switch chip includes multiple NTB ports, each having its own reset pin. In the prior art, software is mostly adopted to detect the state of each port, and the port is controlled to reset through the software when the change of the number of cables or the abnormality of the port is detected. The stability of the software control port reset is poor.
It can be seen that how to improve the stability of port reset is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
An object of the embodiments of the present invention is to provide a reset circuit, which can improve the stability of port reset.
To solve the above technical problem, an embodiment of the present invention provides a reset circuit, including a cable connector, a cable status detector, and a reset chip;
the reset chip is connected with the enabling end of the cable state detector and is used for controlling enabling of the cable state detector;
the input end of the cable state detector is connected with the cable connector, and the output end of the cable state detector is connected with the reset port of the reset chip, and the cable state detector is used for controlling the reset port to execute reset operation according to the number of cables connected into the cable connector.
Optionally, the cable connector includes four cable interfaces; the first reset port of the reset chip is connected with the first interface and the second interface of the cable connector; and a second reset port of the reset chip is connected with a third interface and a fourth interface of the cable connector.
Optionally, the cable status detector comprises a first cable status detector and a second cable status detector;
the reset chip is respectively connected with the enable end of the first cable state detector and the enable end of the second cable state detector and is used for controlling the enable of the first cable state detector and the second cable state detector in a first reset mode;
the input end of a first cable state detector is connected with a first interface and a second interface of the cable connector, and the output end of the first cable state detector is connected with a first reset port of the reset chip and used for controlling the first reset port to reset when the first interface and the second interface are inserted into cables in a first reset mode;
the input end of a second cable state detector is connected with a third interface and a fourth interface of the cable connector, and the output end of the second cable state detector is connected with a second reset port of the reset chip and used for controlling the second reset port to reset when the third interface and the fourth interface are inserted into cables in a first reset mode.
Optionally, the cable status detector further comprises a third cable status detector;
the reset chip is connected with an enabling end of the third cable state detector and used for forbidding the third cable state detector to enable in a first reset mode; in a second reset mode, disabling the first cable status detector and the second cable status detector and controlling the third cable status detector to be enabled; the first reset port of the reset chip is connected with the third interface and the fourth interface of the cable connector;
the input end of the third cable state detector is connected with the first interface, the second interface, the third interface and the fourth interface of the cable connector, and the output end of the third cable state detector is connected with the first reset port of the reset chip and used for controlling the first reset port to reset when the first interface, the second interface, the third interface and the fourth interface are all inserted into cables in the second reset mode.
Optionally, the cable connector is connected to each cable status detector through an or gate chip;
the input end of the first OR gate chip is respectively connected with the first interface and the second interface of the cable connector, and the output end of the first OR gate chip is respectively connected with the input end of the first cable state detector and one input end of the third OR gate chip;
the input end of the second or gate chip is respectively connected with the third interface and the fourth interface of the cable connector, and the output end of the second or gate chip is respectively connected with the input end of the second cable state detector and the other input end of the third or gate chip;
and the output end of the third OR gate chip is connected with the input end of the third cable state detector.
Optionally, the cable status detector comprises a flip-flop and a level shifter.
Optionally, the GPIO port of the reset chip is connected to the enable end of each cable state detector through a level shifter;
the input end of a first level shifter is connected with the GPIO port of the reset chip, and the output end of the first level shifter is respectively connected with the input end of a second level shifter, the enabling end of the first cable state detector and the enabling end of the second cable state detector;
the output end of the second level shifter is connected with the enabling end of the third cable state detector.
Optionally, the level shifter is an NMOS transistor.
Optionally, the TRIGGER is a TRIGGER; the TRIGGER is used for outputting a high level of preset time when detecting the falling edge of the input end.
Optionally, the reset chip is a PCIE switch chip.
According to the technical scheme, the reset circuit comprises a cable connector, a cable state detector and a reset chip; the reset chip is connected with the enabling end of the cable state detector and used for controlling enabling of the cable state detector. The input end of the cable state detector is connected with the cable connector, and the output end of the cable state detector is connected with the reset port of the reset chip and used for controlling the reset port to execute reset operation according to the number of cables connected into the cable connector. After the reset port executes the reset operation, the reset chip can adjust the data bandwidth of the reset port according to the number of cables accessed by the cable interface, so that the consistency of the data bandwidth provided by the reset port and the total bandwidth of the cables is ensured. The reset circuit realizes the reset operation of the reset port through the mutual matching of hardware equipment, the hardware circuit is not influenced by network signals, and the stability of port reset is improved.
Drawings
In order to illustrate the embodiments of the present invention more clearly, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a schematic structural diagram of a reset circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a hardware connection of a reset circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without any creative work belong to the protection scope of the present invention.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Next, a reset circuit according to an embodiment of the present invention will be described in detail. Fig. 1 is a schematic structural diagram of a reset circuit according to an embodiment of the present invention, which includes a cable connector 11, a cable status detector 12, and a reset chip 13.
The cable connector 11 is provided with a cable interface for inserting a cable.
The reset chip 13 includes a reset port, and when the cable is inserted into the cable connector 11, in order to ensure that the data bandwidth of the reset port is consistent with the total bandwidth of the cable, the reset port needs to be reset.
The reset port of the reset chip 13 is connected to the cable interface of the cable connector 11, and after the reset port performs the reset operation, the data bandwidth of the reset port is adjusted according to the number of cables connected to the cable interface.
The reset chip 13 is connected to an enable terminal of the cable status detector 12, and is used for controlling enabling of the cable status detector 12. The cable status detector 12 is only functional on in the enabled state.
The input end of the cable status detector 12 is connected to the cable connector 11, and the output end of the cable status detector 12 is connected to the reset port of the reset chip 13, so as to control the reset port to perform reset operation according to the number of cables connected to the cable connector 11.
In practical applications, one cable corresponds to 4 lanes (lanes), and each reset port can provide 4 lanes in a default state. When a new cable is inserted, the corresponding reset port needs to perform a reset operation, thereby providing 8 lanes according to the number of connected cables.
The conventional reset chip 13 has 2 reset ports, and for convenience of distinction, the 2 reset ports may be referred to as a first reset port and a second reset port, respectively.
The cable connector 11 may employ a new generation SAS storage interface MINI SAS HD.
The cable connector 11 may be provided with four cable ports. Taking 4 cables as an example, after the 4 cables are inserted into the four cable interfaces of the cable connector 11, the reset port of the reset chip 13 needs to provide 16 channels.
It is contemplated that up to 16 channels may be provided per reset port. In the embodiment of the present invention, two reset modes may be provided to implement the provision of 16 channels, and the first reset mode may perform a reset operation on two reset ports, each of which provides 8 channels. The second reset mode may perform a reset operation with one reset port, providing 16 channels through one reset port.
In practical applications, the first reset mode may be applicable to the case where 1 to 4 cables are inserted into the cable connector 11. The second reset mode is applicable to the case where 4 cables are inserted into the cable connector 11.
For the first reset mode, two cable state detectors 12 may be provided, a first cable state detector and a second cable state detector, respectively. A first reset port of the reset chip 13 is connected to the first interface and the second interface of the cable connector 11; the second reset port of the reset chip 13 is connected to the third interface and the fourth interface of the cable connector 11. The reset chip 13 is connected to the enable terminal of the first cable status detector and the enable terminal of the second cable status detector, respectively, and is configured to control the enabling of the first cable status detector and the second cable status detector in the first reset mode.
The input end of the first cable status detector is connected to the first interface and the second interface of the cable connector 11, and the output end of the first cable status detector is connected to the first reset port of the reset chip 13, so as to control the first reset port to reset when the first interface and the second interface are plugged into cables in the first reset mode.
The input end of the second cable state detector is connected to the third interface and the fourth interface of the cable connector 11, and the output end of the second cable state detector is connected to the second reset port of the reset chip 13, so as to control the second reset port to reset when the third interface and the fourth interface are plugged into cables in the first reset mode.
For the second reset mode, a third cable status detector may be provided on the basis of the first cable status detector and the second cable status detector.
In the second reset mode, the reset principle of the two reset ports is the same, and in the embodiment of the present invention, the reset of the first reset port is taken as an example for description.
In the second reset mode, the first reset port may be connected to the first interface, the second interface, the third interface, and the fourth interface of the cable connector 11, respectively. The reset chip 13 is connected to an enable end of the third cable status detector, and is configured to disable the third cable status detector from enabling in the first reset mode; in the second reset mode, the first cable status detector and the second cable status detector are disabled from being enabled, and the third cable status detector is controlled to be enabled.
The input end of the third cable status detector is connected to the first interface, the second interface, the third interface and the fourth interface of the cable connector 11, and the output end of the third cable status detector is connected to the first reset port of the reset chip 13, so as to control the first reset port to reset when the first interface, the second interface, the third interface and the fourth interface are all plugged into cables in the second reset mode.
In the embodiment of the invention, the connection between the cable connector and the cable status detector can be realized by adopting an OR gate chip. Taking 3 cable status detectors as an example, 3 or chips may be provided, which are a first or chip, a second or chip and a third or chip respectively.
Specifically, the input end of the first or gate chip may be connected to the first interface and the second interface of the cable connector 11, respectively, and the output end of the first or gate chip may be connected to the input end of the first cable status detector and an input end of the third or gate chip, respectively; the input end of the second or gate chip is connected to the third interface and the fourth interface of the cable connector 11, respectively, and the output end of the second or gate chip is connected to the input end of the second cable status detector and the other input end of the third or gate chip, respectively; and the output end of the third OR gate chip is connected with the input end of the third cable state detector.
In an embodiment of the present invention, the cable status detector 12 may include a flip-flop and a level shifter.
When the level shifter has an input high level, a low level is output; when a low level is input, a high level performance is output. In practical applications, the level shifter may employ NMOS transistors.
The TRIGGER can adopt a TRIGGER; the TRIGGER is used for outputting a high level of preset time when detecting the falling edge of the input end.
The reset chip 13 has a high level enabling performance, and in the embodiment of the present invention, a GPIO port of the reset chip 13 may be connected to an enabling end of each cable state detector 12 through a level shifter; the input end of the first level shifter is connected with the GPIO port of the reset chip 13, and the output end of the first level shifter is respectively connected with the input end of the second level shifter, the enabling end of the first cable state detector and the enabling end of the second cable state detector; the output end of the second level shifter is connected with the enabling end of the third cable state detector.
In practical applications, the reset chip 13 may adopt a PCIE switch chip. The first level shifter and the second level shifter may employ NMOS transistors.
As shown in fig. 2, which is a schematic diagram of the hardware connection of the reset circuit when 3 cable status detectors are provided, the cable connector includes 4 cable ports, which are MINI SAS HD 1, MINI SAS HD 2, MINI SAS HD 3 and MINI SAS HD 4 from top to bottom. And the 3 cable state detectors are composed of TRIGGERs and NMOS transistors. To facilitate the distinction of the 3 cable status detectors, 3 flip-flops are respectively represented in fig. 2 for TRIGGER1, TRIGGER2 and TRIGGER3, and NMOS transistors connected to the flip-flops are represented by Q3, Q4 and Q5. The PCIE switch chip includes 2 reset ports, which are respectively NTO _ PERST and NT1_ PERST. PCIE switch chip pass
In the first reset mode, the PCIE switch chip may output a low level through the GPIO port, and when the low level passes through the first level shifter (Q1), the low level may output a high level to the enable terminal (TRIGGER enable) of TRIGGER1 and the enable terminal of TRIGGER2, thereby triggering TRIGGER1 and TRIGGER2 to be enabled.
In the second reset mode, the PCIE switch chip may output a high level through the GPIO port, and the high level may output a low level when passing through the first level shifter (Q1); when the low level passes through the second level shifter (Q2), a high level may be output to the enable terminal of TRIGGER2, which may TRIGGER3 to enable accordingly.
Or the gate chip outputs low level only when the input is low level, when the TRIGGER detects that the input end is converted from high level to low level, the TRIGGER can output high level of preset time, and the high level can output electric level to the reset port through the level shifter, so that the reset port is triggered to execute reset operation.
The MODPRS pins of the MINI SAS HD cable connector are often high and are pulled low when MINI SAS HD cable is inserted.
In the first reset mode, when a cable is inserted into the MINI SAS HD 1 connector, the PCIE SWITCH chip recognizes 4 lanes, and establishes a PCIE connection with an external device connected to the cable. When a cable is continuously inserted into the MINI SAS HD 2 connector, the TRIGGER1 detects a falling edge input, the TRIGGER1 outputs a high level for a certain time, the high level drives the NMOS transistor to be conducted, the reset pin of the NT0 port is pulled down, the NT0 port is reconnected after being reset, at the moment, two cables are inserted, 8 lanes are identified, and therefore the bandwidth is increased along with the insertion of the cables.
In the second reset mode, when a cable is inserted into the MINI SAS HD 1 connector, the PCIE SWITCH chip recognizes 4 lanes, and establishes a PCIE connection with the external device connected to the cable. When continuing to plug cables to the MINI SAS HD 2 and MINI SAS HD 3 connectors, the PCIE bandwidth of the NTB ports does not increase. When the fourth cable is inserted, TRIGGER3 will detect a falling edge input, and TRIGGER3 will output a high level for a certain time, the high level drives the NMOS transistor to conduct, the reset pin of NT0 port is pulled down, NT0 port will LINK again after reset, at this time, four cables are inserted, and 16 lanes will be identified.
According to the technical scheme, the reset circuit comprises a cable connector, a cable state detector and a reset chip; the reset chip is connected with the enabling end of the cable state detector and used for controlling enabling of the cable state detector. The input end of the cable state detector is connected with the cable connector, and the output end of the cable state detector is connected with the reset port of the reset chip and used for controlling the reset port to execute reset operation according to the number of cables connected into the cable connector. After the reset port executes the reset operation, the reset chip can adjust the data bandwidth of the reset port according to the number of cables accessed by the cable interface, so that the consistency of the data bandwidth provided by the reset port and the total bandwidth of the cables is ensured. The reset circuit realizes the reset operation of the reset port through the mutual matching of hardware equipment, the hardware circuit is not influenced by network signals, and the stability of port reset is improved.
A reset circuit provided in an embodiment of the present invention is described in detail above. The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Claims (6)
1. A reset circuit is characterized by comprising a cable connector, a cable state detector and a reset chip;
the cable connector comprises four cable interfaces; the first reset port of the reset chip is connected with the first interface and the second interface of the cable connector; a second reset port of the reset chip is connected with a third interface and a fourth interface of the cable connector;
the cable state detector comprises a first cable state detector, a second cable state detector and a third cable state detector;
the reset chip is respectively connected with the enable end of the first cable state detector and the enable end of the second cable state detector and is used for controlling the enable of the first cable state detector and the second cable state detector in a first reset mode;
the input end of a first cable state detector is connected with a first interface and a second interface of the cable connector, and the output end of the first cable state detector is connected with a first reset port of the reset chip and used for controlling the first reset port to reset when the first interface and the second interface are inserted into cables in a first reset mode;
the input end of a second cable state detector is connected with a third interface and a fourth interface of the cable connector, and the output end of the second cable state detector is connected with a second reset port of the reset chip and used for controlling the second reset port to reset when the third interface and the fourth interface are inserted into cables in a first reset mode;
the reset chip is connected with an enabling end of the third cable state detector and used for forbidding the third cable state detector to enable in a first reset mode; in a second reset mode, disabling the first cable status detector and the second cable status detector and controlling the third cable status detector to be enabled; the first reset port of the reset chip is connected with the third interface and the fourth interface of the cable connector;
the input end of a third cable state detector is connected with the first interface, the second interface, the third interface and the fourth interface of the cable connector, and the output end of the third cable state detector is connected with the first reset port of the reset chip and used for controlling the first reset port to reset when the first interface, the second interface, the third interface and the fourth interface are all inserted into cables in a second reset mode;
the cable connector is connected with each cable state detector through an OR gate chip;
the input end of the first OR gate chip is respectively connected with the first interface and the second interface of the cable connector, and the output end of the first OR gate chip is respectively connected with the input end of the first cable state detector and one input end of the third OR gate chip;
the input end of the second or gate chip is respectively connected with the third interface and the fourth interface of the cable connector, and the output end of the second or gate chip is respectively connected with the input end of the second cable state detector and the other input end of the third or gate chip;
and the output end of the third OR gate chip is connected with the input end of the third cable state detector.
2. The reset circuit of claim 1, wherein the cable status detector comprises a flip-flop and a level shifter.
3. The reset circuit of claim 2, wherein the GPIO port of the reset chip is connected to the enable terminal of each cable status detector through a level shifter;
the input end of a first level shifter is connected with the GPIO port of the reset chip, and the output end of the first level shifter is respectively connected with the input end of a second level shifter, the enabling end of the first cable state detector and the enabling end of the second cable state detector;
the output end of the second level shifter is connected with the enabling end of the third cable state detector.
4. The reset circuit of claim 3, wherein the level shifter is an NMOS transistor.
5. The reset circuit of claim 2, wherein the flip-flop is a TRIGGER flip-flop; the TRIGGER is used for outputting a high level of preset time when detecting the falling edge of the input end.
6. The reset circuit of any one of claims 1-5, wherein the reset chip is a PCIE switch chip.
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| CN201910656878.3A CN110399027B (en) | 2019-07-19 | 2019-07-19 | Reset circuit |
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| CN111817904B (en) * | 2020-09-04 | 2021-03-09 | 苏州浪潮智能科技有限公司 | Bandwidth recovery method, device and medium based on PCIE Switch |
| CN112269753A (en) * | 2020-10-23 | 2021-01-26 | 苏州浪潮智能科技有限公司 | PCIE link management method, system and related assembly |
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