CN110399027A - A kind of reset circuit - Google Patents
A kind of reset circuit Download PDFInfo
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- CN110399027A CN110399027A CN201910656878.3A CN201910656878A CN110399027A CN 110399027 A CN110399027 A CN 110399027A CN 201910656878 A CN201910656878 A CN 201910656878A CN 110399027 A CN110399027 A CN 110399027A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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Abstract
The embodiment of the invention discloses a kind of reset circuit, reset circuit includes wire and cable connector, cable state detector and reset chip；Reset chip is connect with the enable end of cable state detector, for the enabled of controlling cable state detector.The input terminal of cable state detector is connect with wire and cable connector, and the output end of cable state detector and the reseting port of reset chip connect, and for accessing the number of cable according to wire and cable connector, control reseting port, which executes, resets operation.After reseting port executes reset operation, reset chip can access the number of cable according to cable interface, adjust the data bandwidth of reseting port, to guarantee the consistency of the data bandwidth that reseting port provides and cable total bandwidth.The reset circuit realizes the reset operation of reseting port by the mutual cooperation of hardware device, and hardware circuit is not influenced by network signal, improves the stability of port reset.
Description
Technical field
The present invention relates to port reset technical fields, more particularly to a kind of reset circuit.
Background technique
Reset circuit is a kind of for making circuit return to the circuit arrangement of state, its operating principle and calculator
That plays the same tune on different musical instruments is wonderful, and only starting pinciple and means are different.Reset circuit has exactly been restored to circuit using it
Beginning state.Just as the effect of the reset button of calculator, to return to reset condition, calculating is re-started.
The function and transparent bridge of nontransparent bridge joint (Non-transparent Bridging, NTB) are much like, main poor
A little Zhi You there are not smart machine or processor on the both sides of non-transparent bridge, and they possess independent address space.
And the host on non-transparent bridge one side cannot see that the full address or input/output space of bridge another side.Each processor is nontransparent
The another side of bridge regards an endpoint (endpoint) as, and it is mapped to the address space of oneself.A usual PCIE
Switch chip includes multiple ports NTB, and there is the reset pin of oneself in each port.Existing technology mostly uses software to examine greatly
The state for surveying each port is resetted when detecting number of cables variation or port exception by software control port.Software control
The stability of port reset processed is poor.
It is those skilled in the art's problem to be solved as it can be seen that how to promote the stability of port reset.
Summary of the invention
The purpose of the embodiment of the present invention is that providing a kind of reset circuit, the stability of port reset can be promoted.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of reset circuit, including it is wire and cable connector, cable-shaped
State detector and reset chip；
The reset chip is connect with the enable end of the cable state detector, for controlling the cable state detection
Device enables；
The input terminal of the cable state detector is connect with the wire and cable connector, the cable state detector it is defeated
Outlet is connect with the reseting port of the reset chip, for accessing the number of cable according to the wire and cable connector, controls institute
It states reseting port and executes and reset operation.
Optionally, the wire and cable connector includes four cable interfaces；First reseting port of the reset chip and institute
State first interface and the second interface connection of wire and cable connector；The second reseting port and the cable of the reset chip connect
Connect third interface and the connection of the 4th interface of device.
Optionally, the cable state detector includes the first cable state detector and the second cable state detector；
The reset chip respectively with the enable end of the first cable state detector and the second cable state detector
Enable end connection, for controlling the first cable state detector and the second cable state detector under the first reset mode
It is enabled；
The input terminal of first cable state detector is connect with the first interface of the wire and cable connector and second interface,
The output end of first cable state detector is connect with the first reseting port of the reset chip, in the first reset mode
Under when the first interface and second interface insertion cable, control first reseting port and reset；
The input terminal of second cable state detector is connect with the third interface of the wire and cable connector and the 4th interface,
The output end of second cable state detector is connect with the second reseting port of the reset chip, in the first reset mode
Under when the third interface and the 4th interface insertion cable, control second reseting port and reset.
Optionally, the cable state detector further includes third cable state detector；
The reset chip is connect with the enable end of the third cable state detector, in the first reset mode
Under, forbid the third cable state detector enabled；Under the second reset mode, forbid the first cable state detector
It is enabled with the second cable state detector, and it is enabled to control the third cable state detector；The reset chip
First reseting port is connect with the third interface of the wire and cable connector and the 4th interface；
The input terminal of third cable state detector connects with the first interface of the wire and cable connector, second interface, third
Mouth and the connection of the 4th interface, the output end of third cable state detector and the first reseting port of the reset chip connect
Connect, under the second reset mode when the first interface, the second interface, the third interface and the described 4th connect
When mouth is inserted into cable, controls first reseting port and reset.
Optionally, the wire and cable connector passes through or door chip is connect with each cable state detector；
First or the input terminal of door chip connect respectively with the first interface of the wire and cable connector and second interface, institute
State output end one with the input terminal of the first cable state detector and third or door chip respectively of first or door chip
Input terminal connection；
Second or the input terminal of door chip connect respectively with the third interface of the wire and cable connector and the 4th interface, institute
State second or door chip output end it is another with the input terminal of the second cable state detector and third or door chip respectively
A input terminal connection；
The output end of third or door chip is connect with the input terminal of third cable state detector.
Optionally, the cable state detector includes trigger and level translator.
Optionally, the GPIO port of the reset chip is made with each cable state detector respectively by level translator
It can end connection；
The input terminal of first level translator is connect with the GPIO port of the reset chip, first level translator
Output end it is cable-shaped with the input terminal of second electrical level converter, the enable end of the first cable state detector and second respectively
The enable end of state detector connects；
The output end of second electrical level converter is connect with the enable end of the third cable state detector.
Optionally, the level translator is NMOS transistor.
Optionally, the trigger is TRIGGER trigger；The TRIGGER trigger is for detecting under input terminal
Drop along when export preset time high level.
Optionally, the reset chip is PCIE switch chip.
Reset circuit includes wire and cable connector, cable state detector and reset coil it can be seen from above-mentioned technical proposal
Piece；Reset chip is connect with the enable end of cable state detector, for the enabled of controlling cable state detector.Cable state
The input terminal of detector is connect with wire and cable connector, and the output end of cable state detector and the reseting port of reset chip connect
It connects, for accessing the number of cable according to wire and cable connector, control reseting port, which executes, resets operation.Reseting port executes reset
After operation, reset chip can access the number of cable according to cable interface, the data bandwidth of reseting port be adjusted, to guarantee
The consistency of data bandwidth and cable total bandwidth that reseting port provides.The reset circuit by the mutual cooperation of hardware device,
The reset operation of reseting port is realized, hardware circuit is not influenced by network signal, improves the stability of port reset.
Detailed description of the invention
In order to illustrate the embodiments of the present invention more clearly, attached drawing needed in the embodiment will be done simply below
It introduces, it should be apparent that, drawings in the following description are only some embodiments of the invention, for ordinary skill people
For member, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of structural schematic diagram of reset circuit provided in an embodiment of the present invention；
Fig. 2 is a kind of hardware connection diagram of reset circuit provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, rather than whole embodiments.Based on this
Embodiment in invention, those of ordinary skill in the art are without making creative work, obtained every other
Embodiment belongs to the scope of the present invention.
In order to enable those skilled in the art to better understand the solution of the present invention, with reference to the accompanying drawings and detailed description
The present invention is described in further detail.
Next, a kind of reset circuit provided by the embodiment of the present invention is discussed in detail.Fig. 1 provides for the embodiment of the present invention
A kind of reset circuit structural schematic diagram, including wire and cable connector 11, cable state detector 12 and reset chip 13.
The cable interface for being inserted into cable is provided on wire and cable connector 11.
It include reseting port on reset chip 13, when wire and cable connector 11 has cable insertion, in order to guarantee reset terminal
The data bandwidth of mouth is consistent with cable total bandwidth, needs to carry out reset operation to reseting port.
The reseting port of reset chip 13 is connect with the cable interface of wire and cable connector 11, resets behaviour when reseting port executes
After work, the number of cable is accessed according to cable interface, adjusts the data bandwidth of reseting port.
Reset chip 13 is connect with the enable end of cable state detector 12, for making for controlling cable state detector 12
Energy.Function is just turned on cable state detector 12 only under enabled state.
The input terminal of cable state detector 12 is connect with wire and cable connector 11, the output end of cable state detector 12 with
The reseting port of reset chip 13 connects, and for accessing the number of cable according to wire and cable connector 11, control reseting port is executed
Reset operation.
In practical applications, a cable corresponds to 4 channels (lane), can provide under each reseting port default conditions
4 lane.When there is new cable insertion, corresponding reseting port needs to be implemented reset operation, thus according to connection
Cable number provides 8 lane.
Conventional reset chip 13 is corresponding with 2 reseting ports, can be by this 2 reseting ports point for the ease of distinguishing
Also known as make the first reseting port and the second reseting port.
Wire and cable connector 11 can use a new generation's SAS memory interface, that is, MINI SAS HD.
Four cable interfaces can be set in wire and cable connector 11.By taking 4 cables as an example, connect when 4 cables are inserted into cable
After connecing four cable interfaces of device 11, the reseting port of reset chip 13 needs to provide 16 channels at this time.
In view of each reseting port at most can provide 16 channels.In embodiments of the present invention, two kinds be can be set again
Bit pattern realizes the offer in 16 channels, and the first reset mode, which can execute two reseting ports, resets operation, each port
It is provided which 8 channels.Second reset mode, which can execute a reseting port, resets operation, is provided by a reseting port
16 channels.
In practical applications, the first reset mode can be adapted for the feelings of 1 to 4 cable insertion wire and cable connector 11
Condition.Second reset mode is suitable for the case where 4 cable insertion wire and cable connector 11.
It is directed to the first reset mode, two cable state detectors 12, the inspection of respectively the first cable state can be set
Survey device and the second cable state detector.First reseting port of reset chip 13 and the first interface of wire and cable connector 11 and
Second interface connection；Second reseting port of reset chip 13 and the third interface of wire and cable connector 11 and the 4th interface connect
It connects.Reset chip 13 connects with the enable end of the first cable state detector and the enable end of the second cable state detector respectively
It connects, it is enabled under the first reset mode, controlling the first cable state detector and the second cable state detector.
The input terminal of first cable state detector is connect with the first interface of wire and cable connector 11 and second interface, the
The output end of one cable state detector is connect with the first reseting port of reset chip 13, under the first reset mode when
When first interface and second interface insertion cable, the first reseting port of control resets.
The input terminal of second cable state detector is connect with the third interface of wire and cable connector 11 and the 4th interface, the
The output end of two cable state detectors is connect with the second reseting port of reset chip 13, under the first reset mode when
When third interface and the 4th interface insertion cable, the second reseting port of control resets.
It is directed to the second reset mode, it can be on the basis of the first cable state detector and the second cable state detector
Upper setting third cable state detector.
The reset principle of two reseting ports is identical under the second reset mode, in embodiments of the present invention, multiple with first
It is unfolded to introduce for the reset of bit port.
Under the second reset mode, can by the first reseting port respectively with the first interface of wire and cable connector 11, second
Interface, third interface and the connection of the 4th interface.Reset chip 13 is connect with the enable end of third cable state detector, is used for
Under the first reset mode, forbid third cable state detector enabled；Under the second reset mode, forbid the first cable state
Detector and the second cable state detector are enabled, and it is enabled to control third cable state detector.
The input terminal of third cable state detector and first interface, second interface, the third interface of wire and cable connector 11
And the 4th interface connection, the output end of third cable state detector connect with the first reseting port of reset chip 13, use
In under the second reset mode when first interface, second interface, third interface and the 4th interface are inserted into cable, control the
One reseting port resets.
In embodiments of the present invention, can use or door chip realize wire and cable connector and cable state detector company
It connects.By taking 3 cable state detectors as an example, 3 or chip can be set, respectively first or door chip, second or Men Xin
Piece and third or door chip.
Specifically, can by first or door chip input terminal respectively with the first interface of wire and cable connector 11 and second
Interface connection, first or door chip output end respectively with the input terminal of the first cable state detector and third or door chip
An input terminal connection；Second or door chip input terminal respectively with the third interface of wire and cable connector 11 and the 4th interface
Connection, second or door chip output end it is another with the input terminal of the second cable state detector and third or door chip respectively
One input terminal connection；The output end of third or door chip is connect with the input terminal of third cable state detector.
In embodiments of the present invention, cable state detector 12 may include trigger and level translator.
When level translator has input high level, low level is exported；When input low level, the performance of high level is exported.
In practical applications, level translator can use NMOS transistor.
Trigger can use TRIGGER trigger；TRIGGER trigger is for output when detecting input terminal failing edge
The high level of preset time.
The performance that there is reset chip 13 high level to enable in embodiments of the present invention can be by reset chip 13
GPIO port is connect with the enable end of each cable state detector 12 respectively by level translator；First level translator it is defeated
Enter end to connect with the GPIO port of reset chip 13, the output end of the first level translator is defeated with second electrical level converter respectively
Enter the enable end connection of end, the enable end of the first cable state detector and the second cable state detector；Second electrical level turns
The output end of parallel operation is connect with the enable end of third cable state detector.
In practical applications, reset chip 13 can use PCIE switch chip.First level translator and the second electricity
Flat turn parallel operation can use NMOS transistor.
The hardware connection diagram of reset circuit, wire and cable connector when being illustrated in figure 23 cable state detectors of setting
Include 4 cable interfaces, is followed successively by MINI SAS HD 1, MINI SAS HD 2,3 and of MINI SAS HD from top to bottom
MINI SAS HD 4.3 cable state detectors are made of TRIGGER and NMOS transistor.For the ease of distinguishing 3 lines
Cable state detector, TRIGGER1, TRIGGER2 and TRIGGER3 are respectively used in Fig. 2 indicates 3 triggers, with Q3, Q4
The NMOS transistor being connected with trigger is indicated with Q5.PCIE switch chip includes 2 reseting ports, respectively NTO_
PERST and NT1_PERST.PCIE switch chip passes through
Under the first reset mode, PCIE switch chip can export low level, low level warp by GPIO port
When crossing the first level translator (Q1), can export a high level to the enable end (Trigger enable) of TRIGGER1 with
And the enable end of TRIGGER2, so that it is enabled to trigger TRIGGER1 and TRIGGER2.
Under the second reset mode, PCIE switch chip can export high level, high level warp by GPIO port
When crossing the first level translator (Q1), a low level can be exported；It, can when the low level passes through second electrical level converter (Q2)
To export a high level to the enable end of TRIGGER2, it is enabled that TRIGGER3 can be triggered accordingly.
Or only when input is all low level, output is just low level to door chip, TRIGGER detects input terminal by height
When level translation is low level failing edge, the high level of preset time can be exported, which passes through level translator, can
To export electric level to reseting port, operation is resetted to trigger reseting port and execute.
The MODPRS pin of MINI SAS HD wire and cable connector is often high, when the insertion of MINI SAS HD cable, can be drawn
It is low.
Under the first reset mode, when being inserted into single line cable to MINI SAS 1 connector of HD, PCIE SWITCH core
Sector-meeting recognizes 4 lane, and the external equipment connecting with the cable establishes PCIE connection.When continuing into single line cable to MINI
When SAS 2 connector of HD, TRIGGER1 can detect a failing edge input, and then TRIGGER1 can export certain time
High level, the high level drive NMOS transistor conduction, drag down the reset pin of the port NT0, the port NT0 after the reset can be again
LINK, there are two cables to be inserted at this time, can recognize 8 lane, which achieves bandwidth to increase with the insertion of cable.
Under the second reset mode, when being inserted into single line cable to MINI SAS 1 connector of HD, PCIE SWITCH core
Sector-meeting recognizes 4 lane, and the external equipment connecting with the cable establishes PCIE connection.When continuing into cable to MINI SAS
HD 2 and when MINI SAS 3 connector of HD, the PCIE bandwidth of the port NTB not will increase.When being inserted into the 4th cable
TRIGGER3 can detect a failing edge input, and then TRIGGER3 can export the high level of certain time, which drives
Dynamic NMOS transistor conduction, drags down the reset pin of the port NT0, the port NT0 after the reset can LINK again, there are four cables to insert at this time
Enter, 16 lane can be recognized.
Reset circuit includes wire and cable connector, cable state detector and reset coil it can be seen from above-mentioned technical proposal
Piece；Reset chip is connect with the enable end of cable state detector, for the enabled of controlling cable state detector.Cable state
The input terminal of detector is connect with wire and cable connector, and the output end of cable state detector and the reseting port of reset chip connect
It connects, for accessing the number of cable according to wire and cable connector, control reseting port, which executes, resets operation.Reseting port executes reset
After operation, reset chip can access the number of cable according to cable interface, the data bandwidth of reseting port be adjusted, to guarantee
The consistency of data bandwidth and cable total bandwidth that reseting port provides.The reset circuit by the mutual cooperation of hardware device,
The reset operation of reseting port is realized, hardware circuit is not influenced by network signal, improves the stability of port reset.
A kind of reset circuit is provided for the embodiments of the invention above to be described in detail.Each implementation in specification
Example is described in a progressive manner, and each embodiment focuses on the differences from other embodiments, each implementation
Same and similar part may refer to each other between example.It should be pointed out that for those skilled in the art, not
, can be with several improvements and modifications are made to the present invention under the premise of being detached from the principle of the invention, these improvement and modification are also fallen into
In the protection scope of the claims in the present invention.
Professional further appreciates that, unit described in conjunction with the examples disclosed in the embodiments of the present disclosure
And algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, in order to clearly demonstrate hardware and
The interchangeability of software, in the above description according to function generally describe it is each it is exemplary at and step.These
Function is implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Profession
Technical staff can use different methods to achieve the described function each specific application, but this realization is not answered
Think beyond the scope of this invention.
The step of method described in conjunction with the examples disclosed in this document or algorithm, can directly be held with hardware, processor
The combination of capable software module or the two is implemented.Software module can be placed in random access memory (RAM), memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technology
In any other form of storage medium well known in field.
Claims (10)
1. a kind of reset circuit, which is characterized in that including wire and cable connector, cable state detector and reset chip；
The reset chip is connect with the enable end of the cable state detector, for controlling the cable state detector
It is enabled；
The input terminal of the cable state detector is connect with the wire and cable connector, the output end of the cable state detector
It connect with the reseting port of the reset chip, for accessing the number of cable according to the wire and cable connector, controls described multiple
Bit port, which executes, resets operation.
2. reset circuit according to claim 1, which is characterized in that the wire and cable connector includes four cable interfaces；
First reseting port of the reset chip is connect with the first interface of the wire and cable connector and second interface；The reset
Second reseting port of chip is connect with the third interface of the wire and cable connector and the 4th interface.
3. reset circuit according to claim 2, which is characterized in that the cable state detector includes first cable-shaped
State detector and the second cable state detector；
The reset chip is enabled with the enable end of the first cable state detector and the second cable state detector respectively
End connection, it is enabled under the first reset mode, controlling the first cable state detector and the second cable state detector；
The input terminal of first cable state detector is connect with the first interface of the wire and cable connector and second interface, and first
The output end of cable state detector is connect with the first reseting port of the reset chip, under the first reset mode when
When the first interface and second interface insertion cable, controls first reseting port and reset；
The input terminal of second cable state detector is connect with the third interface of the wire and cable connector and the 4th interface, and second
The output end of cable state detector is connect with the second reseting port of the reset chip, under the first reset mode when
When the third interface and the 4th interface insertion cable, controls second reseting port and reset.
4. reset circuit according to claim 3, which is characterized in that the cable state detector further includes third cable
State detector；
The reset chip is connect with the enable end of the third cable state detector, for prohibiting under the first reset mode
Only the third cable state detector is enabled；Under the second reset mode, forbid the first cable state detector and institute
It is enabled to state the second cable state detector, and it is enabled to control the third cable state detector；The first of the reset chip
Reseting port is connect with the third interface of the wire and cable connector and the 4th interface；
The first interface of the input terminal of third cable state detector and the wire and cable connector, second interface, third interface with
And the 4th interface connection, the output end of third cable state detector connect with the first reseting port of the reset chip, use
In under the second reset mode when the first interface, the second interface, the third interface and the 4th interface are equal
When being inserted into cable, controls first reseting port and reset.
5. reset circuit according to claim 4, which is characterized in that the wire and cable connector passes through or door chip and each line
The connection of cable state detector；
First or the input terminal of door chip connect respectively with the first interface of the wire and cable connector and second interface, described
One or door chip an output end input with the input terminal of the first cable state detector and third or door chip respectively
End connection；
Second or the input terminal of door chip connect respectively with the third interface of the wire and cable connector and the 4th interface, described
Two or door chip output end it is defeated with another of the input terminal of the second cable state detector and third or door chip respectively
Enter end connection；
The output end of third or door chip is connect with the input terminal of third cable state detector.
6. reset circuit according to claim 5, which is characterized in that the cable state detector includes trigger and electricity
Flat turn parallel operation.
7. reset circuit according to claim 6, which is characterized in that the GPIO port of the reset chip is turned by level
Parallel operation is connect with the enable end of each cable state detector respectively；
The input terminal of first level translator is connect with the GPIO port of the reset chip, first level translator it is defeated
Outlet is examined with the input terminal of second electrical level converter, the enable end of the first cable state detector and the second cable state respectively
Survey the enable end connection of device；
The output end of second electrical level converter is connect with the enable end of the third cable state detector.
8. reset circuit according to claim 7, which is characterized in that the level translator is NMOS transistor.
9. reset circuit according to claim 6, which is characterized in that the trigger is TRIGGER trigger；It is described
TRIGGER trigger exports the high level of preset time when being used to detect input terminal failing edge.
10. reset circuit described in -9 any one according to claim 1, which is characterized in that the reset chip is PCIE
Switch chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910656878.3A CN110399027B (en) | 2019-07-19 | 2019-07-19 | Reset circuit |
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| CN201910656878.3A CN110399027B (en) | 2019-07-19 | 2019-07-19 | Reset circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111817904A (en) * | 2020-09-04 | 2020-10-23 | 苏州浪潮智能科技有限公司 | Bandwidth recovery method, device and medium based on PCIE Switch |
| CN112269753A (en) * | 2020-10-23 | 2021-01-26 | 苏州浪潮智能科技有限公司 | PCIE link management method, system and related assembly |
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