CN112269753A - PCIE link management method, system and related assembly - Google Patents
PCIE link management method, system and related assembly Download PDFInfo
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- CN112269753A CN112269753A CN202011149803.5A CN202011149803A CN112269753A CN 112269753 A CN112269753 A CN 112269753A CN 202011149803 A CN202011149803 A CN 202011149803A CN 112269753 A CN112269753 A CN 112269753A
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- 238000007726 management method Methods 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 claims abstract description 21
- 238000012544 monitoring process Methods 0.000 claims abstract description 17
- 230000008439 repair process Effects 0.000 claims abstract description 12
- 238000004891 communication Methods 0.000 claims abstract description 5
- 230000008569 process Effects 0.000 claims description 13
- 238000004590 computer program Methods 0.000 claims description 11
- 238000003780 insertion Methods 0.000 claims description 3
- 230000037431 insertion Effects 0.000 claims description 3
- 230000001960 triggered effect Effects 0.000 claims description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 230000009471 action Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000011084 recovery Methods 0.000 description 2
- 238000012549 training Methods 0.000 description 2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
Abstract
The application discloses a PCIE link management method, which is applied to PCIE SW drive of a host end, and comprises the steps of negotiating that the PCIE link rate is x4 when cables are inserted into a JBOF end and the host end; acquiring PCIE link information in a x4 communication state, wherein the PCIE link information comprises an in-place state of a cable at an host end, an in-place state of a cable at a JBOF end, PCIE impedance and PCIE bandwidth; judging whether each cable is in place or not according to all in-place states; and if so, executing repair operation to renegotiate the PCIE link rate as a preset rate, and monitoring faults according to the PCIE impedance and the PCIE bandwidth. The method and the device can prevent the link jitter problem caused by frequent links, and improve the safety and reliability of the PCIE link. The application also discloses a PCIE link management system, a PCIE link management device and a computer readable storage medium, which have the beneficial effects.
Description
Technical Field
The present application relates to the field of storage systems, and in particular, to a PCIE link management method, system, and related components.
Background
In view Of the fact that JBOF (Just a Bunch Of Flash, full Flash memory array) is widely popularized and applied, in order to solve the problem Of connection between JBOF and a host, host-side PCIE (Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard) Switch is generally adopted, JBOF is connected through miniSAS cable to support dynamic hot plug and hot plug, a single miniSAS cable can only provide x4 bandwidth, and in order to exert JBOF performance, x16 bandwidth is often required, so 4 miniSAS cables are generally adopted to connect JBOF and the host. Considering that miniSAS PCIE cannot be inserted simultaneously, it is necessary to repeatedly enable the PCIE Switch port to negotiate a link rate of x16 bandwidth, and if frequent links are not inserted at the JBOF end, link jitter may be caused.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The application aims to provide a PCIE link management method, a system, a device and a computer readable storage medium, which can prevent the link jitter problem caused by frequent links and improve the safety and reliability of the PCIE link.
In order to solve the above technical problem, the present application provides a PCIE link management method, which is applied to a PCIE SW driver at an host side, and the PCIE link management method includes:
when the JBOF end and the host end are plugged with cables, negotiating that the PCIE link rate is x 4;
acquiring PCIE link information in a x4 communication state, wherein the PCIE link information comprises PCIE impedance, PCIE bandwidth, an in-place state of a cable at the host end and an in-place state of a cable at the JBOF end;
judging whether each cable is in place or not according to all the in-place states;
and if so, executing repair operation to renegotiate the PCIE link rate as a preset rate, and monitoring faults according to the PCIE impedance and the PCIE bandwidth.
Preferably, the process of acquiring the in-place state of the cable at the host end includes:
acquiring the in-place state of the cable at the host end by polling;
correspondingly, the process of acquiring the in-place state of the cable at the JBOF end includes:
and acquiring the in-place state of the cable at the JBOF end by polling.
Preferably, the process of acquiring the PCIE impedance and the PCIE bandwidth includes:
and acquiring the PCIE impedance and the PCIE bandwidth by reading the value of the register corresponding to the host terminal.
Preferably, the PCIE link management method further includes:
and recording log information corresponding to all the in-place states, the PCIE impedances and the PCIE bandwidths respectively.
Preferably, the cable is a miniSAS cable.
Preferably, the repair operation comprises:
and firstly controlling the downlink port of the host end to be in an invalid state, and then controlling the downlink port of the host end to be in an enabling state.
In order to solve the above technical problem, the present application further provides a PCIE link management system, which is applied to a PCIE SW drive at an host side, and the PCIE link management system includes:
the negotiation module is used for negotiating that the PCIE link rate is x4 when the JBOF end and the host end have cable insertion; the device is also used for executing repair operation to renegotiate PCIE link rate as a preset rate when each cable is in place;
an obtaining module, configured to obtain PCIE link information in an x4 link state, where the PCIE link information includes PCIE impedance, PCIE bandwidth, an in-place state of a cable at the host end, and an in-place state of a cable at the JBOF end;
the judging module is used for judging whether each cable is in place or not according to all the in-place states, and if so, the negotiation module and the fault monitoring module are triggered;
and the fault monitoring module is used for monitoring faults according to the PCIE impedance and the PCIE bandwidth.
Preferably, the PCIE link management system further includes:
and the recording module is used for recording log information corresponding to all the in-place states, the PCIE impedances and the PCIE bandwidths respectively.
In order to solve the above technical problem, the present application further provides a PCIE link management apparatus, including:
a memory for storing a computer program;
a first driver device disposed at a host end, configured to implement, when executing the computer program, the step of implementing the PCIE link management method according to any one of the foregoing descriptions;
the JBOF firmware is used for acquiring the in-place state of a cable at the JBOF end;
and the second driving device is arranged at the JBOF end and is used for inquiring the in-place state of the cable at the JBOF end.
To solve the above technical problem, the present application further provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the steps of the PCIE link management method according to any one of the above are implemented.
The application provides a PCIE link management method, when a user inserts cables at a host end and a JBOF end, the PCIE link rate is firstly negotiated to be x4, PCIE link information is obtained under the condition of x4 communication through PCIE characteristics, whether both ends of the cables are inserted well or not is judged according to the in-place states of both ends of the cables in the PCIE link information, link negotiation of preset rates is carried out after all the ends of the cables are inserted well, the problem of link jitter caused by frequent links under the condition that whether the JBOF end is inserted well or not is prevented, and the safety and the reliability of a PCIE link are improved. In addition, fault monitoring is carried out through PCIE impedance and PCIE bandwidth, so that cable fault positioning is facilitated, and maintainability is achieved. The application also provides a PCIE link management system, a PCIE link management device and a computer readable storage medium, and the PCIE link management method has the same beneficial effects as the PCIE link management method.
Drawings
In order to more clearly illustrate the embodiments of the present application, the drawings needed for the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a flowchart illustrating steps of a PCIE link management method provided in the present application;
fig. 2 is a schematic diagram illustrating a rate negotiation of a PCIE state machine according to the present application;
fig. 3 is a schematic structural diagram of a PCIE link management system provided in the present application;
fig. 4 is a schematic structural diagram of a PCIE link management device provided in the present application.
Detailed Description
The core of the application is to provide a PCIE link management method, a system, a device and a computer readable storage medium, which can prevent the link jitter problem caused by frequent links and improve the security and reliability of the PCIE link.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a flowchart illustrating a step of a PCIE link management method provided in the present application, and the method is applied to a PCIE SW driver at a host, and the PCIE link management method includes:
s101: when cables are inserted into the JBOF end and the host end, negotiating that the PCIE link rate is x 4;
s102: acquiring PCIE link information in a x4 communication state, wherein the PCIE link information comprises PCIE impedance, PCIE bandwidth, an in-place state of a cable at a host end and an in-place state of a cable at a JBOF end;
specifically, when a user inserts 4 minssas cables, it is considered that four minssas cables cannot be inserted simultaneously, and therefore, when it is detected that an minssas cable is inserted for the first time, a PCIE SW driver at a host end first negotiates a PCIE link rate as X4, where the PCIE SW specifically indicates PCIE SWITCH, and through PCIE characteristics, under the condition of X4 connectivity, the in-place states of two ends of each cable are obtained, specifically, the in-place states of the cables at the JBOF end can be obtained through the PCIE SW driver at the JBOF end, the in-place states of the cables at the host end are detected by the PCIE SW driver at the host end, and simultaneously the in-place states of the cables at the JBOF end are read, and meanwhile, PCIE impedance and PCIE bandwidth of a current PCIE link are obtained, where the in-place states are used as basis of rate negotiation, and the PCIE impedance and PCIE bandwidth are used as basis of fault monitoring.
As a preferred embodiment, the PCIE SW driver at the host side may acquire the on-site state of the cable at the host side in a polling manner; correspondingly, the PCIE SW driver at the JBOF end may obtain the in-place state of the cable at the JBOF end in a polling manner. As a preferred embodiment, the PCIE impedance and the PCIE bandwidth may be obtained by reading a value of a register corresponding to the host side.
Wherein, the cable may be a miniSAS cable.
S103: judging whether each cable is in place according to all in-place states, if so, executing S104;
s104: and executing repair operation to renegotiate the PCIE link rate as a preset rate, and monitoring faults according to the PCIE impedance and the PCIE bandwidth.
Specifically, when all the in-place states are normal, a repair operation is performed to renegotiate the PCIE link rate as a preset rate, where the preset rate may be x16, and the preset rate is determined according to actual engineering needs, which is not specifically limited herein.
It can be understood that, when the JBOF terminal and the host terminal are normally connected, but the PCIE impedance is 0, it indicates that there is a failure in the PCIE link. Of course, the determination condition of the fault may be determined according to the actual engineering requirement, and the application is not limited herein.
As a preferred embodiment, the repair operation comprises:
the method comprises the steps of firstly controlling a downlink port of a host end to be in an invalid state, and then controlling the downlink port of the host end to be in an enabling state.
Specifically, the rate negotiation of the PCIE is generally implemented by a state machine, and as shown in fig. 2, fig. 2 is a schematic diagram of the rate negotiation of the PCIE state machine according to the embodiment of the present application.
PCIE link training is related:
the normal PCIE link training state conversion process is that Detect- > Polling- > Configuration- > L0.L0 is the power state of the PCIE link which can work normally in sequence.
PCIE link retraining correlation:
this state is also called Recovery, Recovery is a very important link state, and there are many factors entering this state, such as a change in power state, a change in PCIE link rate, and the like.
As a preferred embodiment, the PCIE link management method further includes:
and recording log information corresponding to all in-place states, PCIE impedance and PCIE bandwidth respectively.
Specifically, the SW drive of the host end records the in-place state of the miniSAS cable and the in-place state of the JBOF end, impedance and other log information, so that the problem of positioning after a fault is facilitated, and maintainability is realized.
It can be seen that, in this embodiment, when a user inserts a cable at a host end and a JBOF end, a PCIE link rate is first negotiated to be x4, PCIE link information is obtained through PCIE characteristics under the condition of x4 link, whether both ends of the cable are inserted well is determined according to an in-place state of both ends of the cable in the PCIE link information, and then link negotiation of a preset rate is performed after all the ends are inserted, so that a link jitter problem caused by frequent links without knowing whether the JBOF end is inserted well is prevented, and the security and reliability of a PCIE link are improved. In addition, fault monitoring is carried out through PCIE impedance and PCIE bandwidth, so that cable fault positioning is facilitated, and maintainability is achieved.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a PCIE link management system provided in the present application, and the PCIE link management system is applied to a PCIE SW driver at a host side, and the PCIE link management system includes:
the negotiation module 11 is configured to negotiate that a PCIE link rate is x4 when the JBOF end and the host end have cable insertions; the method is also used for executing repair operation to renegotiate PCIE link rate as a preset rate when each cable is in place;
the acquiring module 12 is configured to acquire PCIE link information in an x4 link state, where the PCIE link information includes PCIE impedance, PCIE bandwidth, an in-place state of a cable at a host end, and an in-place state of a cable at a JBOF end;
the judging module 13 is used for judging whether each cable is in place according to all in-place states, and if so, the negotiation module 11 and the fault monitoring module 14 are triggered;
and the fault monitoring module 14 is configured to perform fault monitoring according to the PCIE impedance and the PCIE bandwidth.
It can be seen that, in this embodiment, when a user inserts a cable at a host end and a JBOF end, a PCIE link rate is first negotiated to be x4, PCIE link information is obtained through PCIE characteristics under the condition of x4 link, whether both ends of the cable are inserted well is determined according to an in-place state of both ends of the cable in the PCIE link information, and then link negotiation of a preset rate is performed after all the ends are inserted, so that a link jitter problem caused by frequent links without knowing whether the JBOF end is inserted well is prevented, and the security and reliability of a PCIE link are improved. In addition, fault monitoring is carried out through PCIE impedance and PCIE bandwidth, so that cable fault positioning is facilitated, and maintainability is achieved.
As a preferred embodiment, the PCIE link management system further includes:
and the recording module is used for recording log information corresponding to all in-place states, PCIE impedance and PCIE bandwidth.
As a preferred embodiment, the process of acquiring the in-place state of the cable at the host end includes:
acquiring the in-place state of a cable at the host end by polling;
correspondingly, the process of acquiring the in-place state of the cable at the JBOF end comprises the following steps:
and acquiring the in-place state of the cable at the JBOF end by polling.
As a preferred embodiment, the process of acquiring PCIE impedance and PCIE bandwidth includes:
and acquiring the PCIE impedance and the PCIE bandwidth by reading the value of the register corresponding to the host terminal.
As a preferred embodiment, the cable is a miniSAS cable.
As a preferred embodiment, the repair operation comprises:
the method comprises the steps of firstly controlling a downlink port of a host end to be in an invalid state, and then controlling the downlink port of the host end to be in an enabling state.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a PCIE link management device provided in the present application, where the PCIE link management device includes:
a memory 21 for storing a computer program;
a first driver device 22 disposed at the host end, configured to implement the steps of the PCIE link management method as described in any one of the above when executing a computer program;
the JBOF firmware 23 is used for acquiring the in-place state of a cable at the JBOF end;
and the second driving device 24 is arranged at the JBOF end and is used for inquiring the in-place state of the cable at the JBOF end.
Please refer to the above embodiments for the introduction of the PCIE link management apparatus provided in the present application, which is not described herein again.
The PCIE link management device provided by the application has the same beneficial effects as the PCIE link management method.
To solve the above technical problem, the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the PCIE link management method as in any one of the above are implemented.
For the introduction of a computer-readable storage medium provided in the present application, please refer to the above embodiments, which are not described herein again.
The computer-readable storage medium provided by the application has the same beneficial effects as the PCIE link management method.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A PCIE link management method is characterized in that the PCIE link management method is applied to a PCIE SW drive of a host end, and comprises the following steps:
when the JBOF end and the host end are plugged with cables, negotiating that the PCIE link rate is x 4;
acquiring PCIE link information in a x4 communication state, wherein the PCIE link information comprises PCIE impedance, PCIE bandwidth, an in-place state of a cable at the host end and an in-place state of a cable at the JBOF end;
judging whether each cable is in place or not according to all the in-place states;
and if so, executing repair operation to renegotiate the PCIE link rate as a preset rate, and monitoring faults according to the PCIE impedance and the PCIE bandwidth.
2. The PCIE link management method according to claim 1, wherein the process of acquiring the in-place state of the cable at the host end comprises:
acquiring the in-place state of the cable at the host end by polling;
correspondingly, the process of acquiring the in-place state of the cable at the JBOF end includes:
and acquiring the in-place state of the cable at the JBOF end by polling.
3. The PCIE link management method of claim 1, wherein the process of obtaining PCIE impedance and PCIE bandwidth comprises:
and acquiring the PCIE impedance and the PCIE bandwidth by reading the value of the register corresponding to the host terminal.
4. The PCIE link management method of claim 1, wherein the PCIE link management method further comprises:
and recording log information corresponding to all the in-place states, the PCIE impedances and the PCIE bandwidths respectively.
5. The PCIE link management method of claim 1, wherein the cable is a miniSAS cable.
6. The PCIE link management method of any one of claims 1-5, wherein the repair operation includes:
and firstly controlling the downlink port of the host end to be in an invalid state, and then controlling the downlink port of the host end to be in an enabling state.
7. A PCIE link management system is characterized in that the PCIE link management system is applied to a PCIE SW driver at a host end and comprises:
the negotiation module is used for negotiating that the PCIE link rate is x4 when the JBOF end and the host end have cable insertion; the device is also used for executing repair operation to renegotiate PCIE link rate as a preset rate when each cable is in place;
an obtaining module, configured to obtain PCIE link information in an x4 link state, where the PCIE link information includes PCIE impedance, PCIE bandwidth, an in-place state of a cable at the host end, and an in-place state of a cable at the JBOF end;
the judging module is used for judging whether each cable is in place or not according to all the in-place states, and if so, the negotiation module and the fault monitoring module are triggered;
and the fault monitoring module is used for monitoring faults according to the PCIE impedance and the PCIE bandwidth.
8. The PCIE link management system of claim 7, further comprising:
and the recording module is used for recording log information corresponding to all the in-place states, the PCIE impedances and the PCIE bandwidths respectively.
9. A PCIE link management apparatus, comprising:
a memory for storing a computer program;
a first driver device disposed at a host end, configured to implement the steps of the PCIE link management method according to any one of claims 1 to 6 when executing the computer program;
the JBOF firmware is used for acquiring the in-place state of a cable at the JBOF end;
and the second driving device is arranged at the JBOF end and is used for inquiring the in-place state of the cable at the JBOF end.
10. A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the steps of a PCIE link management method as recited in any one of claims 1-6.
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| CN111490904A (en) * | 2020-04-22 | 2020-08-04 | 北京星网锐捷网络技术有限公司 | Uplink bandwidth allocation method, device, medium and equipment |
| CN111722966A (en) * | 2020-06-19 | 2020-09-29 | 广东浪潮大数据研究有限公司 | PCIe Switch detection method, system, device and medium |
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2020
- 2020-10-23 CN CN202011149803.5A patent/CN112269753A/en active Pending
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| TW200803299A (en) * | 2006-02-13 | 2008-01-01 | Teranetics Inc | Auto-sequencing transmission speed of a data port |
| CN101958888A (en) * | 2010-05-21 | 2011-01-26 | 福建星网锐捷网络有限公司 | Configuration method of port negotiation capacity, communication port and communication device |
| CN110399027A (en) * | 2019-07-19 | 2019-11-01 | 苏州浪潮智能科技有限公司 | A kind of reset circuit |
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