CN111443788B - Power-on control circuit of MPSOC (Multi-processor System on chip) - Google Patents
Power-on control circuit of MPSOC (Multi-processor System on chip) Download PDFInfo
- Publication number
- CN111443788B CN111443788B CN202010221010.3A CN202010221010A CN111443788B CN 111443788 B CN111443788 B CN 111443788B CN 202010221010 A CN202010221010 A CN 202010221010A CN 111443788 B CN111443788 B CN 111443788B
- Authority
- CN
- China
- Prior art keywords
- chip
- output end
- level
- voltage
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/263—Arrangements for using multiple switchable power supplies, e.g. battery and AC
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
- Power Sources (AREA)
Abstract
The invention relates to a power-on control circuit of a multiprocessor system-on-chip MPSOC, which comprises: a delay control sub-circuit and a voltage integral control sub-circuit; when the MPSOC is electrified, enabling input signals to be converted into a second level from a first level, converting output signals of an OR gate into the second level from the first level, and converting output signals of ports of a first output end, a second output end and a third output end of a first time sequence control chip into the second level from the first level after delaying for a plurality of preset clock cycles; the output signal of the AND gate is inverted from a first level to a second level according to the signal of the port output signal of the third output end of the first time sequence control chip; the output signals of the ports of the first output end, the second output end and the third output end of the second time sequence control chip are sequentially converted into a second level from the first level after delaying for a plurality of preset clock cycles; when the integrated voltage of the voltage integration circuit reaches a set voltage threshold value, the voltage judgment delay chip outputs a second level signal.
Description
Technical Field
The invention relates to the technical field of electronics, in particular to a power-on control circuit of a multi-processor system-on-chip (MPSOC).
Background
With the development of electronic technology, a conventional Processor cannot rapidly process increasing data, and a Multi Processor System On Chip (MPSOC) developed nowadays can be implemented, but the power-on timing of the MPSOC has a requirement.
The improper power-on time sequence can cause the chip to fail to work normally and even burn out. The power-on starting process is a stage with higher power failure rate, and has larger influence on the quality and reliability of electronic products. For example, in a Light Emitting Diode (LED) display screen, each power-on module of the display screen is powered on at the same time, which easily causes an excessive impact current of the power-on module and a black screen of the display screen, thereby affecting the reliability of the product.
At present, the following methods are mainly used for controlling the power-on sequence: (1) and a PG pin of the power supply chip is adopted for cascade control. Although the cost is low, the timing cannot be controlled, and the delay time of the PG pin is not controllable according to the process correlation of the chip. (2) The control is performed by using a Complex Programmable Logic Device (CPLD). Different delays can be output through programs, delay control is accurate, but whether each path of power supply outputs normally or not cannot be judged, and the output time of each path of power supply cannot be detected. (3) And a singlechip is adopted for control. The output voltage of each power supply is acquired by using the pins, and after the output voltage meets the index, the power supply is delayed for a long time through program control and then the power supply is enabled for the next stage. (4) And a time sequence chip is adopted for control. The number of output circuits is limited, and whether each path of power output is normal cannot be detected.
Disclosure of Invention
The invention aims to provide a power-on control circuit of an MPSOC (multi-processor system on chip), aiming at the defects of the prior art, and the MPSOC can be normally powered on to work by forming a time sequence circuit by a time sequence control chip cascade and a gate circuit.
In order to achieve the above object, the present invention provides a power-on control circuit of an MPSOC, the power-on control circuit comprising: a delay control sub-circuit and a voltage integral control sub-circuit;
the delay control sub-circuit comprises: the system comprises an OR gate, an AND gate and two time sequence control chips; the two time sequence control chips are respectively a first time sequence control chip and a second time sequence control chip;
the time sequence control chip is provided with an enabling signal input end, a first output end, a second output end and a third output end;
a first input end of the OR gate is connected with an enabling input signal, a second input end of the OR gate is connected with a first output end of the second time sequence control chip, and an output end of the OR gate is connected with an enabling signal input end of the first time sequence control chip;
the first input end of the AND gate is connected with the enabling input signal, the second input end of the AND gate is connected with the third output end of the first time sequence control chip, and the output end of the AND gate is connected with the enabling signal input end of the second time sequence control chip;
when the MPSOC is powered on, the enabling input signal is converted into a second level from a first level, the output signal of the OR gate is converted into the second level from the first level, and the first level is converted into the second level from the first level after the output signals of the first output end, the second output end and the third output end of the first time sequence control chip are sequentially delayed for a plurality of preset clock cycles;
the output signal of the AND gate is inverted from a first level to a second level according to the signal of the port output signal of the third output end of the first time sequence control chip; the output signals of the ports of the first output end, the second output end and the third output end of the second time sequence control chip are sequentially converted into a second level from a first level after delaying for a plurality of preset clock cycles;
the voltage integral control sub-circuit comprises: the voltage integrating circuit and the voltage judging delay chip;
the signal input end of the voltage judgment delay chip is connected with the third output end of the second time sequence control chip, the voltage integration signal port of the voltage judgment delay chip is connected with the voltage integration circuit, and the output end of the voltage judgment delay chip is connected with the power-on signal input end of the MPSOC; when the port output signal of the third output end of the second time sequence control chip is inverted from a first level to a second level, the voltage integration circuit starts to carry out voltage integration; and when the integrated voltage reaches a set voltage threshold value, the output end of the voltage judgment delay chip outputs an effective second level signal for electrifying the MPSOC.
Preferably, the MPSOC comprises a plurality of input port groups corresponding to different power timing input requirements;
each input port group is connected with one of the first output end, the second output end and the third output end of the first time sequence control chip or the second time sequence control chip.
Preferably, the power-on control circuit further comprises an enable input signal generation sub-circuit; the enable input signal generation sub-circuit includes a first resistor and a first capacitor;
a first end of the first resistor is connected with a power supply voltage VCC, a second end of the first resistor is connected with a first end of the first capacitor, and a second end of the first capacitor is grounded; the second end of the first resistor is further connected with the first input end of the or gate and the first input end of the and gate, and is used for outputting the enable input signal.
Preferably, the voltage integration circuit is specifically a second capacitor;
one end of the second capacitor is grounded, and the other end of the second capacitor is connected with a voltage integral signal port of the voltage judgment delay chip.
Further preferably, the charging time of the second capacitor is greater than 6 times the plurality of preset clock cycles.
Preferably, the delay control sub-circuit further comprises a pull-up resistor and a pull-down resistor;
the first output end, the second output end and the third output end are respectively connected with the pull-up resistor and the pull-down resistor.
Preferably, the output end of the voltage judging delay chip is also connected with a pull-up resistor.
Preferably, the first timing control chip and the second timing control chip are LM 3880; the voltage judgment delay chip is a TPS 3890.
The power-on control circuit of the MPSOC on the multiprocessor chip, provided by the embodiment of the invention, is a time sequence control circuit formed by cascading time sequence control chips and gate circuits, and has the advantages of simple structure, flexible control and stable time sequence, so that the MPSOC on the multiprocessor chip can be normally powered on to work.
Drawings
Fig. 1 is a logic diagram of a delay control sub-circuit of a power-on control circuit of a multi-processor system-on-chip MPSOC according to an embodiment of the present invention;
fig. 2 is a delay control sub-circuit diagram of a power-on control circuit of an MPSOC of a multiprocessor system on a chip according to an embodiment of the present invention;
fig. 3 is a timing diagram of a power-up control circuit of an MPSOC according to an embodiment of the present invention;
fig. 4 is a voltage integration control sub-circuit diagram of a power-on control circuit of the multi-processor system-on-chip MPSOC according to an embodiment of the present invention.
Detailed Description
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
The power-on control circuit of the MPSOC of the multiprocessor system-on-chip provided by the invention is characterized in that a time sequence control circuit is formed by the cascade connection of time sequence control chips and a gate circuit, and the time sequence control circuit has the advantages of simple structure, flexible control and stable time sequence, so that the MPSOC of the multiprocessor system-on-chip can be normally powered on to work.
The invention provides a power-on control circuit of a multiprocessor system-on-chip MPSOC, which comprises: a delay control sub-circuit and a voltage integral control sub-circuit.
Fig. 1, fig. 2, fig. 3, and fig. 4 are a logic diagram, a delay control sub-circuit diagram, a timing diagram, and a voltage integration control sub-circuit diagram of a delay control sub-circuit of a power-on control circuit of a multiprocessor system on a chip (MPSOC) according to an embodiment of the present invention. The technical scheme of the invention is detailed in the following by combining figures 1-4.
First, a circuit configuration and circuit logic of the delay control sub-circuit are explained.
As shown in fig. 1, the delay control sub-circuit includes: an OR gate 1, an AND gate 2 and two time sequence control chips. The two timing control chips are a first timing control chip 31 and a second timing control chip 32, respectively. The first timing control chip 31 has an enable signal input terminal EN1, a first output terminal a, a second output terminal B, and a third output terminal C. The second timing control chip 32 has an enable signal input terminal EN2, a first output terminal D, a second output terminal E, and a third output terminal F.
The first input terminal of the or gate 1 is connected to the enable input signal Sig EN, the second input terminal of the or gate 1 is connected to the first output terminal D of the second timing control chip 32, and the output terminal of the or gate 1 is connected to the enable signal input terminal EN1 of the first timing control chip 31. The first input end of the and gate 2 is connected to the enable input signal Sig EN, the second input end of the and gate 2 is connected to the third output end C of the first timing control chip 31, and the output end of the and gate 2 is connected to the enable signal input end EN2 of the second timing control chip 32.
The enable input signal Sig EN may be generated by the enable input signal generating sub-circuit 100. In the particular circuit shown in fig. 2, the power-up control circuit further includes an enable input signal generation sub-circuit 100. The enable input signal generating sub-circuit 100 includes a first resistor R74 and a first capacitor C418. A first terminal of the first resistor R74 is connected to the supply voltage VCC, a second terminal of the first resistor R74 is connected to a first terminal of the first capacitor C418, and a second terminal of the first capacitor C418 is grounded GND. The second terminal of the first resistor R74 is further connected to a first input terminal of the or gate 1 and a first input terminal of the and gate 2 for outputting an enable input signal Sig EN.
The delay control sub-circuit 200 is used for outputting different timing signals through the timing control chip. The first timing control chip 31 and the second timing control chip 32 preferably employ LM 3880.
The delay control sub-circuit 200 further includes a pull-up resistor and a pull-down resistor connected to the rear stage of the two sequential control chips for dividing the voltage to generate a suitable level for enabling the rear stage. Specifically, a first output end, a second output end and a third output end of the two sequential control chips are respectively connected with a pull-up resistor and a pull-down resistor. The first output end a of the first timing control chip 31 is connected with a pull-up resistor R75 and a pull-down resistor R262, the second output end B is connected with a pull-up resistor R76 and a pull-down resistor R263, and the third output end C is connected with a pull-up resistor R77 and a pull-down resistor R264. The first output end D of the second timing control chip 32 is connected to a pull-up resistor R78 and a pull-down resistor R265, the second output end E is connected to a pull-up resistor R79 and a pull-down resistor R266, and the third output end F is connected to a pull-up resistor R80 and a pull-down resistor R267.
When the MPSOC is powered on, the enable input signal Sig EN goes from low to high. The output signal of the or gate 1 is inverted from a low level to a high level, and the output signals of the first output terminal a, the second output terminal B, and the third output terminal C of the first timing control chip 31 are sequentially inverted from the low level to the high level after delaying for a plurality of preset clock cycles. The output signal of the and gate 2 is inverted from low level to high level according to the signal of the port output signal of the third output terminal C of the first timing control chip 31. The output signals of the first output end D, the second output end E, and the third output end F of the second timing control chip 32 are sequentially inverted from a low level to a high level after delaying for a plurality of preset clock cycles. The plurality of preset clock cycles refer to the delay time of the timing control chip, and the length of the delay time can be changed through setting.
In a specific embodiment, as shown in fig. 2, when the MPSOC is powered on, the enable input signal Sig _ EN is inverted to a high level, and the or gate 1 outputs a high level signal, so that the first timing chip 31 is triggered by the enable input signal Sig EN, a first timer in the first timing chip 31 starts timing, and when the timing reaches a clock cycle number corresponding to a set delay time, for example, 10ms, a first FLAG1 of the first timing chip 31 is inverted from a low level to a high level, and a second timer in the first timing chip 31 starts timing; when the second timer reaches 10ms, the second FLAG2 is turned from low level to high level, and the third timer in the first timing chip 31 starts timing; when the third timer counts for 10ms, the third FLAG3 toggles from low to high.
And gate 2 ensures that FLAG1 of second timing chip 32 is not pulled high before FLAG3 of first timing chip 31 is pulled high. The power-on sequence of the three flag bits of the second timing chip 32 is consistent with the power-on sequence of the three flag bits of the first timing chip 31, and details are not repeated here. Therefore, the delay control sub-circuit 200 is powered up according to the sequence of the first FLAG1, the second FLAG2, the third FLAG3 of the first timing chip 31, the first FLAG1, the second FLAG2, and the third FLAG3 of the second timing chip 32.
When the MPSOC is powered on, the output signal timing sequence of the delay control sub-circuit 200 is shown in fig. 3, where t is the delay time.
When the power is down, the power-down sequence is the same as the power-up sequence, but the order is opposite, that is, when the power is down, the power is down according to the order of the third FLAG3, the second FLAG2, the first FLAG1, the third FLAG3, the second FLAG2 and the first FLAG1 of the second timing chip 32.
The circuit configuration and circuit logic of the voltage integral control sub-circuit are explained below.
As shown in fig. 4, the voltage integral control sub-circuit includes: a voltage integrating circuit 300 and a voltage judging delay chip 4. The signal input terminal SENSE of the voltage determination delay chip 4 is connected to the third output terminal F of the second timing control chip 32, the voltage integration signal port CT of the voltage determination delay chip 4 is connected to the voltage integration circuit 300, and the output terminal RESTN of the voltage determination delay chip is connected to the power-on signal input terminal PS _ POR _ B of the MPSOC.
In the practical circuit of the present invention, the voltage integrating circuit 300 is specifically implemented by using the second capacitor C422. One end of the second capacitor C422 is grounded GND, and the other end is connected to the voltage integration signal port CT of the voltage determination delay chip 4. The charging time of the second capacitor C422 is greater than 6 times the preset clock period. The voltage determination delay chip 4 is preferably a TPS 3890. The output end of the voltage judging delay chip 4 is connected with a pull-up resistor R81.
The voltage integration circuit starts voltage integration when the port output signal of the third output terminal C of the second timing control chip 32 is inverted from a low level to a high level. When the integrated voltage reaches a set voltage threshold, the output terminal RESTN of the voltage determination delay chip is connected to the PS _ POR _ B pin of the MPSOC, and outputs an active high level signal for powering up the MPSOC to the PS _ POR _ B pin.
In a particular embodiment, the MPSOC includes a plurality of input port sets corresponding to different power timing input requirements. Each input port group is connected to one of the first output port, the second output port, and the third output port of the first timing control chip 31 or the second timing control chip 32.
MPSOC is divided into an SOC end and an FPGA end, wherein the SOC end is called as PS end for short, and the FPGA end is called as PL end for short. The PS terminal and the PL terminal are independent, the principle that external power supply is also isolated is adopted during design, and the power supply can be shared later for simplifying the cost. The PS _ POR _ B pin of the MPSOC must be switched to a high level after the power-up of the PS and PL terminals is completed, and the power-up process of the PS and PL terminals must be kept at a low level.
The power-on requirement of the PS terminal is divided into 6 steps, and the power-on requirement of the PL terminal is divided into 3 steps. Therefore, in this embodiment, the pins of the MPSOC are divided into 6 groups according to the power-up requirement of the MPSOC, and each group may only include the port of the PL terminal or the port of the PS terminal or may include both the ports of the PS terminal and the PL terminal, so as to perform 6-step power-up. Each group is connected to one of the first output terminal, the second output terminal, and the third output terminal of the first timing control chip 31 or the second timing control chip 32.
The SENSE pin of the voltage determination delay chip of fig. 4 is connected to the third output terminal F, i.e., FLAG3, of the second time control chip 32 of fig. 3. After the power-on of the PS end and the PL end of the MPSOC is finished, namely after the FLAG3 is converted into a high level, the voltage integrating circuit of the voltage judgment delay chip starts to carry out voltage integration, and when the voltage of the PS _ POR _ B is larger than a set voltage threshold value, the PS _ POR _ B is turned over from the low level to the high level, so that the MPSOC is successfully powered on to work.
The power-on control circuit of the MPSOC of the multiprocessor system-on-chip provided by the invention is characterized in that a time sequence control circuit is formed by the cascade connection of time sequence control chips and a gate circuit, and the time sequence control circuit has the advantages of simple structure, flexible control and stable time sequence, so that the MPSOC of the multiprocessor system-on-chip can be normally powered on to work.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A power-on control circuit of a multiprocessor system-on-chip MPSOC, characterized in that the power-on control circuit comprises: a delay control sub-circuit and a voltage integral control sub-circuit;
the delay control sub-circuit comprises: the system comprises an OR gate, an AND gate and two time sequence control chips; the two time sequence control chips are respectively a first time sequence control chip and a second time sequence control chip;
the time sequence control chip is provided with an enabling signal input end, a first output end, a second output end and a third output end;
a first input end of the OR gate is connected with an enabling input signal, a second input end of the OR gate is connected with a first output end of the second time sequence control chip, and an output end of the OR gate is connected with an enabling signal input end of the first time sequence control chip;
the first input end of the AND gate is connected with the enabling input signal, the second input end of the AND gate is connected with the third output end of the first time sequence control chip, and the output end of the AND gate is connected with the enabling signal input end of the second time sequence control chip;
when the MPSOC is powered on, the enabling input signal is converted into a second level from a first level, the output signal of the OR gate is converted into the second level from the first level, and the first level is converted into the second level from the first level after the output signals of the first output end, the second output end and the third output end of the first time sequence control chip are sequentially delayed for a plurality of preset clock cycles;
the output signal of the AND gate is inverted from a first level to a second level according to the signal of the port output signal of the third output end of the first time sequence control chip; the output signals of the ports of the first output end, the second output end and the third output end of the second time sequence control chip are sequentially converted into a second level from a first level after delaying for a plurality of preset clock cycles;
the voltage integral control sub-circuit comprises: the voltage integrating circuit and the voltage judging delay chip;
the signal input end of the voltage judgment delay chip is connected with the third output end of the second time sequence control chip, the voltage integration signal port of the voltage judgment delay chip is connected with the voltage integration circuit, and the output end of the voltage judgment delay chip is connected with the power-on signal input end of the MPSOC; when the port output signal of the third output end of the second time sequence control chip is inverted from a first level to a second level, the voltage integration circuit starts to carry out voltage integration; and when the integrated voltage reaches a set voltage threshold value, the output end of the voltage judgment delay chip outputs an effective second level signal for electrifying the MPSOC.
2. The power-on control circuit of a multiprocessor system-on-chip MPSOC of claim 1, wherein the MPSOC comprises a plurality of input port sets corresponding to different power timing input requirements;
each input port group is connected with one of the first output end, the second output end and the third output end of the first time sequence control chip or the second time sequence control chip.
3. The power-on control circuit of the MPSOC of claim 1, further comprising an enable input signal generation sub-circuit; the enable input signal generation sub-circuit includes a first resistor and a first capacitor;
a first end of the first resistor is connected with a power supply voltage VCC, a second end of the first resistor is connected with a first end of the first capacitor, and a second end of the first capacitor is grounded; the second end of the first resistor is further connected with the first input end of the or gate and the first input end of the and gate, and is used for outputting the enable input signal.
4. The power-on control circuit of the MPSOC as claimed in claim 1, wherein the voltage integration circuit is a second capacitor;
one end of the second capacitor is grounded, and the other end of the second capacitor is connected with a voltage integral signal port of the voltage judgment delay chip.
5. The power-on control circuit of the MPSOC of claim 4, wherein the charging time of the second capacitor is greater than 6 times the plurality of preset clock cycles.
6. The power-on control circuit of the MPSOC of the multi-processor system on a chip as claimed in claim 1, wherein the delay control sub-circuit further comprises a pull-up resistor and a pull-down resistor;
the first output end, the second output end and the third output end are respectively connected with the pull-up resistor and the pull-down resistor.
7. The power-on control circuit of the MPSOC as claimed in claim 1, wherein the output terminal of the voltage determination delay chip is further connected with a pull-up resistor.
8. The power-on control circuit of the MPSOC as claimed in claim 1, wherein the first timing control chip and the second timing control chip are LM 3880; the voltage judgment delay chip is a TPS 3890.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010221010.3A CN111443788B (en) | 2020-03-25 | 2020-03-25 | Power-on control circuit of MPSOC (Multi-processor System on chip) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010221010.3A CN111443788B (en) | 2020-03-25 | 2020-03-25 | Power-on control circuit of MPSOC (Multi-processor System on chip) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111443788A CN111443788A (en) | 2020-07-24 |
| CN111443788B true CN111443788B (en) | 2022-02-18 |
Family
ID=71648007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010221010.3A Active CN111443788B (en) | 2020-03-25 | 2020-03-25 | Power-on control circuit of MPSOC (Multi-processor System on chip) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111443788B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114995262A (en) * | 2022-08-05 | 2022-09-02 | 成都万创科技股份有限公司 | Power supply time sequence control method and system of X86 platform |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104238627A (en) * | 2014-09-05 | 2014-12-24 | 浪潮电子信息产业股份有限公司 | Method for realizing server power-on/off sequential control by using hardware circuit |
| CN104932314A (en) * | 2015-06-16 | 2015-09-23 | 山东超越数控电子有限公司 | Simple cascade and monitoring method of a number of power supply sequencing devices |
| CN109257038A (en) * | 2018-11-28 | 2019-01-22 | 中国空空导弹研究院 | High Speed Signal Processor System has access to electricity sequential control circuit |
| CN110544328A (en) * | 2019-09-02 | 2019-12-06 | 哈尔滨工业大学 | embedded high-energy-efficiency computing platform and method for airborne fault prediction and health management |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100585105B1 (en) * | 2003-11-05 | 2006-06-01 | 삼성전자주식회사 | Timing controller for reducing memory update operation current, LCD driver having the same and method for outputting display data |
| CN102999140B (en) * | 2012-05-30 | 2015-12-09 | 国家计算机网络与信息安全管理中心 | A kind of electrifying timing sequence control system of PCIE board and method |
| US9305905B2 (en) * | 2013-09-06 | 2016-04-05 | Micron Technology, Inc. | Apparatuses and related methods for staggering power-up of a stack of semiconductor dies |
| CN206481280U (en) * | 2017-02-24 | 2017-09-08 | 厦门九华通信设备厂 | A kind of delays time to control reset circuit |
| CN108415331B (en) * | 2018-03-13 | 2021-02-09 | 北京比特大陆科技有限公司 | AI deep learning board card and power supply method thereof |
| CN208849899U (en) * | 2018-11-27 | 2019-05-10 | 北京旷视科技有限公司 | A kind of power control circuit for network video recorder |
-
2020
- 2020-03-25 CN CN202010221010.3A patent/CN111443788B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104238627A (en) * | 2014-09-05 | 2014-12-24 | 浪潮电子信息产业股份有限公司 | Method for realizing server power-on/off sequential control by using hardware circuit |
| CN104932314A (en) * | 2015-06-16 | 2015-09-23 | 山东超越数控电子有限公司 | Simple cascade and monitoring method of a number of power supply sequencing devices |
| CN109257038A (en) * | 2018-11-28 | 2019-01-22 | 中国空空导弹研究院 | High Speed Signal Processor System has access to electricity sequential control circuit |
| CN110544328A (en) * | 2019-09-02 | 2019-12-06 | 哈尔滨工业大学 | embedded high-energy-efficiency computing platform and method for airborne fault prediction and health management |
Non-Patent Citations (3)
| Title |
|---|
| "32通道MIMO数字电路关键技术研究与验证";赵晋楠;《中国优秀硕士学位论文全文数据库 信息科技辑》;20190115;第44-49页 * |
| "High Performance CMOS Image Sensor Power Supply Solutions for Industrial Cameras or Vision Sensors";TEXAS INSTRUMENTS;《www.ti.com.cn》;20190831;第12页 * |
| "TPS3890";TEXAS INSTRUMENTS;《www.ti.com.cn》;20160531;第1页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111443788A (en) | 2020-07-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8199858B2 (en) | OOB (out of band) detection circuit and serial ATA system | |
| US7626416B2 (en) | Method and apparatus for high resolution ZQ calibration | |
| US8004911B2 (en) | Memory system, memory device, and output data strobe signal generating method | |
| CN111443788B (en) | Power-on control circuit of MPSOC (Multi-processor System on chip) | |
| CN116054798B (en) | Method and device for eliminating time sequence metastable state in multi-voltage domain power-on and power-off reset | |
| US20190341096A1 (en) | Techniques for clock signal jitter generation | |
| KR100612034B1 (en) | Test-mode entry method and test-mode entry circuit for the same | |
| US8054695B2 (en) | Semiconductor memory apparatus | |
| KR20060092313A (en) | Multi device system forming daisy chain and operating method for the same | |
| US5198709A (en) | Address transition detector circuit | |
| CN114882934B (en) | Test Circuit | |
| CN109240130B (en) | Programmable pin level control circuit | |
| US8395946B2 (en) | Data access apparatus and associated method for accessing data using internally generated clocks | |
| CN111128262B (en) | Memory circuit, circuit control method, integrated circuit device, and processor | |
| US20090326843A1 (en) | Apparatus and method for detecting temperature/voltage variation of semiconductor integrated circuit | |
| KR20170045058A (en) | Input circuit and electric apparatus including input circuit | |
| KR20120119348A (en) | Delay circuit and latency control circuit of memory and signal delay method | |
| CN105573950A (en) | Method for setting VR chip address based on gate circuit chip | |
| CN116665747A (en) | Internal data availability for system debugging | |
| US10276258B2 (en) | Memory controller for selecting read clock signal | |
| US20220294428A1 (en) | Deterministic Jitter Generator with Controllable Probability Distribution | |
| CN114758686A (en) | Position determination method, reading method, starting method, device, equipment and medium | |
| KR20180013451A (en) | Semiconductor Apparatus | |
| CN113946937A (en) | Synchronization method and simulator | |
| KR0140454B1 (en) | Semiconductor memory device for incrementing address at high speed in burst access |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220311 Address after: 401122 No.1, 1st floor, building 3, No.21 Yunzhu Road, Yubei District, Chongqing Patentee after: Chongqing landshipu Information Technology Co.,Ltd. Address before: B4-006, maker Plaza, 338 East Street, Huilongguan town, Changping District, Beijing 100096 Patentee before: Beijing Idriverplus Technology Co.,Ltd. |
|
| TR01 | Transfer of patent right |