CN208849899U - A kind of power control circuit for network video recorder - Google Patents
A kind of power control circuit for network video recorder Download PDFInfo
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- CN208849899U CN208849899U CN201821969778.3U CN201821969778U CN208849899U CN 208849899 U CN208849899 U CN 208849899U CN 201821969778 U CN201821969778 U CN 201821969778U CN 208849899 U CN208849899 U CN 208849899U
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Abstract
The utility model provides a kind of power control circuit for network video recorder.The power control circuit includes system power supply power supply, the first power supply, control module and field programmable gate array；The system power supply power supply connects the input terminal of first power supply and the first input end of the control module；The control terminal that the output end of first power supply connects the first input end of the field programmable gate array and first power supply connects the second input terminal of the control module；The output end of the control module connects the second input terminal of the field programmable gate array.The power control circuit solves the problems, such as that field programmable gate array is easy to damage by the first power supply and control module.Achieve the purpose that improve product reliability as a result,.
Description
Technical field
The utility model relates to the field network video recorder (Network Video Recorder, hereinafter referred to as NVR),
More particularly to a kind of power control circuit for NVR.
Background technique
A kind of data acquisition and recording terminal equipment of the existing NVR as field of video monitoring, more and more assumes responsibility for
Intelligent human-face analytic function.In order to meet the calculating force request of intellectual analysis, more and more NVR are used can be compiled based on scene
The scheme of journey gate array (Field-Programmable Gate Array, hereinafter referred to as FPGA).FPGA is to power-on and power-off, reset
Between sequential relationship have special requirement, need to carry out relevant control, otherwise enter solution reset state not powering on sufficiently
Or there are wafer damage risks when not entering reset state with regard to unexpected power down.
Utility model content
The utility model is proposed, in view of the above problems at least to be partially solved the above problem.
One aspect according to the present utility model provides a kind of power control circuit for NVR, including system power supply
Power supply, the first power supply, control module and field programmable gate array, wherein
The system power supply power supply connects the input terminal of first power supply and the first input end of the control module；
The output end of first power supply connects the first input end of the field programmable gate array and described first
The control terminal of power supply connects the second input terminal of the control module；
The output end of the control module connects the second input terminal of the field programmable gate array.
Illustratively, the control module include second source, processor, monitoring module and with door, wherein
The input terminal of the input terminal of the second source and the monitoring module is all connected with the system power supply power supply；
The output end of the second source connects the control of the first input end of the processor and first power supply
End connects the second input terminal of the processor；
The output end connection of the processor is described to be connected with the first input end of door and the output end of the monitoring module
Connect second input terminal with door；
Second input terminal that the field programmable gate array is connect with the output end of door.
Illustratively, the processor is Advanced RISC Machine (Advanced
RISCMachines, hereinafter referred to as ARM).
Illustratively, the monitoring module is power supply monitoring IC chip.
Illustratively, the control terminal of first power supply is POWER OK or POWER GOOD signal pins.
Illustratively, the second input terminal of the field programmable gate array is PS_POR_B pin.
Power control circuit according to the present utility model for network video recorder passes through the first power supply and control mould
Block solves the problems, such as that FPGA is easy to damage.Achieve the purpose that improve product reliability as a result,.
The above description is merely an outline of the technical solution of the present invention, in order to better understand the skill of the utility model
Art means, and being implemented in accordance with the contents of the specification, and in order to allow above and other purpose, feature of the utility model
It can be more clearly understood with advantage, it is special below to lift specific embodiment of the present utility model.
Detailed description of the invention
The utility model embodiment is described in more detail in conjunction with the accompanying drawings, the utility model above-mentioned and its
Its purpose, feature and advantage will be apparent.Attached drawing is used to provide to further understand the utility model embodiment, and
And part of specification is constituted, it is used to explain the utility model together with the utility model embodiment, not constitute to this reality
With novel limitation.In the accompanying drawings, identical reference label typically represents same parts or step.
Fig. 1 shows the schematic block diagram of the power control circuit for NVR according to the utility model one embodiment；With
And
Fig. 2 shows the schematic block diagrams according to the power control circuit for NVR of the utility model another embodiment.
Specific embodiment
In order to enable the purpose of this utility model, technical solution and advantage become apparent, retouch in detail below with reference to accompanying drawings
State example embodiment according to the present utility model.Obviously, described embodiment is only that a part of the utility model is implemented
Example, rather than the whole embodiments of the utility model, it should be appreciated that the utility model is not by the limit of example embodiment described herein
System.Based on embodiment described in the utility model, those skilled in the art institute in the case where not making the creative labor
Obtained all other embodiment should all be fallen within the protection scope of the utility model.
Fig. 1 shows the schematic frame of the power control circuit 100 for NVR according to the utility model one embodiment
Figure.
As shown in Figure 1, the power control circuit 100 for NVR includes system power supply power supply 110, the first power supply 120, control
Molding block 130 and FPGA140.
System power supply power supply 110 is responsible for powering to whole system.System power supply power supply 110 connects the defeated of the first power supply 120
Enter the first input end at end and control module 130.System power supply power supply 110 is supplied to the first power supply 120 and control module 130 respectively
Electricity.After system power supply power supply 110 powers on, the first power supply 120 and control module 130 power on simultaneously.110 power down of system power supply power supply
Afterwards, the first power supply 120 and the power down simultaneously of control module 130.
Illustratively, system power supply power supply 110 is DC12V power supply.
The control terminal connection of the first input end and the first power supply 120 of the output end connection FPGA140 of first power supply 120
Second input terminal of control module 130.First power supply 120 is used to power to FPGA140, and the first power supply 120 is also used to
Condition indicative signal PG is sent when necessary to control module 130.When the first power supply 120 powers on, FPGA140 is powered on simultaneously.
After the completion of FPGA140 is powered on, the control terminal output state indication signal PG of the first power supply 120.Condition indicative signal PG passes through
Second input terminal of control module 130 sends control module 130 to.
Illustratively, the control terminal of the first power supply 120 is POWER OK or POWER GOOD signal pins.
The first input end of control module 130 connects system power supply power supply 110, to monitor the upper of system power supply power supply 110
Electricity and/or power-down state.Second input terminal of control module 130 connects the control terminal and control module 120 of the first power supply 120
Output end connection FPGA140 the second input terminal.Control module 130 is via its second input terminal received from the first electricity as a result,
The condition indicative signal PG of the control terminal output in source 120, to export solution reset/reset instruction letter according to condition indicative signal PG
Number give FPGA140.
The first input end of FPGA140 connects the output end of the first power supply 120, to be powered by the first power supply 120 for it.
The output end of the second input terminal link control module 130 of FPGA 140 is referred to receiving solution from control module 130 and resetting or reset
Show signal and corresponding state is entered according to received signal.Optionally,
The second input terminal of FPGA 140 is PS_POR_B pin.
When control module 130 monitors that system power supply power supply 100 powers on and the control terminal output state of the first power supply 120
After indication signal PG is to control module 130, control module 130 exports solution reset/reset indication signal to FPGA140.Wherein should
Reset/reset indication signal instruction solution of FPGA 140 is solved to reset.FPGA140 solution resets starting.Control module 130, which continues to monitor, is
System power supply 110, before monitoring that the supply voltage of system power supply power supply 110 drops to closing threshold value, FPGA140's is each
Road power supply keeps working normally.Wherein, which can be the arbitrary value closed in threshold range, the closing threshold value model
It encloses for 0V to 7.02V.When control module 130 monitors under system power supply power supply 110 electric, and its supply voltage is less than and closes threshold
When value, control module 130 exports solution reset/reset indication signal to FPGA 140 again.The wherein solution reset/reset instruction letter
Number instruction FPGA 140 reset.FPGA 140 enters reset state.Each road power supply of FPGA 140 is gradually lower electric.
Power control circuit according to the present utility model for NVR, it is real by the first power supply 120 and control module 130
The timing control that the existing solution of FPGA 140 is resetted or resetted, avoids to power on and causes asking for wafer damage when insufficient or unexpected power down
Topic.In the case that the power control circuit is also solved without backup power source simultaneously, FPGA can ensure that in power supply power down
Normal reset effectively prevents the relevant issues due to caused by non-normal reset.
Especially in the scheme that the FPGA based on match Sentos (Xilinx) realizes intelligence computation, in order to realize that algorithm adds
It is close, it needs using electrical fuse (eFUSE) function.EFUSE is mainly used for encrypting firmware.The function is to FPGA or more
Sequential relationship between electricity, reset there are certain requirements, and there are wafer damage risks if being unsatisfactory for.Currently, being based on Xilinx
The control program that official provides not can solve the problem, especially be easier to cause the damage of chip under unexpected power-down conditions.
Fig. 2 shows the schematic frames according to the power control circuit 200 for NVR of another embodiment of the utility model
Figure.As shown in Fig. 2, the power control circuit 200 for NVR includes system power supply power supply 210, the first power supply 220, control module
230 and FPGA 240.Wherein, system power supply power supply 210, the function of the first power supply 220 and FPGA 240, position and structure are distinguished
It is similar with the corresponding component in the above-mentioned power control circuit 100 for NVR.For sake of simplicity, details are not described herein.
As shown in Fig. 2, including second source 231, processor for control module 230 in the power control circuit 200 of NVR
232, monitoring module 233 and with door 234.
The input terminal of second source 231 connects system power supply power supply 210, to be powered by system power supply power supply 210 for it.The
The first input end of the output end connection processor 232 of two power supplys 231 is simultaneously powered for it.
Second input terminal of processor 232 connects the control terminal of the first power supply 220, the output end connection of processor 232 with
The first input end of door 234.Processor 232 is used for according to generating from the received condition indicative signal PG of the first power supply 220 and defeated
RESET_N signal gives 234 first input end of door out.
Illustratively, when system power supply power supply 210 powers on, processor 232 and FPGA 240 are powered on simultaneously.It handles at this time
The RESET_N signal of the output end output of device 232 always remains as low level.After the completion of FPGA240 is powered on, the first power supply 220
Output state indication signal PG is to processor 232.After processor 232 receives condition indicative signal PG, delay is after a certain period of time
The RESET_N signal for outputting it end output is set to high level, and is transmitted to the first input end with door 234.Optionally, above-mentioned to prolong
When the time be greater than 12ms.Preferably, delay time 14ms.
Illustratively, processor 232 is ARM.Arm processor is suitble to control field, combines with FPGA and processing can be enhanced
Ability, and have the characteristics that versatile, configuration is flexible.Optionally, processor 232 is also possible at CPLD, MCU or CPU
Manage device.
The input terminal of monitoring module 233 connects system power supply power supply 210, to be powered by system power supply power supply 210 for it.Prison
Control the second input terminal of the output end connection and door 234 of module 233.Monitoring module 233 is used for according to system power supply power supply 210
Supply voltage generates and exports the second input terminal that PFO_N signal gives door 234.Monitoring module 233 monitors system power supply electricity
Output signal PFO_N is set to high level when powering on and its supply voltage is greater than or equal to unlatching threshold value by source 210；Work as prison
System power supply power supply 210 is controlled when lower electric and its voltage is less than and closes threshold value, output signal PFO_N is set to low level.
Optionally, which can be the arbitrary value opened in threshold range, and the unlatching threshold range is 0.8V to 0.95V.
Illustratively, monitoring module 233 is power supply monitoring IC chip.Preferably, monitoring module 233 is public with IMP
The monitoring product I MP706 that department releases is realized.IMP706 can powered on, generated reset signal during power down, and have it is low in energy consumption,
High performance feature.
The output end and monitoring module 233 of processor 232 are separately connected with the first input end of door 234 and the second input terminal
Output end.The second input terminal of FPGA 240 is connect with the output end of door 234.When the first input end and second with door 234
When input terminal receives high level signal simultaneously, high level signal is exported, low level signal is otherwise exported.
When system power supply power supply 210 powers on, monitoring module 233 powers on simultaneously, and the first power supply 220 is also powered on and powered simultaneously
To FPGA 240, second source 231 is also powered on simultaneously and is powered to processor 232.At this time processor 232 during startup its
Output end, which is output to, always remains as low level, the output of monitoring module 233 with the RESET_N signal of 234 first input end of door
End, which is output to, always remains as low level with the PFO_N signal of 234 second input terminal of door.With the confession of system power supply power supply 210
Piezoelectric voltage persistently rises, and the supply voltage that monitoring module 233 monitors system power supply power supply 210, which is greater than or equal to, opens threshold value
When, the PFO_N signal of output is set to high level by monitoring module 233.At this point, the RESET_N signal that processor 232 exports is low
Level, the PFO_N signal that monitoring module 233 exports are high level, export low level signal with door 234.When FPGA 240 is powered on
After the completion, 220 output state indication signal PG of the first power supply is to processor 232.When to receive the first power supply 220 defeated for processor 232
After condition indicative signal PG out, be delayed certain time, and RESET_N signal is then set to high level.At this point, PFO_N signal
It is high level with RESET_N signal, receives 2 high level signals simultaneously with door 234 at this time, then the letter of its output end output
Number become high level signal.The high level signal sends the second input terminal of FPGA 240 to, and the solution of FPGA 240, which resets, to be started to open
It is dynamic.
When 210 power down of system power supply power supply, the supply voltage of system power supply power supply 210 starts to reduce and progressively reach closing
Threshold value, each road power supply of FPGA 240 is also able to maintain normal work at this time.Monitoring module 233 detects system power supply power supply 210
Supply voltage be less than close threshold value when, the PFO_N signal of output is set to low level by monitoring module 233.At this point, with door 234
The second input terminal receive low level signal, then with 234 output end of door output signal low level is become from high level.The low electricity
Ordinary mail number sends the second input terminal of FPGA 240 to, and FPGA 240 enters reset state.Each road power supply of FPGA 240 is gradually
Lower electricity.
In short, above-mentioned power control circuit ensure FPGA sufficiently power on reach stable state under the premise of, allow FPGA
Into solution reset state, the risk of wafer damage is avoided.When electric under system, when system power supply power supply voltage drops to closing threshold value
When, which issues reset signal to FPGA in the case where each road power supply of FPGA is also able to maintain normal situation in advance,
Driving FPGA enters reset state, also avoids the risk of unexpected power-down conditions wafer damage.
This for NVR power control circuit in, control module using second source, processor, monitoring module and with
Door realizes that while effectively FPGA being avoided to damage, implementation is simple, has saved system cost.
Although describing example embodiment by reference to attached drawing here, it should be understood that above example embodiment are only exemplary
, and be not intended to the scope of the utility model limited to this.Those of ordinary skill in the art can carry out various wherein
Change and modify, without departing from the scope of the utility model and spirit.All such changes and modifications are intended to be included in appended
Within the scope of the utility model required by claim.
In several embodiments provided herein, it should be understood that disclosed circuit can be by others side
Formula is realized.For example, the division of the unit, only a kind of logical function partition, can there is other division in actual implementation
Mode, such as multiple units or components may be combined or can be integrated into another equipment, or some features can be ignored.
In the instructions provided here, numerous specific details are set forth.It is to be appreciated, however, that the utility model
Embodiment can be practiced without these specific details.Similarly, it should be understood that in order to simplify the utility model simultaneously
Help understands one or more of each inventive point, and in the description to the exemplary embodiment of the utility model, this is practical
Novel each feature is grouped together into a single embodiment, figure, or description thereof sometimes.More precisely, such as phase
As the claims answered reflect, inventive point is that all spies less than some disclosed single embodiment can be used
The feature of sign solves corresponding technical problem.Therefore, it then follows thus claims of specific embodiment are expressly incorporated in
The specific embodiment, wherein separate embodiments of each claim as the utility model itself.
It will be understood to those skilled in the art that any combination pair can be used other than mutually exclusive between feature
All features disclosed in this specification (including adjoint claim, abstract and attached drawing) and so disclosed any circuit
Component be combined.Unless expressly stated otherwise, it is disclosed in this specification (including the accompanying claims, abstract and drawings)
Each feature can be replaced with an alternative feature that provides the same, equivalent, or similar purpose.
In addition, it will be appreciated by those of skill in the art that although some embodiments described herein include other embodiments
In included certain features rather than other feature, but the combination of the feature of different embodiments mean it is practical new in this
Within the scope of type and form different embodiments.For example, in detail in the claims, embodiment claimed it is any
One of can in any combination mode come using.
The utility model is limited it should be noted that above-described embodiment illustrates rather than the utility model,
And those skilled in the art can be designed alternative embodiment without departing from the scope of the appended claims.In right
In it is required that, any reference symbol between parentheses should not be configured to limitations on claims.Word "comprising" is not arranged
Except there are element or steps not listed in the claims.Word "a" or "an" located in front of the element does not exclude the presence of more
A such element.In the unit claims listing several devices, several in these devices can be by same
One hardware branch embodies.The use of word first, second, and third does not indicate any sequence.It can be by these lists
Word is construed to title.
Above description is only a specific implementation of the present invention or to the explanation of specific embodiment, this is practical new
The protection scope of type is not limited thereto, the technology model that anyone skilled in the art discloses in the utility model
In enclosing, it can easily think of the change or the replacement, should be covered within the scope of the utility model.The protection of the utility model
Range should be subject to the protection scope in claims.
Claims (6)
1. a kind of power control circuit for network video recorder, which is characterized in that including system power supply power supply, the first electricity
Source, control module and field programmable gate array, wherein
The system power supply power supply connects the input terminal of first power supply and the first input end of the control module；
The output end of first power supply connects the first input end of the field programmable gate array and first power supply
Control terminal connect the second input terminal of the control module；
The output end of the control module connects the second input terminal of the field programmable gate array.
2. power control circuit according to claim 1, which is characterized in that the control module includes second source, place
Manage device, monitoring module and with door, wherein
The input terminal of the input terminal of the second source and the monitoring module is all connected with the system power supply power supply；
The output end of the second source connects the first input end of the processor and the control terminal of first power supply connects
Connect the second input terminal of the processor；
The output end connection of the processor is described to connect institute with the output end of the first input end of door and the monitoring module
State the second input terminal with door；
Second input terminal that the field programmable gate array is connect with the output end of door.
3. power control circuit according to claim 2, which is characterized in that the processor is Advanced Reduced Instruction Set meter
Calculation machine processor.
4. power control circuit according to claim 2 or 3, which is characterized in that the monitoring module is Power Supply Monitoring collection
At circuit chip.
5. power control circuit according to any one of claims 1 to 3, which is characterized in that the control of first power supply
End is POWER OK or POWER GOOD signal pins.
6. power control circuit according to any one of claims 1 to 3, which is characterized in that the field-programmable gate array
Second input terminal of column is PS_POR_B pin.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201821969778.3U CN208849899U (en) | 2018-11-27 | 2018-11-27 | A kind of power control circuit for network video recorder |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201821969778.3U CN208849899U (en) | 2018-11-27 | 2018-11-27 | A kind of power control circuit for network video recorder |
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| CN208849899U true CN208849899U (en) | 2019-05-10 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111443788A (en) * | 2020-03-25 | 2020-07-24 | 北京智行者科技有限公司 | Power-on control circuit of MPSOC (Multi-processor System on chip) |
-
2018
- 2018-11-27 CN CN201821969778.3U patent/CN208849899U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111443788A (en) * | 2020-03-25 | 2020-07-24 | 北京智行者科技有限公司 | Power-on control circuit of MPSOC (Multi-processor System on chip) |
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