CN206481280U - A kind of delays time to control reset circuit - Google Patents
A kind of delays time to control reset circuit Download PDFInfo
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- CN206481280U CN206481280U CN201720174271.8U CN201720174271U CN206481280U CN 206481280 U CN206481280 U CN 206481280U CN 201720174271 U CN201720174271 U CN 201720174271U CN 206481280 U CN206481280 U CN 206481280U
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Abstract
The utility model discloses a kind of delays time to control reset circuit, including reset key, reset generator, delay signal generating circuit, the reset generator is MAX706 family chips, the hand-reset input connection reset key of the reset generator, the power input connection operating voltage of the reset generator, the comparator input terminal connection delay signal generating circuit of the reset generator, the comparator results output end of the reset generator connects the processor electrification reset pin of flush type circuit system, the systematic reset signal output end of the reset generator connects the reset pin of flush type circuit system.The utility model can effectively eliminate the shake of system reset button, compared with available circuit and more refined effectively, can meet the reset demand of conventional embedded chip.
Description
Technical field
The utility model is related to a kind of reset circuit, more particularly to a kind of delays time to control reset circuit.
Background technology
In flush type circuit system based on ZYNQ family chips, ZYNQ (expansible processing platform) chip is needed to use
Reset signal, to have stable original operating state after ensuring chip power-up.It is required that reset signal continues to that chip is stable
After power supply, the usual reset signal is connected to the power supply state good instruction pin of power supply chip.Used in embedded system
Power supply chip quantity is more, and the state of each power supply, which is compared, can make complex circuit designs, and different embedded chips
Need resetting time different, therefore the length of control resetting time seems and is even more important.
The power-on reset signal generation circuit of the flush type circuit system of prior art is as shown in figure 1, its core component is
Chip model LM339M four road comparators, the state of supply voltage is judged by comparing power supply chip per output voltage all the way,
Then power-on reset signal PS_POR_B is exported.The systematic reset signal PS-RST of flush type circuit system passes through shown in Fig. 2
Key switch BTN7 is produced.
There is problems with above-mentioned reset signal generating circuit：
To being compared the peripheral circuit, it is necessary to more complicated per power supply output state all the way；
The power-on reset signal PS_POR_B duration cannot be adjusted according to specific needs；
Systematic reset signal has shake.
Utility model content
The utility model provide it is a kind of it is simple, facilitate controllable delays time to control reset circuit, for overcoming prior art
Reset signal generating circuit present in weak point.
The utility model solves the technical scheme that its technical problem used：A kind of delays time to control reset circuit, including
Reset key, reset generator, delay signal generating circuit, the reset generator are MAX706 family chips, reset production
The hand-reset input connection reset key of raw device, the power input connection operating voltage of the reset generator, the reset
The comparator input terminal connection delay signal generating circuit of generator, the comparator results output end connection of the reset generator is embedding
Enter the processor electrification reset pin of formula circuit system, the systematic reset signal output end connection embedded-type electric of the reset generator
The reset pin of road system.
Further, the stabilizing circuit of the power-on reset signal for resetting generator, stabilizing circuit connection are included
The comparator results output end for resetting generator.
Further, the delay signal generating circuit includes resistance R1, electric capacity C1, and electric capacity C1 one end connection is described multiple
The comparator input terminal of position generator, and pass through the resistance R1 connections operating voltage.
Further, the stabilizing circuit includes electric capacity C2, electric capacity C2 one end connection ratio for resetting generator
Compared with device result output end, other end ground connection.
Further, in addition to resistance R2, resistance R3, resistance R2 one end connection resets the systematic reset signal of generator
Output end, the other end connects the reset pin of flush type circuit system；The resistance R3 one end connection resistance R2 other end, resistance
R3 other end ground connection.
Further, the power supply that power supply chip of the operating voltage from flush type circuit system is finally exported.
Further, the model MAX706TESA for resetting generator, its pin 1 is hand-reset input, is drawn
Pin 2 is power input, and pin 3 is earth terminal, and connects electricity, and pin 4 is comparator input terminal, and pin 5 is that comparator results are defeated
Go out end, pin 6 is house dog input, and vacant, pin 7 is systematic reset signal output end, pin 8 is house dog output
End, and it is vacant.
Further, one end of the reset key connects the hand-reset input, other end ground connection.
Compared to prior art, the utility model has the advantages that：
The power-on reset signal PS_ resetted required for generator produces ZYNQ chips being made up of MAX706 family chips
POR_B and systematic reset signal PS-RST, power-on reset signal PS_POR_B delay depend on delay signal generating circuit, lead to
The duration of power-on reset signal can be controlled by crossing the delay signal generating circuit.Chip MAX706 can effectively eliminate system
The shake of reset key, is compared with available circuit, and the utility model is more refined effectively, can meet conventional embedded chip
Reset demand.
The utility model is described in further detail below in conjunction with drawings and Examples；But one kind of the present utility model is prolonged
When control reset circuit be not limited to embodiment.
Brief description of the drawings
Fig. 1 is the schematic diagram of the power-on reset signal generation circuit of prior art；
Fig. 2 is the schematic diagram of the systematic reset signal generation circuit of prior art；
Fig. 3 is electrical block diagram of the present utility model.
Embodiment
Embodiment, a kind of shown in Figure 3, delays time to control reset circuit of the present utility model, including reset key S1-
SW, reset generator D1, delay signal generating circuit, the reset generator D1 is MAX706 family chips, specifically, the reset
Generator D1 model MAX706TESA, its pin 1 is hand-reset input, and pin 2 is power input, and pin 3 is
Earth terminal, and electricity is connect, pin 4 is comparator input terminal, and pin 5 is comparator results output end, and pin 6 inputs for house dog
End, and vacant, pin 7 is systematic reset signal output end, and pin 8 is house dog output end, and vacant.Reset generator D1's
Hand-reset input connects reset key S1-SW, and power input connection operating voltage VCC, comparator input terminal connection is prolonged
Slow signal generating circuit, comparator results output end connects the processor electrification reset pin PS_POR_ of flush type circuit system
B, systematic reset signal output end connects the reset pin PS-RST of flush type circuit system.
In the present embodiment, include the stabilizing circuit of the power-on reset signal for resetting generator D1, the stabilizing circuit
The connection comparator results output end for resetting generator D1.The stabilizing circuit includes electric capacity C2, electric capacity C2 one end
The connection comparator results output end for resetting generator D1, other end ground connection.
In the present embodiment, the delay signal generating circuit includes resistance R1, electric capacity C1, and electric capacity C1 one end connection is described
Generator D1 comparator input terminal is resetted, and the operating voltage VCC is connected by resistance.The operating voltage VCC is specific
The power supply that power supply chip from flush type circuit system is finally exported.
In the present embodiment, in addition to resistance R2, resistance R3 for partial pressure, resistance R2 one end connection reset generator D1
Systematic reset signal output end, the other end connect flush type circuit system reset pin；Resistance R3 one end connection resistance
The R2 other end, resistance R3 other end ground connection.One end of the reset key S1-SW connects the hand-reset input,
The other end is grounded.
The utility model first connects after core power the powering order for connecting I/O interface powers using ZYNQ chips, and
The characteristics of I/O interface powers are usually not less than 1.8V.Different from available circuit, generator D1 pin 4 and inside 1.25V is resetted
Level is compared, and simplifies periphery circuit design.Reset key S1-SW shake can be eliminated by resetting generator D1, by adjusting
C1 capacitance is held in economize on electricity, can control the duration of power-on reset signal.
Above-described embodiment is only used for further illustrating a kind of delays time to control reset circuit of the present utility model, but this practicality is new
Type is not limited to embodiment, every any simply to be repaiied according to what technical spirit of the present utility model was made to above example
Change, equivalent variations and modification, each fall within the protection domain of technical solutions of the utility model.
Claims (8)
1. a kind of delays time to control reset circuit, it is characterised in that：Including reset key, reset generator, postpones signal generation electricity
Road, the reset generator is MAX706 family chips, and the hand-reset input connection reset key of the reset generator should
The power input connection operating voltage of generator is resetted, the comparator input terminal connection delay signal of the reset generator is produced
Circuit, the comparator results output end of the reset generator connects the processor electrification reset pin of flush type circuit system, should
The systematic reset signal output end for resetting generator connects the reset pin of flush type circuit system.
2. delays time to control reset circuit according to claim 1, it is characterised in that：Also include the upper of the reset generator
The stabilizing circuit of reset signal, the stabilizing circuit connection comparator results output end for resetting generator.
3. delays time to control reset circuit according to claim 1, it is characterised in that：The delay signal generating circuit includes
Resistance R1, electric capacity C1, electric capacity C1 one end connection is described to reset the comparator input terminal of generator, and passes through resistance R1 connections institute
State operating voltage.
4. delays time to control reset circuit according to claim 2, it is characterised in that：The stabilizing circuit includes electric capacity C2,
Electric capacity C2 one end connection comparator results output end for resetting generator, other end ground connection.
5. delays time to control reset circuit according to claim 1, it is characterised in that：Also include resistance R2, resistance R3, resistance
R2 one end connection resets the systematic reset signal output end of generator, and the reset of other end connection flush type circuit system is drawn
Pin；The resistance R3 one end connection resistance R2 other end, resistance R3 other end ground connection.
6. delays time to control reset circuit according to claim 1, it is characterised in that：The operating voltage comes from embedded-type electric
The power supply that the power supply chip of road system is finally exported.
7. delays time to control reset circuit according to claim 1, it is characterised in that：The model for resetting generator
MAX706TESA, its pin 1 is hand-reset input, and pin 2 is power input, and pin 3 is earth terminal, and connects electricity, is drawn
Pin 4 is comparator input terminal, and pin 5 is comparator results output end, and pin 6 is house dog input, and vacant, pin 7 is
Systematic reset signal output end, pin 8 is house dog output end, and vacant.
8. delays time to control reset circuit according to claim 1, it is characterised in that：One end connection institute of the reset key
State hand-reset input, other end ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720174271.8U CN206481280U (en) | 2017-02-24 | 2017-02-24 | A kind of delays time to control reset circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720174271.8U CN206481280U (en) | 2017-02-24 | 2017-02-24 | A kind of delays time to control reset circuit |
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| CN206481280U true CN206481280U (en) | 2017-09-08 |
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| CN201720174271.8U Active CN206481280U (en) | 2017-02-24 | 2017-02-24 | A kind of delays time to control reset circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111443788A (en) * | 2020-03-25 | 2020-07-24 | 北京智行者科技有限公司 | Power-on control circuit of MPSOC (Multi-processor System on chip) |
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2017
- 2017-02-24 CN CN201720174271.8U patent/CN206481280U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111443788A (en) * | 2020-03-25 | 2020-07-24 | 北京智行者科技有限公司 | Power-on control circuit of MPSOC (Multi-processor System on chip) |
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