CN109257038A - High Speed Signal Processor System has access to electricity sequential control circuit - Google Patents
High Speed Signal Processor System has access to electricity sequential control circuit Download PDFInfo
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- CN109257038A CN109257038A CN201811438411.3A CN201811438411A CN109257038A CN 109257038 A CN109257038 A CN 109257038A CN 201811438411 A CN201811438411 A CN 201811438411A CN 109257038 A CN109257038 A CN 109257038A
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- Prior art keywords
- pin
- high speed
- signal processor
- speed signal
- electricity
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Abstract
Have access to electricity sequential control circuit the present invention provides a kind of High Speed Signal Processor System, belongs to digital circuit technique field, including the non-isolated adjustable DC/DC power module U1 and adjustable managing chip U2 that is delayed；Wherein, digitally DGND is commonly connected to the pin SMARTSYNC, pin GND and pin SENSE- of U1 after the pin VOADJUST connection resistance R3 of U1, power supply output end is commonly connected to after the pin TURBOTRANS connection resistance R1 of U1 with pin VO, the pin SENSE+ of U1, the pin VI of U1 is connect with energization input.The present invention provides a kind of circuit that stability contorting power supply electrifying sequence is realized in the digital signal processing circuit system using FPGA and DSP as core, especially meeting the requirements output supply voltage is+1V and its following level, and it is required that it reaches the high-precision output after threshold value after ms grade delays with respect to input voltage, have many advantages, such as to power on reliable and stable, parameter setting conveniently, structure it is simply small in size.
Description
Technical field
The invention belongs to digital circuit technique field, and in particular, to a kind of in High Speed Signal Processor System
Electric sequential control circuit.
Background technique
The core of High Speed Signal Processor System be extensive programmable gate array (FPGA) and have parallel processing energy
The digital signal processor (DSP) of power, in addition to this further includes the storage chips such as DDR, RAM and other I/O circuits, high speed signal
Processing system need to provide for its chip and circuit including DSP core IO supply voltage DVDD, DSP core supply voltage CVDD,
DDR reference voltage Vref s, FPGA kernel supply voltage VCCINT, auxiliary power supply voltage VCCAUX, IO auxiliary power supply voltage
The supply voltages such as VCCAUX_IO, RAM block supply voltage VCCBRAM, I/O input voltage VIN, and according to the chip of selection and
The difference of physical circuit passes through the electric sequence of each supply voltage of circuit control.As Chinese patent 201420359531.5 is public
A kind of multiple DSP system based on video information acquisition process opened belongs to a kind of High Speed Signal Processor System, which refers to
Power management module (401) includes the circuit for the monitoring power source change built using TLC7733, TLC7725, TPS3707 chip,
Cooperate peripheral circuit generation+1.2V power supply ,+1.8V power supply ,+3.3V power supply ,+5V power supply, while referring to for each system
Power demands reset management module (402) and are made of TPS3808, TPS3350 chip for providing required reset signal for system
Reset circuit, provide electrification reset interface for whole system.Power management module in its open scheme does not disclose specifically
Realize the circuit of electric sequence control section.
In the prior art, the scheme for controlling the electrifying timing sequence of more power supplys mainly has following three kinds: the first is to utilize electricity
The enable end of source module controls；It is for second to carry out control by adjusting the time constant of power supply soft-start circuit and power on；Third
Kind is to utilize dedicated electrifying timing sequence controller.Wherein, the first scheme is the power supply output control series connection powered on using prime
Diode current flow cut-off, the power circuit for directly controlling rear end is enabled, this method to be mainly characterized by circuit simple, be suitble to two
To three-way power and each power supply basic demand powers on simultaneously.Due to being simple diode as ON-OFF control circuit, nothing
Method controls the time delay of each road power supply electrifying, and it is unreliable to work, when power supply electrifying timing sequence itself and bigger desired value difference
It is easy to burn diode, is only applicable to simple electrifying timing sequence control；Second scheme is by adjusting power supply delay startup electricity
The case where time constant on road carries out control and powers on, and is provided for multiple power supplies by each isolated power module, each power module
Order is powered on using isolated soft-start circuit control out-put supply, but since the starting time of each module and power-on time are each
Not identical, time parameter set by soft-start circuit is not applied for the power module of different manufacturers, and controllability is poor, simultaneously
For first power on supply voltage when powered on as after supply voltage conversion made of power source design, can not still use this side
Method；The third scheme controls the electric sequence and timing of each road power supply by power supply electrifying sequence controller, the disadvantage is that, powering on
Sequence controller relative cost is higher, and logical resource and interface resource are relatively limited, and needs dedicated programmed logic external member.In
State's patent 201120080943.1 provides a kind of power-on time sequence control circuit, and circuit includes sequence controller and electronic switch
Circuit, wherein the input terminal of sequence controller and output end are connected respectively to the electronic switching circuit control terminal of power supply sum, pass through
Carry out the output signal of control sequential controller to sequence controller programming, connects on-off with control the electronic switching circuit
It opens, with the enable end for being switched on or switched off control charged power circuit of electronic switching circuit, to realize to different charged powers
The control of the electrifying timing sequence for the supply voltage that circuit is exported.The electronic switching circuit principle of above scheme easily realizes, but because making
Cause volume big with transformer, it is at high cost, and postpone to export specified supply for a period of time after powering on for electric sequence control+5V
The function of piezoelectric voltage, due to limiting to for electronic switching circuit itself, in the case where being delayed power supply, transient response characteristic is poor, on
The service life of core devices is easily damaged and influenced during electricity, especially in specified output+1V and following voltage, output characteristics
It is easy to be influenced to be difficult to reliably to power on by conduct electrons switch.
Summary of the invention
It is real in the digital signal processing circuit system using FPGA and DSP as core that it is an object of the present invention to provide a kind of
The circuit of existing stability contorting power supply electrifying sequence meets the requirements output supply voltage especially as+1V and its following level, and
And require its with respect to input voltage reach threshold value after by ms grade delay after high-precision output, with power on it is reliable and stable,
The advantages that parameter setting is convenient, structure is simply small in size.
Present invention provide the technical scheme that
A kind of High Speed Signal Processor System has access to electricity sequential control circuit, including non-isolated adjustable DC/DC power module U1
With the adjustable managing chip U2 that is delayed；Wherein, after the pin VOADJUST connection resistance R3 of U1 with the pin SMARTSYNC of U1, draw
Foot GND and pin SENSE- is commonly connected to digitally DGND, draws after the pin TURBOTRANS connection resistance R1 of U1 with U1
Foot VO, pin SENSE+ are commonly connected to power supply output end, and the pin VI of U1 is connect with energization input；The pin RESET# of U2
It connect through resistance R2 with energization input after being connect with the pin TRACK of U1, draws after the pin CT connection capacitor C2 of U2 with U2
Foot GND is commonly connected to digitally DGND, and one end is connected to supply input after the pin SENSE of the pin VDD and U2 of U2 are connected
It holds, is connected to digitally DGND after another termination capacitor C1.
Further, the pin INHIBIT of U1 connects vacantly, and the pin MR# of U2 connects vacantly；
Further, energization input and digitally between DGND and have a tantalum electrolytic capacitor, power supply output end with digitally
Between DGND and there is tantalum electrolytic capacitor.
Further, U1 and U2 is respectively PTH08T230W and TPS3808G50, after energization input voltage reaches 5V,
1V voltage below can be exported according to setting.
One aspect of the present invention has the benefit that the size of adjustment resistance R3, available different output
Voltage, such as when resistance R3 is 20.5K Ω, input power 5V obtains output voltage 1V through U1.
One aspect of the present invention has the benefit that can be electric to control input by adjusting the size of capacitor C2
Source powers on reach threshold value after, voltage 1V output delay time.Such as when capacitor C2 is 470PF, voltage 1V is opposite after transformation
It is exported after input voltage 5V delay 3.2ms, capacitor C2 is bigger, and delay time is bigger.
Detailed description of the invention
Fig. 1 is the circuit diagram of one embodiment of the invention；
Fig. 2 is the schematic diagram of the DC/DC translation circuit in one embodiment of the invention；
Fig. 3 is the schematic diagram of the output voltage delay control circuit in one embodiment of the invention；
Fig. 4 is the schematic diagram of energization input filter circuit in one embodiment of the invention；
Fig. 5 is the schematic diagram of power supply output end filter circuit in one embodiment of the invention.
Specific embodiment
Further description is made to the present invention combined with specific embodiments below:
As shown in Figure 1, the present embodiment is a kind of power-on time sequence control circuit 100 for High Speed Signal Processor System,
Inside includes a non-isolated adjustable DC/DC power module U1 and an adjustable managing chip U2 of delay, and judgement may be implemented and supply
It after the voltage of electrical input Vin reaches specified threshold value, then is delayed after specified time, exports specified burning voltage.This reality
It applies in example and is passed through after the input of energization input Vin reaches 5V voltage according to the requirement of High Speed Signal Processor System where it
After 3.2ms power supply output end vo ut export stable 1V voltage, for High Speed Signal Processor System specified chip or
The power supply of person's circuit.
As shown in Fig. 2, the non-isolated adjustable DC/DC power module U1 of the present embodiment selects PTH08T230W, input electricity
Pressing range can be 4.5V~14V, and corresponding output voltage values range can be 0.69V~5.5V, and maximum provides electric current 6A, and efficiency is reachable
95%, output voltage precision ± 1.5%.After the 7th foot VOADJUST connecting resistance R3 of U1 with the 1st foot SMARTSYNC of U1, the 3rd
Foot GND, the 6th foot SENSE- are commonly connected to digitally DGND, and the 2nd foot VI of U1 meets input power 5V (i.e. energization input), U1
It is connect after 8th foot TURBOTRANS foot connecting resistance R1 with the 4th foot VO and as the output end 1V of U1 (i.e. power supply output end), U1
5th foot SENSE+ meets the output end 1V of U1, and the 10th foot INHIBIT is hanging, wherein input power 5V termination capacitor C3~C5, output
1V termination capacitor C6~C10.
As shown in figure 3, the adjustable managing chip U2 of the delay of the present embodiment selects TPS3808G50, it is TPS3808 series core
Fixed surveillance voltage value is the model of 5V in piece.The 9th foot TRACK of the 1st foot RESET# (being RESET in figure) and the U1 of U2 connects
After connecing (network as shown in Figure 3 is marked as TRACK_5V), it is pulled to input power 5V through resistance R2, the 2nd foot GND connects digitally
DGND, the 3rd foot MR# (in figure be MR) connect hanging, and the 4th foot CT connects after capacitor C2 to digitally DGND, the 5th foot SENSE and the 6th foot
VDD connection, a termination input power 5V, to digitally DGND after another termination capacitor C1.
Fig. 4, Fig. 5 show filter circuit between energization input and digitally DGND and power supply output end with digitally
Filter circuit between DGND.Wherein capacitor C5, C6 is tantalum electrolytic capacitor.
Working principle
In the present embodiment, the size of resistance R3 is adjusted, the voltage of available different power supply output end such as works as resistance R3
When for 20.5K Ω, input power 5V obtains output voltage 1V through non-isolation DC/DC converter U1.It can be by adjusting capacitor C2
Size power on and reach threshold value controlling input power 5V after, voltage 1V output delay time.Such as when capacitor C2 is 470PF
When, voltage 1V is exported after postponing 3.2ms with respect to input voltage 5V after transformation, and capacitor C2 is bigger, and delay time is bigger.Above-mentioned choosing
Type is made for following circuits parameter: resistance R1 is 5.9K Ω, R2 is 10K Ω, and capacitor C1 is that 0.1UF, C3 and C4 are
20UF, tantalum electrolytic capacitor C5 are 330UF, tantalum electrolytic capacitor C6 be 100UF, C7~C10 is 47UF.Height provided in this embodiment
Fast signal processing system is greatly reduced because load transient changes bring voltage deviation, enhances the stability of output voltage,
Meet a kind of large-scale F PGA and high-speed dsp be core igh-speed wire-rod production line circuit system supply voltage requirement, pass through
The example of one typical circuit provides a kind of beneficial reference for the design of power circuit in complex digital circuitry.
Part not in the detailed description of the invention is the prior art.
Claims (4)
- The sequential control circuit 1. a kind of High Speed Signal Processor System has access to electricity, it is characterised in that: including non-isolated adjustable DC/DC electricity The source module U1 and adjustable managing chip U2 that is delayed；Wherein, the pin after the pin VOADJUST connection resistance R3 of U1 with U1 SMARTSYNC, pin GND and pin SENSE- are commonly connected to digitally DGND, the pin TURBOTRANS connection resistance of U1 Power supply output end is commonly connected to after R1 with the pin VO of U1, pin SENSE+, the pin VI of U1 is connect with energization input；U2 Pin RESET# and U1 pin TRACK connection after connect through resistance R2 with energization input, the pin CT connection capacitor of U2 Digitally DGND is commonly connected to after C2 with the pin GND of U2, one end connects after the pin SENSE of the pin VDD and U2 of U2 are connected It is connected to energization input, is connected to digitally DGND after another termination capacitor C1.
- The sequential control circuit 2. High Speed Signal Processor System according to claim 1 has access to electricity, it is characterised in that: U1's draws Foot INHIBIT connects vacantly, and the pin MR# of U2 connects vacantly.
- 3. according to claim 1 or 2 described in any item High Speed Signal Processor Systems have access to electricity sequential control circuit, feature exists In: between energization input and digitally DGND and there is a tantalum electrolytic capacitor, powering output end and digitally between DGND and has tantalum Electrolytic capacitor.
- The sequential control circuit 4. High Speed Signal Processor System according to claim 3 has access to electricity, it is characterised in that: U1 and U2 Respectively PTH08T230W and TPS3808G50.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811438411.3A CN109257038A (en) | 2018-11-28 | 2018-11-28 | High Speed Signal Processor System has access to electricity sequential control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811438411.3A CN109257038A (en) | 2018-11-28 | 2018-11-28 | High Speed Signal Processor System has access to electricity sequential control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109257038A true CN109257038A (en) | 2019-01-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811438411.3A Pending CN109257038A (en) | 2018-11-28 | 2018-11-28 | High Speed Signal Processor System has access to electricity sequential control circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111443788A (en) * | 2020-03-25 | 2020-07-24 | 北京智行者科技有限公司 | Power-on control circuit of MPSOC (Multi-processor System on chip) |
| CN114326500A (en) * | 2021-12-27 | 2022-04-12 | 昂纳信息技术（深圳）有限公司 | Power supply circuit, FPGA circuit and optical module |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201222720Y (en) * | 2008-07-08 | 2009-04-15 | 深圳市同洲电子股份有限公司 | Control circuit for electrification sequence |
| CN203535416U (en) * | 2013-10-23 | 2014-04-09 | 河海大学常州校区 | A digital signal processing chip power supply circuit |
| CN209201037U (en) * | 2018-11-28 | 2019-08-02 | 中国空空导弹研究院 | High Speed Signal Processor System has access to electricity sequential control circuit |
-
2018
- 2018-11-28 CN CN201811438411.3A patent/CN109257038A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201222720Y (en) * | 2008-07-08 | 2009-04-15 | 深圳市同洲电子股份有限公司 | Control circuit for electrification sequence |
| CN203535416U (en) * | 2013-10-23 | 2014-04-09 | 河海大学常州校区 | A digital signal processing chip power supply circuit |
| CN209201037U (en) * | 2018-11-28 | 2019-08-02 | 中国空空导弹研究院 | High Speed Signal Processor System has access to electricity sequential control circuit |
Non-Patent Citations (2)
| Title |
|---|
| TEXAS INSTRUMENTS: "6-A, 4.5-V to 14-V INPUT, NON-ISOLATED, WIDE-OUTPUT, ADJUSTABLE POWER MODULE WITH TurboTrans™，Check for Samples: PTH08T230W, PTH08T231W", pages 9, Retrieved from the Internet <URL:www.ti.com> * |
| TEXAS INSTRUMENTS: "TPS3808 Low-Quiescent-Current, Programmable-Delay Supervisory Circuit", pages 4, Retrieved from the Internet <URL:www.ti.com> * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111443788A (en) * | 2020-03-25 | 2020-07-24 | 北京智行者科技有限公司 | Power-on control circuit of MPSOC (Multi-processor System on chip) |
| CN111443788B (en) * | 2020-03-25 | 2022-02-18 | 北京智行者科技有限公司 | Power-on control circuit of MPSOC (Multi-processor System on chip) |
| CN114326500A (en) * | 2021-12-27 | 2022-04-12 | 昂纳信息技术（深圳）有限公司 | Power supply circuit, FPGA circuit and optical module |
| CN114326500B (en) * | 2021-12-27 | 2024-03-12 | 昂纳科技(深圳)集团股份有限公司 | Power supply circuit, FPGA circuit and optical module |
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