CN105281724A - Power-on reset circuit used for integrated circuit chip - Google Patents
Power-on reset circuit used for integrated circuit chip Download PDFInfo
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- CN105281724A CN105281724A CN201510800251.2A CN201510800251A CN105281724A CN 105281724 A CN105281724 A CN 105281724A CN 201510800251 A CN201510800251 A CN 201510800251A CN 105281724 A CN105281724 A CN 105281724A
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- electrify restoration
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Abstract
The invention provides a power-on reset circuit used for an integrated circuit chip. The power-on reset circuit comprises a delay circuit, a comparison circuit and a biasing circuit. The delay circuit enables input power supply voltage to form delayed voltage signals with certain time delay. The comparison circuit receives the delayed voltage signals and outputs reset signals when the delayed voltage signals are greater than set voltage values. The biasing circuit provides the set voltage values for the comparison circuit. The power-on reset circuit effectively reduces the layout area of circuits, solves the problem of system instability caused by power glitches, can achieve reliable reset even during slow rise of power supply and is easy to popularize and implement.
Description
Technical field
The present invention relates to technical field of integrated circuits, particularly relate to a kind of for the electrify restoration circuit in integrated circuit (IC) chip.
Background technology
In electronic system, electrify restoration circuit is one of circuit module be in daily use, and it can realize producing reset signal while power up, carries out reset operation, thus eliminate the labile state of circuit module when powering on initial to other module of circuit.In the Circuits System containing the unit such as register, latch, trigger, power-on reset signal is all needed to carry out initialization or replacement to these unit.
Major part electrify restoration circuit is all adopt time delay mechanism to produce reset signal, as shown in Figure 1.Fig. 1 is a basic reset circuit, to utilize in RC circuit the charging of electric capacity to realize the delay of signal.There are the following problems for this circuit structure, on the one hand, for ensureing avdd stable rear a period of time (being about μ s level), reset circuit just exports reset signal, need the time constant of the RC circuit be delayed very large, so just make electric capacity very large (about μ F level), and electric capacity large so in integrated circuits, to considerable area be taken, cause the very big rising of cost.On the other hand, the filter effect of electric capacity to burr signal is limited, if having larger fluctuation for generation of the supply voltage of reset signal, then likely produces the reset signal of mistake and makes circuit misoperation, causing the instability of system.
To sum up, a kind of new electrify restoration circuit is needed badly to solve the problem.
Summary of the invention
One of technical problem to be solved by this invention needs to provide a kind of new electrify restoration circuit to solve the misoperation problem of existing reset circuit.
In order to solve the problems of the technologies described above, the embodiment of the application provides a kind of for the electrify restoration circuit in integrated circuit (IC) chip, comprising: delay circuit, makes the supply voltage of input form the time delay voltage signal with certain hour delay; Comparison circuit, receives described time delay voltage signal, exports reset signal when described time delay voltage signal is greater than the magnitude of voltage of setting; Biasing circuit, for described comparison circuit provides the magnitude of voltage of setting.
Preferably, described delay circuit is set to low-pass network, comprises the first transistor and the first filter capacitor; Described biasing circuit provides the first bias voltage or the second bias voltage to work in linear zone to make it for described the first transistor.
Preferably, described the first transistor is PMOS transistor, and its source electrode connects the positive pole of the supply voltage of input, and its drain electrode couples with one end of described first filter capacitor, the negative pole of the supply voltage of another termination input of described first filter capacitor; The grid of described PMOS transistor connects described first bias voltage or the second bias voltage, exports time delay voltage signal in the drain electrode of described PMOS transistor.
Preferably, described biasing circuit comprises the first biasing resistor, the first diode and the second diode between the positive pole of the supply voltage being serially connected with input successively and negative pole, described first diode and the equal forward bias of the second diode, and locate output first bias voltage coupling of they.
Preferably, described biasing circuit also comprises the transistor seconds working in saturation region between the positive pole of the supply voltage being serially connected with input successively and negative pole and the second biasing resistor, the grid of described transistor seconds and drain electrode short circuit, locate output second bias voltage in the drain electrode of described transistor seconds and coupling of described second biasing resistor.
Preferably, using described first bias voltage as the magnitude of voltage of described setting.
Preferably, described comparison circuit comprises positive feedback hysteresis comparator.
Preferably, the drain electrode of described PMOS transistor is coupled to the in-phase input end of described positive feedback hysteresis comparator, the magnitude of voltage of inverting input by setting described in first-order filtering network insertion of described positive feedback hysteresis comparator.
Preferably, described first-order filtering network comprises the second filter capacitor, and the capacitance of described second filter capacitor is not more than 1pF.
Preferably, described first filter capacitor comprises mos capacitance, MIM capacitor or MOM capacitor.
Compared with prior art, the one or more embodiments in such scheme can have the following advantages or beneficial effect by tool:
While the chip area effectively reducing circuit, solve the problem of the system instability that power supply burr causes, and also can realize reliable reset when power supply slowly rises, be easy to promotion and implementation.
Other advantages of the present invention, target, to set forth in the following description to a certain extent with feature, and to a certain extent, based on will be apparent to those skilled in the art to investigating hereafter, or can be instructed from the practice of the present invention.Target of the present invention and other advantages can by specifications below, claims, and in accompanying drawing, specifically noted structure realizes and obtains.
Accompanying drawing explanation
Accompanying drawing is used to provide the further understanding of technical scheme to the application or prior art, and forms a part for specification.Wherein, the expression accompanying drawing of the embodiment of the present application and the embodiment one of the application are used from the technical scheme explaining the application, but do not form the restriction to technical scheme.
Fig. 1 is electrify restoration circuit schematic diagram basic in prior art;
Fig. 2 is the structural representation of the electrify restoration circuit of the embodiment of the present application;
Fig. 3 is the delay circuit schematic diagram of the electrify restoration circuit of the embodiment of the present application;
Fig. 4 is the comparison circuit schematic diagram of the electrify restoration circuit of the embodiment of the present application;
Fig. 5 is the biasing circuit schematic diagram of the electrify restoration circuit of the embodiment of the present application;
Fig. 6 is the contrast schematic diagram of the simulation result to the embodiment of the present application and comparative examples;
Fig. 7 is the schematic diagram of the chip area of the embodiment of the present application and comparative examples.
Embodiment
Describe embodiments of the present invention in detail below with reference to drawings and Examples, to the present invention, how application technology means solve technical problem whereby, and the implementation procedure reaching relevant art effect can fully understand and implement according to this.Each feature in the embodiment of the present application and embodiment, can be combined with each other under prerequisite of not conflicting mutually, the technical scheme formed is all within protection scope of the present invention.
As shown in Figure 2, the electrify restoration circuit of the embodiment of the present application comprises delay circuit 21, comparison circuit 22 and biasing circuit 23, electrify restoration circuit receives the supply voltage avdd of input, and the reset signal Vrst of stable output, is described in detail below in conjunction with Fig. 3, Fig. 4, Fig. 5.
Delay circuit 21, is mainly used in making the supply voltage of input form the time delay voltage signal with certain hour delay, then the time delay voltage signal of output is received the input of comparison circuit 22.For reducing chip area with cost-saving, the embodiment of the present application have employed a kind of delay circuit structure as shown in Figure 3, and delay circuit is traditionally arranged to be low-pass network, comprises the first transistor and the first filter capacitor that work in linear zone.
Concrete, as shown in Figure 3, delay circuit 21 is by the PMOS M being biased in linear zone
pwith electric capacity C
0composition.In this low-pass network, M
psource electrode meet the positive pole avdd of the supply voltage of input, its drain electrode and C
0one end couple, C
0the negative pole avss of another termination supply voltage.M
pgrid connect the first bias voltage or the second bias voltage, time delay voltage signal V
delayfrom M
pdrain electrode export.In such scheme, delay circuit produces certain time delay to supply voltage avdd.Due to M
ppipe works in linear zone, therefore can be equivalent to the large resistance of one tens, thus the first less filter capacitor of only need arranging in pairs or groups, the power-on time that just can realize needed for reset circuit postpones.
Further, M is passed through
pgrid voltage V
bto M
ppipe controls, and can produce the large resistance of the different equivalence of resistance, thus controls the delay time of delay circuit 21 flexibly.First bias voltage and the second bias voltage produce by biasing circuit 23.M
pequivalent resistance be inversely proportional to the voltage being applied to its grid.Namely M is worked as
pwhen being operated in linear zone with larger overdrive voltage, the large resistance of equivalence can be realized.Work as M
pwhen being operated in linear zone with less overdrive voltage, the large resistance of larger equivalence can being realized, thus reduce the volume of electric capacity further, and then reduce the area of domain.
It is also to be noted that the implementation of the first filter capacitor in above-mentioned delay circuit 21 has multiple choices, such as, PMOS transistor or nmos pass transistor can be utilized to form mos capacitance as C
0, further, being not limited to mos capacitance, can also be MIM capacitor, MOM capacitor etc. conventional in integrated circuit.Owing to adopting the large resistance in the PMOS transistor equivalence integrated circuit of linear zone work, greatly reduce the area of circuit layout.Compared with adopting the scheme of high-ohmic resistor in integrated circuit, chip area of the present invention is about reduced to 1/4th of former scheme, significantly reduces cost, improves the competitiveness of integrated circuit.
Comparison circuit 22, the time delay voltage signal that reception delay circuit 21 exports, exports reset signal and resets to circuit when time delay voltage signal is greater than the magnitude of voltage of setting.Fig. 4 is the comparison circuit schematic diagram of the electrify restoration circuit of the embodiment of the present application, can find out, in the present embodiment, comparison circuit 22 adopts positive feedback hysteresis comparator structure.Concrete, transistor M
4, M
5form the Differential Input of comparator to pipe, wherein, M
4for in-phase input end, M
5for inverting input.Transistor M
2as tail current source, its drain electrode and M
4and M
5source electrode be coupled in together, M
2bias voltage V
bpthered is provided by biasing circuit 23, V
bpbe also transistor M simultaneously
3bias voltage is provided.Transistor M
6, M
9grid with drain electrode be coupled in separately together with, composition diode structure load.
Comparator utilizes positive feedback to realize lag function.Transistor M
7and M
8grid separately respectively with M
6and M
9grid couple, M
7and M
8drain electrode separately respectively with M
5and M
4drain electrode couple, M
7and M
8source electrode be coupled in the negative pole avss of the supply voltage connecing input together, form the positive feedback of cross coupling structure.
Transistor M
9drain electrode output signal receive transistor M
10grid, M
10by V
bpbiased M
3current offset is provided.M
10drain electrode output signal, through M
11, M
13and M
12, M
14the two-stage inverter of composition, exports reset signal V
rst, and by electric capacity C
2filtering clutter.
The in-phase input end V of comparator
ipthe time delay voltage signal V that reception delay circuit 21 exports
delay, i.e. V
iptogether with being coupled in the source electrode of the PMOS transistor of delay circuit 21.The inverting input V of comparator
inby resistance R
2and C
1the magnitude of voltage (magnitude of voltage of this setting is provided by biasing circuit 23) of first-order filtering network insertion one setting of composition, and R
2and C
1time constant compared with the delay time of delay circuit 21, negligible.The above-mentioned comparison circuit combining positive feedback and filter network, can avoid the reset signal of the mistake produced due to the fluctuation of supply voltage effectively, can realize highly reliable reset signal and export.
Biasing circuit 23, for providing the first bias voltage and the second bias voltage for delay circuit 21, simultaneously for comparison circuit 22 provides magnitude of voltage input and the transistor M of setting
2with M
3required bias voltage.Biasing circuit can produce two-way bias voltage, and a road is for putting on M
pthe first bias voltage V of grid
bd, it provides the magnitude of voltage of setting for comparator simultaneously, and a road is for putting on M
pthe second bias voltage V of grid
bp, it by current-mirror structure, is the M of comparator simultaneously
2with M
3bias voltage is provided.Concrete, as shown in Figure 5, by be serially connected with successively input supply voltage both positive and negative polarity between the first biasing resistor R
0, the first diode D
1, the second diode D
0composition bias voltage V
bdoutput circuit, wherein, D
1with equal D
0forward bias, at D
1with D
0couple place output first bias voltage V
bdput on PMOS transistor M
pgrid.Simultaneously as the magnitude of voltage of setting, by filter resistance R
2with the second filter capacitor C
1the first-order filtering network of composition is input to the inverting input of comparator.Utilize diode can be M
pthere is provided a stable reference voltage with comparator, the low-power consumption requirement of circuit can also be met simultaneously.
Further as shown in Figure 5, by be serially connected with successively input supply voltage both positive and negative polarity between transistor seconds M
1with the second biasing resistor R
1composition bias voltage V
bpoutput circuit, wherein, M
1work in saturation region, M
1grid with drain electrode short circuit, its source electrode meets the positive pole avdd of the supply voltage of input, at M
1drain electrode and R
1couple place output second bias voltage V
bpput on PMOS transistor M
pgrid.Simultaneously can as the transistor M in comparison circuit 22
2and M
3bias voltage.Use the transistor of diode structure mainly in order to form current mirror with the transistor in comparator, for comparator provides a stable bias current.The bias circuit construction of the embodiment of the present application is simple, reliable and stable.
For example, when the supply voltage avdd inputted is 1.8V, V
bdbe about 0.7V, and V
bpbe about 1.1V.V
bdreceive the V of delay circuit 21
bend, the M now in delay circuit
pthe grid voltage of pipe is lower, and namely overdrive voltage is comparatively large, and the resistance of equivalent resistance is less, but still pipe area that can be less reaches the resistance of tens.If chip area will be reduced further, can by V
bpreceive the V of delay circuit
bend, the M now in delay circuit
pthe grid voltage of pipe is higher, and namely overdrive voltage is less, and the resistance of equivalent resistance is comparatively large, thus under obtaining time of delay as hereinbefore, can reduce the electric capacity C in delay circuit 21 further
0capacitance, and then reduce the area of domain.
Electrify restoration circuit of the prior art, because needs use very large resistance and electric capacity, causes integrated circuit diagram to increase, cost increase, does not utilize the miniaturization of integrated circuit.In the embodiment of the application, by the large resistance adopting the PMOS transistor equivalence working in linear zone to become, only need configure less electric capacity, just can the delay requirement of realizing circuit.It is also to be noted that the C in comparison circuit
1with C
2all can adopt small capacitances, such as, be not more than 1pF, thus can not impact the chip area of the entirety of circuit, the reliability of reset signal can also be improved simultaneously.
Fig. 6 is the contrast schematic diagram of the simulation result to the embodiment of the present application and comparative examples, and Fig. 7 is the schematic diagram of the chip area of the embodiment of the present application and comparative examples.The validity of the application is described below in conjunction with Fig. 6 and Fig. 7.
In order to contrast effect of the present invention, on the basis of embodiments of the invention, the delay circuit in the present invention is used instead high-ohmic resistor conventional in integrated circuit, all the other parameters of circuit all remain unchanged, example as a comparison.The embodiment of the application emulated together with comparative examples, in emulation, the breadth length ratio of getting the first transistor (i.e. PMOS transistor) is 20 μm/500nm, the first filter capacitor C
0capacitance be 0.8pF, simulation result is as shown in Figure 6.The delay circuit of adjustment the present invention and comparative examples, makes the time of delay of reset signal identical.In test, supply voltage avdd all when 12 μ s, is raised to ceiling voltage 1.8V, and reset signal V
rstwhen being deferred to 23 μ s, by low transition to high level.
The chip area of embodiments of the invention and comparative examples is contrasted, as shown in Figure 7.When time of delay is identical, when with the first bias voltage V
bdwhen putting on delay circuit 21, the chip area of the embodiment of the present application is 149 × 39 μm
2, when with the second bias voltage V
bpwhen putting on delay circuit 21, the chip area of the embodiment of the present application is 134 × 39 μm
2, and the chip area of comparative examples is 320 × 68 μm
2, be less than 1/4 of comparative examples with chip area during the second bias voltage effect, significantly reduce chip area, contribute to the cost reducing integrated circuit.
The electrify restoration circuit of the embodiment of the present application, while the remarkable scaled down version area of pictural surface, can realize reliable and stable work, can be widely used in needing in the integrated circuit of system initialization.Compared with RC reset circuit of the prior art, owing to have employed the hysteresis comparator structure combining filter network, not only can solve false triggering that power supply burr causes and system unstable, and also can realize when power supply slowly rises accurately and reliably resetting.Be easy to apply.
Although the execution mode disclosed by the present invention is as above, the execution mode that described content just adopts for the ease of understanding the present invention, and be not used to limit the present invention.Technical staff in any the technical field of the invention; under the prerequisite not departing from the spirit and scope disclosed by the present invention; any amendment and change can be done what implement in form and in details; but scope of patent protection of the present invention, the scope that still must define with appending claims is as the criterion.
Claims (10)
1., for the electrify restoration circuit in integrated circuit (IC) chip, comprising:
Delay circuit, makes the supply voltage of input form the time delay voltage signal with certain hour delay;
Comparison circuit, receives described time delay voltage signal, exports reset signal when described time delay voltage signal is greater than the magnitude of voltage of setting;
Biasing circuit, for described comparison circuit provides the magnitude of voltage of setting.
2. electrify restoration circuit according to claim 1, is characterized in that, described delay circuit is set to low-pass network, comprises the first transistor and the first filter capacitor;
Described biasing circuit provides the first bias voltage or the second bias voltage to work in linear zone to make it for described the first transistor.
3. electrify restoration circuit according to claim 2, is characterized in that,
Described the first transistor is PMOS transistor, and its source electrode connects the positive pole of the supply voltage of input, and its drain electrode couples with one end of described first filter capacitor, the negative pole of the supply voltage of another termination input of described first filter capacitor;
The grid of described PMOS transistor connects described first bias voltage or the second bias voltage, exports time delay voltage signal in the drain electrode of described PMOS transistor.
4. electrify restoration circuit according to claim 3, it is characterized in that, described biasing circuit comprises the first biasing resistor, the first diode and the second diode between the positive pole of the supply voltage being serially connected with input successively and negative pole, described first diode and the equal forward bias of the second diode, and locate output first bias voltage coupling of they.
5. electrify restoration circuit according to claim 3, it is characterized in that, described biasing circuit also comprises the transistor seconds working in saturation region between the positive pole of the supply voltage being serially connected with input successively and negative pole and the second biasing resistor, the grid of described transistor seconds and drain electrode short circuit, locate output second bias voltage in the drain electrode of described transistor seconds and coupling of described second biasing resistor.
6. electrify restoration circuit according to claim 4, is characterized in that, using described first bias voltage as the magnitude of voltage of described setting.
7. electrify restoration circuit according to claim 6, is characterized in that, described comparison circuit comprises positive feedback hysteresis comparator.
8. electrify restoration circuit according to claim 7, it is characterized in that, the drain electrode of described PMOS transistor is coupled to the in-phase input end of described positive feedback hysteresis comparator, the magnitude of voltage of inverting input by setting described in first-order filtering network insertion of described positive feedback hysteresis comparator.
9. electrify restoration circuit according to claim 8, is characterized in that, described first-order filtering network comprises the second filter capacitor, and the capacitance of described second filter capacitor is not more than 1pF.
10. electrify restoration circuit according to claim 2, is characterized in that, described first filter capacitor comprises mos capacitance, MIM capacitor or MOM capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510800251.2A CN105281724B (en) | 2015-11-19 | 2015-11-19 | For the electrification reset circuit in IC chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510800251.2A CN105281724B (en) | 2015-11-19 | 2015-11-19 | For the electrification reset circuit in IC chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105281724A true CN105281724A (en) | 2016-01-27 |
| CN105281724B CN105281724B (en) | 2018-12-07 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510800251.2A Active CN105281724B (en) | 2015-11-19 | 2015-11-19 | For the electrification reset circuit in IC chip |
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| Country | Link |
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| CN (1) | CN105281724B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634454A (en) * | 2016-02-26 | 2016-06-01 | 北京时代民芯科技有限公司 | Single-particle reinforced power-on reset circuit applicable to SRAM type FPGA for aerospace |
| CN108649934A (en) * | 2018-05-31 | 2018-10-12 | 成都锐成芯微科技股份有限公司 | A kind of hysteresis comparator circuit |
| CN113783557A (en) * | 2021-09-27 | 2021-12-10 | 普冉半导体(上海)股份有限公司 | Chip power-on reset circuit |
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| US6879194B1 (en) * | 2003-08-25 | 2005-04-12 | National Semiconductor Corporation | Apparatus and method for an active power-on reset current comparator circuit |
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| US20140285243A1 (en) * | 2013-03-19 | 2014-09-25 | Fujitsu Semiconductor Limited | Power on reset circuit, power supply circuit, and power supply system |
| CN104378093A (en) * | 2014-11-17 | 2015-02-25 | 锐迪科创微电子（北京）有限公司 | Power-on reset method and circuit using MIPI standard circuit |
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| US6879194B1 (en) * | 2003-08-25 | 2005-04-12 | National Semiconductor Corporation | Apparatus and method for an active power-on reset current comparator circuit |
| CN1949668A (en) * | 2006-10-25 | 2007-04-18 | 华中科技大学 | Retarding comparator circuit of single terminal input |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105634454A (en) * | 2016-02-26 | 2016-06-01 | 北京时代民芯科技有限公司 | Single-particle reinforced power-on reset circuit applicable to SRAM type FPGA for aerospace |
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| CN108649934A (en) * | 2018-05-31 | 2018-10-12 | 成都锐成芯微科技股份有限公司 | A kind of hysteresis comparator circuit |
| CN113783557A (en) * | 2021-09-27 | 2021-12-10 | 普冉半导体(上海)股份有限公司 | Chip power-on reset circuit |
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| Publication number | Publication date |
|---|---|
| CN105281724B (en) | 2018-12-07 |
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