CN105281724B - For the electrification reset circuit in IC chip - Google Patents
For the electrification reset circuit in IC chip Download PDFInfo
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- CN105281724B CN105281724B CN201510800251.2A CN201510800251A CN105281724B CN 105281724 B CN105281724 B CN 105281724B CN 201510800251 A CN201510800251 A CN 201510800251A CN 105281724 B CN105281724 B CN 105281724B
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- electrification reset
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Abstract
The invention discloses a kind of electrification reset circuits in IC chip, including delay circuit, and the supply voltage of input is made to form the delay voltage signal with certain time delay；Comparison circuit receives the delay voltage signal, the output reset signal when the delay voltage signal is greater than the voltage value of setting；Biasing circuit provides the voltage value of setting for the comparison circuit.The electrification reset circuit solves the problems, such as that system caused by power supply burr is unstable while the chip area that circuit is effectively reduced, and also can be realized reliable reset when power supply slowly rises, implementation easy to spread.
Description
Technical field
The present invention relates to technical field of integrated circuits more particularly to a kind of electrification reset electricity in IC chip
Road.
Background technique
In electronic system, electrification reset circuit is one of the circuit module being in daily use, it is able to achieve in power up
Reset signal is generated simultaneously, reset operation is carried out to other modules of circuit, to eliminate when powering on initial circuit module not
Stable state.In the circuit system for containing the units such as register, latch, trigger, power-on reset signal is required to this
A little units are initialized or are reset.
Most of electrification reset circuit is all that reset signal is generated using time delay mechanism, as shown in Figure 1.Fig. 1 is
One basic reset circuit utilizes the delay for realizing signal in RC circuit to the charging of capacitor.This circuit structure exists
Following problem, on the one hand, to guarantee a period of time (about μ s grades) after avdd stablizes, reset circuit ability output reset signal is needed
The time constant for generating the RC circuit of delay is very big, and it is very big (about μ F grades) to allow for capacitor in this way, and big in this way
Capacitor in integrated circuits, will occupy considerable area, lead to the very big rising of cost.On the other hand, capacitor is to burr
The filter effect of signal is limited, if the supply voltage for generating reset signal has biggish fluctuation, it is likely that generates wrong
Accidentally reset signal and make circuit maloperation, cause the unstable of system.
To sum up, the new electrification reset circuit of one kind is needed to solve the above problems.
Summary of the invention
The first technical problem to be solved by the present invention is that need to provide a kind of new electrification reset circuit existing to solve
The maloperation problem of reset circuit.
In order to solve the above-mentioned technical problem, embodiments herein provides a kind of for powering in IC chip
Reset circuit, comprising: delay circuit makes the supply voltage of input form the delay voltage signal with certain time delay；Than
Compared with circuit, the delay voltage signal is received, the output reset signal when the delay voltage signal is greater than the voltage value of setting；
Biasing circuit provides the voltage value of setting for the comparison circuit.
Preferably, the delay circuit is set as low-pass network, including the first transistor and the first filter capacitor；It is described inclined
Circuits provide the first bias voltage or the second bias voltage so that it works in linear zone for the first transistor.
Preferably, the first transistor is PMOS transistor, and source electrode connects the anode of the supply voltage of input, is drained
It is coupled with one end of first filter capacitor, the cathode of the supply voltage of another termination input of first filter capacitor；
The grid of the PMOS transistor connects first bias voltage or the second bias voltage, defeated in the drain electrode of the PMOS transistor
Be delayed voltage signal out.
Preferably, the biasing circuit includes first be sequentially connected in series between the anode and cathode of the supply voltage of input
Biasing resistor, first diode and the second diode, the first diode and the equal forward bias of the second diode, and at them
Coupling at export the first bias voltage.
Preferably, the biasing circuit further includes the work being sequentially connected in series between the anode and cathode of the supply voltage of input
Make in the second transistor and the second biasing resistor of saturation region, the grid of the second transistor and drain electrode are shorted, described the
The second bias voltage is exported at the drain electrode of two-transistor and the coupling of second biasing resistor.
Preferably, using first bias voltage as the voltage value of the setting.
Preferably, the comparison circuit includes positive feedback hysteresis comparator.
Preferably, the drain electrode of the PMOS transistor is coupled to the non-inverting input terminal of the positive feedback hysteresis comparator, institute
The inverting input terminal for stating positive feedback hysteresis comparator passes through the voltage value of setting described in first-order filtering network insertion.
Preferably, the first-order filtering network includes the second filter capacitor, and the capacitance of second filter capacitor is little
In 1pF.
Preferably, first filter capacitor includes mos capacitance, MIM capacitor or MOM capacitor.
Compared with prior art, one or more embodiments in above scheme can have following advantage or beneficial to effect
Fruit:
While the chip area that circuit is effectively reduced, solve the problems, such as that system caused by power supply burr is unstable,
And also can be realized reliable reset when power supply slowly rises, implementation easy to spread.
Other advantages, target and feature of the invention will be illustrated in the following description to a certain extent, and
And to a certain extent, based on will be apparent to those skilled in the art to investigating hereafter, Huo Zheke
To be instructed from the practice of the present invention.Target and other advantages of the invention can be wanted by following specification, right
Specifically noted structure is sought in book and attached drawing to be achieved and obtained.
Detailed description of the invention
Attached drawing is used to provide to the technical solution of the application or further understanding for the prior art, and constitutes specification
A part.Wherein, the attached drawing for expressing the embodiment of the present application is used to explain the technical side of the application together with embodiments herein
Case, but do not constitute the limitation to technical scheme.
Fig. 1 is electrification reset circuit schematic diagram basic in the prior art；
Fig. 2 is the structural schematic diagram of the electrification reset circuit of the embodiment of the present application；
Fig. 3 is the delay circuit schematic diagram of the electrification reset circuit of the embodiment of the present application；
Fig. 4 is the comparison circuit schematic diagram of the electrification reset circuit of the embodiment of the present application；
Fig. 5 is the biasing circuit schematic diagram of the electrification reset circuit of the embodiment of the present application；
Fig. 6 is the contrast schematic diagram to the simulation result of the embodiment of the present application and comparative examples；
Fig. 7 is the schematic diagram of the chip area of the embodiment of the present application and comparative examples.
Specific embodiment
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and examples, how to apply to the present invention whereby
Technological means solves technical problem, and the realization process for reaching relevant art effect can fully understand and implement.This Shen
Please each feature in embodiment and embodiment, can be combined with each other under the premise of not colliding, be formed by technical solution
It is within the scope of the present invention.
As shown in Fig. 2, the electrification reset circuit of the embodiment of the present application includes delay circuit 21, comparison circuit 22 and biased electrical
Road 23, electrification reset circuit receive the supply voltage avdd of input, export stable reset signal Vrst, below with reference to Fig. 3, figure
4, Fig. 5 is described in detail.
Delay circuit 21 is mainly used for that the supply voltage of input is made to form the delay voltage letter with certain time delay
Number, then the delay voltage signal of output is connected to the input terminal of comparison circuit 22.To reduce chip area with save the cost, this Shen
Please embodiment use a kind of delay circuit structure as shown in Figure 3, delay circuit is traditionally arranged to be low-pass network, including work
In the first transistor and the first filter capacitor of linear zone.
Specifically, as shown in figure 3, delay circuit 21 is by being biased in the PMOS tube M of linear zonepWith capacitor C0Composition.It is low at this
In open network, MpSource electrode connect input supply voltage positive avdd, drain electrode and C0One end coupling, C0Another termination
The cathode avss of supply voltage.MpGrid connect the first bias voltage or the second bias voltage, be delayed voltage signal VdelayFrom Mp
Drain electrode output.In above scheme, delay circuit generates certain delay to supply voltage avdd.Due to MpPipe works in linearly
Area, therefore can be equivalent to one tens big resistance, thus lesser first filter capacitor that need to only arrange in pairs or groups, so that it may realize
The delay of power-on time needed for reset circuit.
Further, pass through MpGrid voltage VbTo MpPipe is controlled, and can produce the different equivalent big electricity of resistance value
Resistance, to flexibly control the delay time of delay circuit 21.First bias voltage and the second bias voltage are by biasing circuit 23
It generates.MpEquivalent resistance be inversely proportional with the voltage for being applied to its grid.Work as MpIt is worked with biggish overdrive voltage linear
Equivalent big resistance may be implemented in Qu Shi.Work as MpWith the work of lesser overdrive voltage in linear zone, it may be implemented bigger
Equivalent big resistance to further reduce the volume of capacitor, and then reduces the area of domain.
It is also to be noted that the implementation of the first filter capacitor in above-mentioned delay circuit 21 has multiple choices,
For example, can use PMOS transistor or NMOS transistor to form mos capacitance as C0, further, it is not limited to
Mos capacitance can also be common MIM capacitor, MOM capacitor etc. in integrated circuit.Since the PMOS using linear zone work is brilliant
Big resistance in the equivalent integrated circuit of body pipe, greatly reduces the area of circuit layout.With high resistant electricity in use integrated circuit
The scheme of resistance is compared, and chip area of the invention is about reduced to a quarter of former scheme, significantly reduces cost, improves collection
At the competitiveness of circuit.
Comparison circuit 22, the delay voltage signal that reception delay circuit 21 exports, when delay voltage signal is greater than setting
Output reset signal resets circuit when voltage value.Fig. 4 is that the comparison of the electrification reset circuit of the embodiment of the present application is electric
Road schematic diagram, it can be seen that in the present embodiment, comparison circuit 22 uses positive feedback hysteresis comparator structure.Specifically, crystal
Pipe M4、M5The Differential Input of comparator is formed to pipe, wherein M4For non-inverting input terminal, M5For inverting input terminal.Transistor M2As
Tail current source, drain electrode and M4And M5Source electrode be coupled together, M2Bias voltage VbpIt is provided by biasing circuit 23, VbpSimultaneously
It is also transistor M3Bias voltage is provided.Transistor M6、M9Grid be respectively couple to drain electrode together with, form diode structure
Load.
Comparator realizes lag function using positive feedback.Transistor M7And M8Grid respectively with M6And M9Grid
Pole coupling, M7And M8Drain electrode respectively with M5And M4Drain electrode coupling, M7And M8Source electrode be coupled together connecing the electricity of input
The cathode avss of source voltage, constitutes the positive feedback of cross coupling structure.
Transistor M9Drain electrode output signal be connected to transistor M10Grid, M10By VbpThe M of biasing3Current offset is provided.
M10Drain electrode output signal, by M11、M13And M12、M14The two-stage phase inverter of composition, output reset signal Vrst, and by capacitor C2
Filtering clutter.
The non-inverting input terminal V of comparatoripThe delay voltage signal V that reception delay circuit 21 exportsdelay, i.e. VipWith delay
The source electrode of the PMOS transistor of circuit 21 is coupled together.The inverting input terminal V of comparatorinPass through resistance R2And C1The one of composition
The voltage value (voltage value of the setting is provided by biasing circuit 23) of one setting of rank filter network access, and R2And C1Time it is normal
Number can be ignored compared with the delay time of delay circuit 21.It is above-mentioned to combine positive feedback and the comparison of filter network is electric
Road, the fluctuation due to supply voltage can be effectively avoided and generate mistake reset signal, can be realized highly reliable answer
Position signal output.
Biasing circuit 23, for providing the first bias voltage and the second bias voltage for delay circuit 21, while to compare
Circuit 22 provides voltage value input and the transistor M of setting2With M3Required bias voltage.It is inclined that biasing circuit can produce two-way
Voltage is set, all the way to be applied to MpGrid the first bias voltage Vbd, the voltage value of setting is provided simultaneously for comparator, one
Road is to be applied to MpGrid the second bias voltage Vbp, pass through current-mirror structure simultaneously, be the M of comparator2With M3It provides inclined
Set voltage.Specifically, as shown in figure 5, the first biasing resistor by being sequentially connected in series between the positive and negative anodes of the supply voltage of input
R0, first diode D1, the second diode D0Form bias voltage VbdOutput circuit, wherein D1With equal D0Forward bias, in D1
With D0Coupling at export the first bias voltage VbdIt is applied to PMOS transistor MpGrid.Voltage value as setting simultaneously,
Pass through filter resistance R2With the second filter capacitor C1Inverting input terminal of the first-order filtering network inputs of composition to comparator.It utilizes
Diode can be MpA stable reference voltage is provided with comparator, while the low-power consumption requirement of circuit can also be met.
Further as shown in figure 5, second transistor M by being sequentially connected in series between the positive and negative anodes of the supply voltage of input1
With the second biasing resistor R1Form bias voltage VbpOutput circuit, wherein M1Work in saturation region, M1Grid and drain electrode it is short
It connects, source electrode meets the positive avdd of the supply voltage of input, in M1Drain electrode and R1Coupling at export the second bias voltage Vbp
It is applied to PMOS transistor MpGrid.It can simultaneously serve as the transistor M in comparison circuit 222And M3Bias voltage.It uses
The transistor of diode structure provides a stabilization primarily to the transistor composition current mirror in comparator for comparator
Bias current.The bias circuit construction of the embodiment of the present application is simple, reliable and stable.
For example, when the supply voltage avdd of input is 1.8V, VbdAbout 0.7V, and VbpAbout 1.1V.VbdIt is connected to
The V of delay circuit 21bIt holds, at this time the M in delay circuitpThe grid voltage of pipe is lower, i.e., overdrive voltage is larger, equivalent resistance
Resistance value it is smaller, but still can be reached with lesser pipe area tens resistance value.If further decreasing chip area,
It can be by VbpIt is connected to the V of delay circuitbIt holds, at this time the M in delay circuitpThe grid voltage of pipe is higher, i.e., overdrive voltage compared with
Small, the resistance value of equivalent resistance is larger, to obtain under delay time as hereinbefore, can further decrease delay circuit 21
In capacitor C0Capacitance, and then reduce domain area.
Electrification reset circuit in the prior art, due to needing to lead to integrated circuit using very big resistance and capacitor
Domain increases, and cost increase does not utilize the miniaturization of integrated circuit.In embodiments herein, by using working in line
Property area PMOS transistor it is equivalent at big resistance, only need to configure lesser capacitor, so that it may realize the delay requirement of circuit.Also
It should be noted that the C in comparison circuit1With C2Small capacitances can be used, such as no more than 1pF, because without to the whole of circuit
The chip area of body impacts, while can also improve the reliability of reset signal.
Fig. 6 is to the contrast schematic diagram of the simulation result of the embodiment of the present application and comparative examples, and Fig. 7 is the embodiment of the present application
With the schematic diagram of the chip area of comparative examples.Illustrate the validity of the application below with reference to Fig. 6 and Fig. 7.
In order to compare effect of the invention, on the basis of the embodiment of the present invention, the delay circuit in the present invention is changed
With high-ohmic resistor common in integrated circuit, remaining parameter of circuit is remained unchanged, as a comparison example.By the implementation of the application
Example emulated together with comparative examples, in emulation, take the first transistor (i.e. PMOS transistor) breadth length ratio be 20 μm/
500nm, the first filter capacitor C0Capacitance be 0.8pF, simulation result is as shown in Figure 6.The adjustment present invention and comparative examples
Delay circuit keeps the delay time of reset signal identical.In test, supply voltage avdd in 12 μ s, is raised to ceiling voltage
1.8V, and reset signal VrstWhen being deferred to 23 μ s, high level is jumped to by low level.
The chip area of the embodiment of the present invention and comparative examples is compared, as shown in Figure 7.It is identical in delay time
In the case where, when with the first bias voltage VbdWhen being applied to delay circuit 21, the chip area of the embodiment of the present application is 149 × 39
μm2, when with the second bias voltage VbpWhen being applied to delay circuit 21, the chip area of the embodiment of the present application is 134 × 39 μm2,
And the chip area of comparative examples is 320 × 68 μm2, chip area when with the effect of the second bias voltage is less than comparative examples
1/4, chip area is significantly reduced, the cost for reducing integrated circuit is facilitated.
The electrification reset circuit of the embodiment of the present application can be realized reliable and stable while being reduced significantly chip area
Work, can be widely applied to need in the integrated circuit of system initialization.Compared with RC reset circuit in the prior art,
Combine the hysteresis comparator structure of filter network due to using, not only can solve false triggering caused by power supply burr and
System is unstable, and also can be realized when power supply slowly rises and accurately and reliably reset.Application easy to spread.
Although disclosed herein embodiment it is as above, the content is only to facilitate understanding the present invention and adopting
Embodiment is not intended to limit the invention.Any those skilled in the art to which this invention pertains are not departing from this
Under the premise of the disclosed spirit and scope of invention, any modification and change can be made in the implementing form and in details,
But scope of patent protection of the invention, still should be subject to the scope of the claims as defined in the appended claims.
Claims (8)
1. a kind of electrification reset circuit in IC chip, comprising:
Delay circuit makes the supply voltage of input form the delay voltage signal with certain time delay；
Comparison circuit receives the delay voltage signal, and when the delay voltage signal is greater than the voltage value of setting, output is multiple
Position signal；
Biasing circuit provides the voltage value of setting for the comparison circuit,
Wherein, the delay circuit is set as low-pass network, including the first transistor and the first filter capacitor；
The biasing circuit generates different the first bias voltages and the second bias voltage of two-way, to be selectively described first
Transistor provides first bias voltage or second bias voltage so that it works in linear zone,
Wherein, the first transistor is PMOS transistor, and source electrode connects the anode of the supply voltage of input, drain electrode with it is described
One end of first filter capacitor couples, the cathode of the supply voltage of another termination input of first filter capacitor；
The grid of the PMOS transistor connects first bias voltage or the second bias voltage, in the leakage of the PMOS transistor
Pole output delay voltage signal.
2. electrification reset circuit according to claim 1, which is characterized in that the biasing circuit includes being sequentially connected in series in defeated
The first biasing resistor, first diode and the second diode between the anode and cathode of the supply voltage entered, the described 1st
Pole pipe and the equal forward bias of the second diode, and first bias voltage is exported at their coupling.
3. electrification reset circuit according to claim 1, which is characterized in that the biasing circuit further include be sequentially connected in series in
The second transistor for working in saturation region and the second biasing resistor between the anode and cathode of the supply voltage of input, described
The grid of two-transistor and drain electrode are shorted, and are exported at the drain electrode of the second transistor and the coupling of second biasing resistor
Second bias voltage.
4. electrification reset circuit according to claim 2, which is characterized in that set described in using first bias voltage
Fixed voltage value.
5. electrification reset circuit according to claim 4, which is characterized in that the comparison circuit includes positive feedback sluggishness ratio
Compared with device.
6. electrification reset circuit according to claim 5, which is characterized in that the drain electrode of the PMOS transistor is coupled to institute
The non-inverting input terminal of positive feedback hysteresis comparator is stated, the inverting input terminal of the positive feedback hysteresis comparator passes through first-order filtering net
Network accesses the voltage value of the setting.
7. electrification reset circuit according to claim 6, which is characterized in that the first-order filtering network includes the second filtering
The capacitance of capacitor, second filter capacitor is not more than 1pF.
8. electrification reset circuit according to claim 1, which is characterized in that first filter capacitor include mos capacitance,
MIM capacitor or MOM capacitor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510800251.2A CN105281724B (en) | 2015-11-19 | 2015-11-19 | For the electrification reset circuit in IC chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510800251.2A CN105281724B (en) | 2015-11-19 | 2015-11-19 | For the electrification reset circuit in IC chip |
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| CN105281724A CN105281724A (en) | 2016-01-27 |
| CN105281724B true CN105281724B (en) | 2018-12-07 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105634454B (en) * | 2016-02-26 | 2018-07-06 | 北京时代民芯科技有限公司 | A kind of electrification reset circuit reinforced suitable for aerospace with the single-particle of SRAM type FPGA |
| CN108649934A (en) * | 2018-05-31 | 2018-10-12 | 成都锐成芯微科技股份有限公司 | A kind of hysteresis comparator circuit |
| CN113783557A (en) * | 2021-09-27 | 2021-12-10 | 普冉半导体(上海)股份有限公司 | Chip power-on reset circuit |
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| US6879194B1 (en) * | 2003-08-25 | 2005-04-12 | National Semiconductor Corporation | Apparatus and method for an active power-on reset current comparator circuit |
| CN1949668A (en) * | 2006-10-25 | 2007-04-18 | 华中科技大学 | Retarding comparator circuit of single terminal input |
| CN102882497A (en) * | 2012-09-27 | 2013-01-16 | 电子科技大学 | Low-power-consumption high-reliability electrification resetting circuit |
| CN104378093A (en) * | 2014-11-17 | 2015-02-25 | 锐迪科创微电子（北京）有限公司 | Power-on reset method and circuit using MIPI standard circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6118599B2 (en) * | 2013-03-19 | 2017-04-19 | 富士通株式会社 | Power-on reset circuit, power supply circuit and power supply system |
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- 2015-11-19 CN CN201510800251.2A patent/CN105281724B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6879194B1 (en) * | 2003-08-25 | 2005-04-12 | National Semiconductor Corporation | Apparatus and method for an active power-on reset current comparator circuit |
| CN1949668A (en) * | 2006-10-25 | 2007-04-18 | 华中科技大学 | Retarding comparator circuit of single terminal input |
| CN102882497A (en) * | 2012-09-27 | 2013-01-16 | 电子科技大学 | Low-power-consumption high-reliability electrification resetting circuit |
| CN104378093A (en) * | 2014-11-17 | 2015-02-25 | 锐迪科创微电子（北京）有限公司 | Power-on reset method and circuit using MIPI standard circuit |
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