CN106444943B - Voltage generation circuit - Google Patents
Voltage generation circuit Download PDFInfo
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- CN106444943B CN106444943B CN201510485966.3A CN201510485966A CN106444943B CN 106444943 B CN106444943 B CN 106444943B CN 201510485966 A CN201510485966 A CN 201510485966A CN 106444943 B CN106444943 B CN 106444943B
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Abstract
Voltage generation circuit includes the first capacitance, the second capacitance, first switch, second switch, third switch and the 4th switch.First switch is coupled between the first end of input terminal and the first capacitance and is controlled by first control signal.Second switch is coupled between the first end of the first capacitance and the 3rd end of the second capacitance and is controlled by second control signal.3rd switch is coupled between the second end of ground terminal and the first capacitance and is controlled by the 3rd control signal.4th switch is coupled between the second end of the first capacitance and the 4th end of the second capacitance and is controlled by the 4th control signal.4th control signal has from output voltage level to the amplitude of oscillation of ground voltage level, and when the 4th control signal is output voltage level, the 4th switch is not turned on, and when the 4th control signal is ground voltage level, the 4th switch conduction.
Description
Technical field
This exposure relates to a kind of voltage generation circuit, and overvoltage (over-stress) is avoided more particularly to one kind
Voltage generation circuit.
Background technology
Charge pump (charge pump) can be used to provide voltage for known voltage generation circuit.Voltage generation circuit
Charge pump would generally control the charge or discharge of capacitance using some switches.For example, it is in the current potential of an input voltage
The current potential of positive VDD and output voltage is in the voltage generation circuit of negative VDD, in order to ensure these switches can be fully on and complete
Close, each endpoint of these switches may must be operated between negative potential-VDD to positive potential+VDD.In another example
In, it is positive VDD and during the current potential of output voltage is the voltage generation circuit of 2 times of VDD in the current potential of an input voltage, in order to ensure
These switches can be fully on and be completely closed, and each endpoint of these switches may must be operated between 0 volt~2 times VDD
Current potential.For above-mentioned two, the both ends of some switches may must endure as the voltage difference of 2 times of VDD, this may result in these
The damage of switch.It is to use high voltage device as switch to be used for solving one of above-mentioned method of overvoltage problem at present, to hold
By higher voltage difference.But this method can cause the holistic cost of voltage generation circuit to increase.Therefore, how without using
A kind of voltage generation circuit for avoiding the problem that overvoltage is provided under the premise of high voltage device, and actually industry is eager to solve.
The content of the invention
According to an embodiment of this exposure, there is provided a kind of voltage generation circuit.Voltage generation circuit includes the first capacitance, the
Two capacitances, first switch, second switch, third switch and the 4th switch.First capacitance has first end and second end.Second
Capacitance has the 3rd end and the 4th end.3rd end is couple to ground terminal, and the 4th end is couple to an output terminal.Ground terminal has ground connection
Voltage level, output terminal have output voltage level.First switch is coupled between the first end of input terminal and the first capacitance, and
It is controlled by first control signal.Input terminal has input voltage level.Second switch is coupled to the first end of the first capacitance and the
Between 3rd end of two capacitances, and it is controlled by second control signal.3rd switch is coupled to the second of ground terminal and the first capacitance
Between end, and it is controlled by the 3rd control signal.4th switch is coupled to the second end of the first capacitance and the 4th end of the second capacitance
Between, and it is controlled by the 4th control signal.When first switch and three switch conductions, second switch is not led with the 4th switch
It is logical, and when first switch is not turned on the 3rd switch, second switch and the 4th switch conduction.4th control signal has from defeated
Go out voltage level to the amplitude of oscillation of ground voltage level, when the 4th control signal is output voltage level, the 4th switch is not turned on,
And when the 4th control signal is ground voltage level, the 4th switch conduction.
According to another embodiment of this exposure, there is provided another voltage generation circuit.Voltage generation circuit includes the first electricity
Appearance, first switch, second switch, third switch and the 4th switch.First capacitance has first end and second end.First switch
It is coupled between the first end of input terminal and the first capacitance, and is controlled by first control signal.Input terminal has input voltage position
It is accurate.Second switch is coupled between first end and the output terminal of the first capacitance, and is controlled by second control signal.Output terminal has
One output voltage level.3rd switch is coupled between the second end of ground terminal and the first capacitance, and is controlled by the 3rd control letter
Number, ground terminal has ground voltage level.4th switch is coupled between second end and the input terminal of the first capacitance, and is controlled by
4th control signal.When first switch and three switch conductions, second switch is not turned on the 4th switch, and works as first switch
When being not turned on the 3rd switch, second switch and the 4th switch conduction.Second control signal be with from input voltage level to
The amplitude of oscillation of output voltage level, when second control signal is output voltage level, second switch is not turned on, and when the second control
When signal is input voltage level, second switch conducting.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and coordinate institute's accompanying drawings
It is described in detail below.
Brief description of the drawings
Fig. 1 show the voltage generation circuit schematic diagram according to this exposure first embodiment.
Fig. 2A and Fig. 2 B show equivalent circuit diagram of the voltage generation circuit in period 1 and second round of Fig. 1.
Fig. 3 show the schematic diagram that the output voltage of the voltage generation circuit of Fig. 1 changes over time.
Fig. 4 A and Fig. 4 B show operation of each switch in the voltage generation circuit of Fig. 1 in period 1 and second round
The schematic diagram of voltage level.
Fig. 5 show the sequence diagram of the control signal respectively switched in the voltage generation circuit of Fig. 1.
Fig. 6 show the voltage generation circuit schematic diagram according to this exposure second embodiment.
Fig. 7 A and Fig. 7 B show equivalent circuit diagram of the voltage generation circuit in period 1 and second round of Fig. 6.
Fig. 8 A and Fig. 8 B show operation of each switch in the voltage generation circuit of Fig. 6 in period 1 and second round
The schematic diagram of voltage level.
Fig. 9 show the sequence diagram of the control signal respectively switched in the voltage generation circuit of Fig. 6.
Embodiment
Fig. 1 show the circuit diagram of the voltage generation circuit 100 according to this exposure first embodiment.In this embodiment
In, voltage generation circuit 100 is a negative voltage generator, comprising an input terminal Vin, capacitance C1, capacitance C2, switch M1~M4,
An and output end vo ut.Capacitance C1 has first end N1 and second end N2.Capacitance C2 has first end N3 and second end N4.Electricity
The first end N3 for holding C2 is couple to ground terminal GND, and second end N4 is couple to output end vo ut.Ground terminal GND has a ground connection
Voltage level, is, for example, 0 (V).In one embodiment, output end vo ut has an output voltage level, is, for example ,-VDD (V).
Switch M1 is coupled between input terminal Vin and the first end N1 of capacitance C1, and is controlled by control signal S1.Input terminal Vin has
One input voltage level, is, for example, VDD (V).Switch M2 be coupled to capacitance C1 first end N1 and capacitance C2 first end N3 it
Between, and it is controlled by control signal S2.Switch M3 is coupled between ground terminal GND and the second end N2 of capacitance C1, and is controlled by control
Signal S3 processed.Switch M4 is coupled between the second end N4 of second end N2 and capacitance C2 of capacitance C1, and is controlled by control signal
S4.When switch M1 is turned on switch M3, switch M2 and switch M4 are not turned on.Similarly, when switching M1 and switch M3 is not turned on,
Switch M2 is turned on switch M4.
In detail, Fig. 2A and Fig. 2 B show the voltage generation circuit 100 of Fig. 1 respectively in period 1 and second round
Equivalent circuit diagram.In the period 1, switch M1 is turned on switch M3, and is switched M2 and switch M4 and be not turned on.At this time, voltage
As shown in Figure 2 A, input voltage VDD charges capacitance C1 to the equivalent circuit of generation circuit 100.And in the second cycle, switch M1
When being not turned on switch M3, and switch M2 and turned on switch M4.At this time, the equivalent circuit of voltage generation circuit 100 such as Fig. 2 B institutes
Show, capacitance C1 is in parallel with capacitance C2, and the electric charge that capacitance C1 is stored in the period 1 can share capacitance C2 in the second cycle.
Please continue to refer to Fig. 3, Fig. 3 show the schematic diagram that the voltage of the output end vo ut of voltage generation circuit 100 changes over time.By
By lasting four switches of switching in the period 1 and in second round, the voltage of output end vo ut can be by initial voltage level
0 (V) is little by little adjusted to the voltage level of-VDD.However, Fig. 3 is only schematic diagram, during the charging of the voltage of output end vo ut
Between length and the voltage level that charges every time according to capacitance C1 and capacitance C2 and the parameter of M1~M4 can be switched and be determined, the present invention
It is not limited with the level and time that are indicated on scheming.
That is, when switching M1 and turn on switch M3, and switch M2 and switch M4 when being not turned on, the second of capacitance C1
The voltage level for holding N2 is ground voltage level, that is, the voltage level of the second end N4 of 0 (V), capacitance C2 are output voltage
Level, that is,-VDD, and control signal S4 is output voltage level, that is,-VDD.On the other hand, as switch M1 and switch
M3 is not turned on, and switch M2 with switch M4 turn on when, the voltage level of the second end N2 of capacitance C1 is output voltage level, also
It is-VDD, the voltage level of the 4th end N4 of capacitance C2 is output voltage level, that is,-VDD, and control signal S4 is ground connection
Voltage level, that is, 0 (V).Therefore, in the case where switch M4 is conductive and nonconductive, the voltage position that M4 both ends are born is switched
Standard is all between 0~-VDD, therefore the switch M4 of voltage generation circuit 100 can be will not (end-point voltage be poor in the case of overvoltage
Not less than VDD) normally turn on closing and output voltage can be produced.Therefore, high voltage device can be without the use of as switch M4
And the cost of circuit can be reduced.
The hereby switching control of switch of the account for voltage generation circuit 100 in period 1 and second round as an example below
System.Fig. 4 A and Fig. 4 B are respectively shown in the operation voltage in period 1 and second round, respectively switched in voltage generation circuit 100
The voltage level schematic diagram of level and each endpoint.Fig. 4 A and Fig. 4 B will illustrate in the lump with reference to Fig. 1.In this embodiment, open
It is, for example, p-type gold oxygen half electric crystal (PMOS) to close M1, and switch M2, switch M3 and switch M4 are, for example, N-type gold oxygen half electric crystal
(NMOS)。
Referring to Fig. 5, Fig. 5 show the sequence diagram of control signal S1~S4 of voltage generation circuit 100.T1 is represented
Period 1, T2 represent second round.As shown in figure 5, control signal S1 and control signal S2 has from ground voltage level 0
(V) to the amplitude of oscillation of input voltage level VDD, control signal S3 is with from output voltage level-VDD to input voltage level VDD
The amplitude of oscillation, control signal S4 have from output voltage level-VDD to the amplitude of oscillation of ground voltage level 0 (V).
In the period 1, as shown in Figure 4 A, the gate terminal receiving voltage level for switching M1 is the control signal S1 of 0 (V),
And the input voltage that the source terminal receiving voltage level for switching M1 is VDD.Therefore switch M1 is switched on (ON), and switchs the leakage of M1
Extremely the voltage level of (N1 i.e. shown in Fig. 1) is VDD.At this time, switch the voltage level of each endpoint operation of M1 0~
Between VDD, that is, switch each endpoints of M1 between voltage difference not less than situations of the VDD without having overvoltage.Switch M3's
Gate terminal receiving voltage level is the control signal S3 of VDD, and because switch M3 is conducting (ON), therefore the source terminal for switching M3 is
Ground voltage level 0 (V), the voltage level for switching the drain electrode end of M3 are 0 (V) because being coupled to ground.At this time, each end of M3 is switched
The voltage level of point is also between 0~VDD, therefore the voltage difference switched between each endpoint of M3 there will not be not less than VDD
The situation of voltage.The gate terminal receiving voltage level for switching M2 is the control signal S2 of 0 (V), and switchs the electricity of the source terminal of M2
Pressure level is 0 (V) because being coupled to ground, and the voltage level for switching the drain electrode end (N1 i.e. shown in Fig. 1) of M2 is VDD, therefore
Switch M2 is to be not turned on (OFF).At this time, the voltage level of each endpoint of M2 is switched also between 0~VDD, that is, switch M2
Voltage difference between each endpoint is also not less than situations of the VDD without having overvoltage.Switch the gate terminal receiving voltage level of M4
For the control signal S4 of-VDD, and the voltage level for switching the source terminal of M4 is-VDD, and the drain electrode end for switching M4 is ground voltage
Level 0 (V), therefore M4 is switched to be not turned on (OFF).At this time, switch the voltage level of each endpoint operation of M4-VDD~0 it
Between, therefore the voltage difference between each endpoints of M4 is switched also not less than situations of the VDD without having overvoltage.
In the second cycle, as shown in Figure 4 B, the gate terminal receiving voltage level for switching M2 is the control signal S2 of VDD,
And the source terminal for switching M2 is ground voltage level 0 (V) because being coupled to ground, the drain electrode end for switching M2 is ground voltage level 0
(V), therefore switch M2 is conducting.At this time, the voltage level of each endpoint of M2 is switched also between 0~VDD, therefore switchs each of M2
Voltage difference between endpoint there will not be the situation of overvoltage not less than VDD.The gate terminal receiving voltage level for switching M4 is 0
(V) control signal S4, and the source terminal for switching M4 is output voltage level-VDD, therefore M4 is switched as conducting, and switch M4
Drain electrode end be output voltage level-VDD.At this time, the voltage level of each endpoint of M4 is switched between-VDD~0, therefore is switched
Voltage difference between each endpoint of M4 there will not be the situation of overvoltage not less than VDD.Switch the gate terminal receiving voltage of M1
Level is the control signal S1 of VDD, and the input voltage that the source terminal receiving voltage level for switching M1 is VDD, therefore, switchs M1
It is not turned on (OFF), and the voltage level for switching the drain electrode end of M1 is 0 (V).At this time, the voltage level of each endpoint of M1 is switched 0
Between~VDD, therefore the voltage difference between each endpoint of M1 is switched not less than situations of the VDD without having overvoltage.Switch M3's
Gate terminal Rreceive output voltage level be-VDD control signal S3, and the source terminal for switching M3 be output voltage level for-
VDD, and the voltage level for switching the drain electrode end of M3 is ground voltage level 0 (V) because being coupled to ground, therefore M3 is switched not lead
It is logical.At this time, the voltage level of each endpoint of M3 is switched also between-VDD~0, therefore switchs the voltage difference between each endpoint of M3
It there will not be the situation of overvoltage not less than VDD.
As shown in the above, four of voltage generation circuit 100 switch M1~M4 are in the period 1 and second round
The voltage level of middle operation is all between 0~VDD, or between-VDD~0, therefore switch M1~M4 all can be will not be excessively electric
(voltage difference is not less than VDD) is normally turned on closing and can be produced output voltage in the case of pressure.
Referring again to Fig. 1, in another embodiment, voltage generation circuit 100 can more include a buffer 110.Buffering
The input terminal of device 110 is couple to the second end N2 of capacitance C1, and produces control signal S4 with controlling switch M4.Buffer 110 is inclined
The ground voltage level 0 (V) of ground terminal GND and the output voltage level of output end vo ut are pressed on, for example, buffer 110 is just
Power input is biased in ground voltage level 0 (V), and the negative supply input terminal of buffer 110 is then coupled to output end vo ut,
To be biased in the quasi- VDD of output voltage.That is,-VDD the levels of this buffer 110 bias can be by the defeated of voltage generation circuit 100
Outlet Vout is provided.In one embodiment, this buffer 110 may be, for example, a phase inverter, to produce the second end of capacitance C1
The inversion signal of N2.In this embodiment, in the period 1, the voltage level of the second end N2 of capacitance C1 is (high-order for 0 (V)
It is accurate), the control signal S4 that then corresponding output voltage level is-VDD (low level) of buffer 110.In the second cycle, capacitance C1
The voltage level of second end N2 be-VDD (low level), then corresponding output voltage level is 0 (V) (high levels) to buffer 110
Control signal S4.When the transient response of second round, the voltage level of output end vo ut is at the beginning 0 (V), switchs M4's
The voltage level of drain electrode end (i.e. N2) is-VDD (V), and the gate terminal receiving voltage level for switching M4 is the control signal S4 of 0 (V),
And the voltage level for switching M4 source terminals is 0 (V), at this time switch M4 somewhat turn on and have some electric currents by, and cause switch
The voltage level of M4 source terminals, that is, the voltage level of output end vo ut, understand the gradually negative with drain electrode end (N2)
It is close.And when the voltage level of switch M4 source terminals is changed into-VDD, and the voltage level for switching the gate terminal of M4 is 0 (V), then
Switch M4 can be turned on normally.
Fig. 6 show the circuit diagram of the voltage generation circuit 500 according to this exposure second embodiment.In this embodiment
In, voltage generation circuit 500 is a voltage multiplie, includes an output terminal Vin, capacitance C3, switch M5~M8 and an output terminal
Vout.Input terminal Vin has an input voltage level, is, for example, VDD (V).Capacitance C3 has first end N5 and second end N6.Open
Close M5 to be coupled between input terminal Vin and the first end N5 of capacitance C3, and be controlled by control signal S5.Switch M6 is coupled to capacitance
Between the first end N5 and output end vo ut of C3, and it is controlled by control signal S6.Switch M7 is coupled to ground terminal GND and capacitance C3
Second end N6 between, and be controlled by control signal S7.Ground terminal GND has a ground voltage level, is, for example, 0 (V).Switch
M8 is coupled between the second end N6 input terminals Vin of capacitance C3, and is controlled by control signal S8.Output end vo ut has an output
Voltage level, is, for example, 2VDD (V).When switch M5 is turned on switch M7, switch M6 and switch M8 are not turned on.Similarly, when opening
When pass M5 is not turned on switch M7, switch M6 is turned on switch M8.
In detail, be respectively voltage generation circuit 500 shown in Fig. 7 A and Fig. 7 B period 1 and second round etc.
Imitate circuit diagram.In the period 1, switch M5 is turned on switch M7, and is switched M6 and switch M8 and be not turned on.At this time, voltage produces
As shown in Figure 7 A, input voltage VDD charges capacitance C3 to the equivalent circuit of circuit 500.And in the second cycle, switch M5 is with opening
Close M7 to be not turned on, and switch M6 and turned on switch M8.At this time, the equivalent circuit of voltage generation circuit 500 as shown in Figure 7 B, capacitance
The electric charge that C3 is stored in the period 1 still can remain unchanged.Similarly, by lasting in the period 1 and second week
Interim four switch M5~M8 of switching, the voltage of output end vo ut can little by little be adjusted to the voltage level of 2VDD.
That is, when switch M5 is turned on switch M7, and switch M6 is not turned on switch M8, the second end of capacitance C3
The voltage level of N6 is ground voltage level because being coupled to ground, that is, 0 (V).On the other hand, when switch M5 is with switching M7 not
Conducting, and when switching M6 and being turned on switching M8, the voltage level of the second end N6 of capacitance C3 is defeated because being coupled to input terminal Vin
Enter voltage level, that is, VDD, and the voltage level of the first end N5 of capacitance C3 is output voltage level, that is, 2VDD, and
Control signal S6 is input voltage level, that is, VDD.Therefore, in the case where switch M6 is conductive and nonconductive, switch M6 is held
The voltage received is between VDD~2VDD, therefore the switch S6 of voltage generation circuit 500 can be will not (electricity in the case of voltage overload
Pressure difference is not less than VDD) normally turn on closing and output voltage can be produced.Therefore, also it is used as and opens without the use of high voltage device
Close M6 and the cost of circuit can be reduced.
The hereby switching control of switch of the account for voltage generation circuit 500 in period 1 and second round as an example below
System.It is respectively the operation respectively switched the electricity of voltage generation circuit 500 in period 1 and second round shown in Fig. 8 A and Fig. 8 B
Press level and each end-point voltage level schematic diagram.Fig. 8 A and Fig. 8 B will illustrate in the lump with reference to Fig. 6.In this embodiment, open
It is, for example, p-type gold oxygen half electric crystal (PMOS) to close M5, switch M6 and switch M8, and switch M7 is, for example, N-type gold oxygen half electric crystal
(NMOS)。
Referring to Fig. 9, Fig. 9 show the sequence diagram of control signal S1~S4 of voltage generation circuit 500.T1 is represented
Period 1, T2 represent second round.As shown in figure 9, control signal S5 has from ground voltage level 0 (V) to output voltage
The amplitude of oscillation of level 2VDD, control signal S6 have from input voltage level VDD to the amplitude of oscillation of output voltage level 2VDD.Control letter
Number S7 and control signal S8 has the amplitude of oscillation from ground voltage level 0 (V) to input voltage level VDD.
In the period 1, as shown in Figure 8 A, the gate terminal receiving voltage level for switching M5 is the control signal S5 of 0 (V),
Because M5 is switched as conducting (ON), and the drain terminal voltage level of first switch M1 is VDD because being coupled to input terminal Vin,
Therefore the voltage level for switching the source terminal of M5 is VDD.At this time, the voltage difference between each endpoint of M5 is switched between 0~VDD,
Situation without having overvoltage.The gate terminal receiving voltage level for switching M7 is the control signal S7 of VDD, and switchs the source of M7
Extreme voltage level is 0 (V) because being coupled to ground.Therefore, M7 is switched as conducting (ON), switchs the electricity of the drain electrode end (N6) of M7
Therefore it is 0 (V) to press level.At this time, switch the voltage level of each endpoint of M7 between 0~VDD, thus switch M7 each endpoint it
Between voltage difference there will not be the situation of overvoltage not less than VDD.The gate terminal receiving voltage level for switching M6 is 2VDD's
Control signal S6, and the voltage level for switching the source terminal (N5) of M6 is VDD, the voltage level for switching the drain electrode end of M6 is
2VDD, therefore switch M6 and be not turned on (OFF).At this time, the voltage level of each endpoint operation of M6 is switched between VDD~2VDD,
The voltage difference between each endpoints of M6 is namely switched also not less than situations of the VDD without having overvoltage.Switch the gate terminal of M8
Receiving voltage level is the control signal S8 of VDD, and the voltage level for switching the source terminal (N6) of M8 is 0 (V), switchs the leakage of M8
Extreme voltage level is VDD because being coupled to input terminal Vin, therefore switchs M8 and be not turned on (OFF).At this time, each of M8 is switched
The voltage level of endpoint is also between 0~VDD, therefore the voltage difference switched between each endpoint of M8 there will not be not less than VDD
The situation of overvoltage.
In the second cycle, as shown in Figure 8 B, the gate terminal receiving voltage level for switching M6 is the control signal S6 of VDD,
Because M6 is switched as conducting (ON), and the drain electrode end for switching M6 is output voltage level 2VDD, therefore switch the source terminal (N5) of M6
Voltage level be 2VDD.At this time, the voltage level of each endpoint of M6 is switched between VDD~2VDD, therefore switchs each end of M6
Voltage difference between point is not less than VDD and without having the situation of overvoltage.The gate terminal receiving voltage level for switching M8 is 0
(V) control signal S8, because switch M8 is conducting (ON), and the voltage level for switching the drain electrode end of M8 is VDD, therefore switchs M8
Source terminal (N6) be input voltage level VDD.At this time, switch the voltage level of each endpoint operation of M8 also 0~VDD it
Between, therefore the voltage difference between each endpoint of M8 is switched not less than VDD and without having the situation of overvoltage.Switch the gate terminal of M5
Receiving voltage level is the control signal S5 of 2VDD, and the voltage level for switching the source terminal of M5 is also 2VDD, and switchs M5's
The voltage level of drain electrode end is VDD because being coupled to input terminal Vin, therefore switchs M5 to be not turned on (OFF).At this time, M5 is switched
Each endpoint voltage level between VDD~2VDD, therefore switch M5 each endpoint between voltage difference not less than VDD without
There is the situation of overvoltage.The gate terminal receiving voltage level for switching M7 is the control signal S7 of 0 (V), and switchs the source terminal of M7
Voltage level also because be coupled to ground be 0 (V), the voltage level for switching the drain electrode end of M7 be VDD, thus switch M7 be do not lead
Logical (OFF).At this time, the voltage level of each endpoint of M7 is switched between 0~VDD, therefore switchs the voltage between each endpoint of M7
Difference is not less than situations of the VDD without having overvoltage.
As shown in the above, four of voltage generation circuit 500 switch M5~M8 are in the period 1 and second round
The voltage level of middle operation is all between 0~VDD, or between VDD~2VDD, therefore switch M5~M8 all can be will not mistake
(voltage difference is not less than VDD) is normally turned on closing and can be produced output voltage in the case of voltage.
Referring again to Fig. 6, in another embodiment, voltage generation circuit 500 can more include a buffer 510.Buffering
The input terminal of device 510 is couple to the first end N5 of capacitance C3, and produces control signal S6 with controlling switch M6.Buffer 510 is inclined
It is pressed on the output voltage level 2VDD of the input voltage level VDD and output end vo ut of input terminal Vin.For example, this buffer 510
Positive supply input terminal be biased in voltage level 2VDD, and this bias can be provided by the output end vo ut of voltage generation circuit 500
Level, and the negative supply input terminal of this buffer 510 is then biased in voltage level VDD, and can be by the defeated of voltage generation circuit 500
Enter to hold Vin to provide this bias level.This buffer 510 may be, for example, a phase inverter, to produce the first end N5's of capacitance C3
The inversion signal of signal.In this embodiment, in the period 1, the voltage level of the first end N5 of capacitance C3 is VDD (low levels
It is accurate), buffer 510 then accordingly produces the control signal S6 that voltage level is 2VDD (high levels).In the second cycle, capacitance C3
The voltage level of first end N5 be 2VDD (high levels), it is VDD's (low level) that buffer 510, which then accordingly produces voltage level,
Control signal S6.
According to above-described embodiment, there is provided two kinds of voltage generation circuits.One kind is negative voltage generator, includes input terminal
Vin, capacitance C1, capacitance C2, switch M1~M4 and output end vo ut.The first end N3 of capacitance C2 is couple to ground terminal GND,
And second end N4 is couple to output end vo ut.Switch M1 is coupled between input terminal Vin and the first end N1 of capacitance C1, and controlled
In control signal S1.Switch M2 is coupled between the first end N3 of first end N1 and capacitance C2 of capacitance C1, and is controlled by control
Signal S2.Switch M3 is coupled between ground terminal GND and the second end N2 of capacitance C1, and is controlled by control signal S3.Switch M4
It is coupled between the second end N4 of second end N2 and capacitance C2 of capacitance C1, and is controlled by control signal S4.When switch M1 is with opening
When closing M3 conductings, switch M2 is not turned on switch M4.When switching M1 and switch M3 is not turned on, switch M2 is turned on switch M4.
Control signal S4 has from output voltage level-VDD to the amplitude of oscillation of ground voltage level 0 (V).When control signal S4 is output electricity
When pressing level-VDD, switch M4 is not turned on, and when control signal S4 is ground voltage level 0 (V), switch M4 conductings.
Another kind is voltage multiplie, includes output terminal Vin, capacitance C3, switch M5~M8 and output end vo ut.Switch M5
It is coupled between input terminal Vin and the first end N5 of capacitance C3, and is controlled by control signal S5.Switch M6 is coupled to capacitance C3's
Between first end N5 and output end vo ut, and it is controlled by control signal S6.Switch M7 is coupled to the of ground terminal GND and capacitance C3
Between two end N6, and it is controlled by control signal S7.Switch M8 is coupled between the second end N6 input terminals Vin of capacitance C3, and by
Control in control signal S8.When switch M5 is turned on switch M7, switch M6 and switch M8 are not turned on.When switch M5 is with switching M7 not
During conducting, switch M6 is turned on switch M8.Control signal S6 has from input voltage level VDD to output voltage level 2VDD's
The amplitude of oscillation, when control signal S6 is output voltage level 2VDD, switch M6 is not turned on, and when control signal S6 is input voltage position
During quasi- VDD, switch M6 conductings.
Two kinds of voltage generation circuits of this exposure can all make element in the case where not having overvoltage, there is provided output electricity
Pressure, therefore element can be avoided because high voltage causes to damage.In addition, this exposure is compared to known circuit design, it may be unnecessary to
The cost of circuit can be further saved using high pressure resistant element.
In conclusion although this exposure is disclosed above with multiple embodiments, so it is not limited to this exposure.Originally take off
Reveal those of ordinary skill in the art, in the spirit and scope for not departing from this exposure, when various changes can be made
With retouching.Therefore, the protection domain of this exposure is when subject to appended claims institute defender.
Claims (12)
1. a kind of voltage generation circuit, it is characterised in that include：
One first capacitance, has a first end and a second end；
One second capacitance, has one the 3rd end and one the 4th end, and the 3rd end is couple to a ground terminal, and the 4th end is couple to one
Output terminal, the ground terminal have a ground voltage level, which has an output voltage level；
One first switch, is coupled between an input terminal and the first end of first capacitance, and is controlled by one first control letter
Number, which has an input voltage level；
One second switch, is coupled between the first end of first capacitance and the 3rd end of second capacitance, and is controlled by
One second control signal；
One the 3rd switch, is coupled between the ground terminal and the second end of first capacitance, and is controlled by one the 3rd control letter
Number；And
One the 4th switch, is coupled between the second end of first capacitance and the 4th end of second capacitance, and be controlled by
One the 4th control signal, wherein, the 4th switch is non-high pressure resistant element；
Wherein, when the first switch and during three switch conductions, which is not turned on the 4th switch, and work as this
When one switch is not turned on the 3rd switch, the second switch and the 4th switch conduction；
Wherein, the 4th control signal has from the output voltage level to the amplitude of oscillation of the ground voltage level, when the 4th control
When signal processed is the output voltage level, the 4th switch is not turned on, and when the 4th control signal is the ground voltage level
When, the 4th switch conduction.
2. voltage generation circuit as claimed in claim 1, it is characterised in that further include：
One buffer, an input terminal system of the buffer are couple to the second end of first capacitance, and produce the 4th control
Signal is switched with controlling the 4th.
3. voltage generation circuit as claimed in claim 2, it is characterised in that the buffer system is biased in the ground voltage level
With the output voltage level.
4. voltage generation circuit as claimed in claim 1, it is characterised in that first control signal and second control signal tool
Have an amplitude of oscillation from the ground voltage level to the input voltage level, the 3rd control signal have from the output voltage level and
The amplitude of oscillation of the input voltage level.
5. voltage generation circuit as claimed in claim 4, it is characterised in that in a period 1, the first control signal
And the second control signal is the ground voltage level, the 3rd signal is the input voltage level, the 4th control signal
For the output voltage level, and wherein, the first switch and the 3rd switch are conducting, and the second switch and the 4th switch are
It is not turned on.
6. voltage generation circuit as claimed in claim 4, it is characterised in that in a second round, the first control signal
And the second control signal is the input voltage level, the 3rd signal is the output voltage level, the 4th control signal
For the ground voltage level, and wherein, the first switch and the 3rd switch is are not turned on, the second switch and the 4th switch
For conducting.
7. a kind of voltage generation circuit, it is characterised in that include：
One first capacitance, has a first end and a second end；
One first switch, is coupled between an input terminal and the first end of first capacitance, and is controlled by one first control letter
Number, which has an input voltage level；
One second switch, is coupled between the first end of first capacitance and an output terminal, and is controlled by one second control letter
Number, which has an output voltage level, wherein, which is non-high pressure resistant element；
One the 3rd switch, is coupled between a ground terminal and the second end of first capacitance, and is controlled by one the 3rd control letter
Number, which has a ground voltage level；And
One the 4th switch, is coupled between the second end of first capacitance and the input terminal, and is controlled by one the 4th control letter
Number；
Wherein, when the first switch and during three switch conductions, which is not turned on the 4th switch, and work as this
When one switch is not turned on the 3rd switch, the second switch and the 4th switch conduction；
Wherein the second control signal is with the amplitude of oscillation from the input voltage level to the output voltage level, when second control
When signal processed is the output voltage level, which is not turned on, and when the second control signal is the input voltage level
When, second switch conducting.
8. voltage generation circuit as claimed in claim 7, it is characterised in that further include：
One buffer, an input terminal system of the buffer are couple to the first end of first capacitance, and produce second control
Signal is to control the second switch.
9. voltage generation circuit as claimed in claim 8, it is characterised in that the buffer system is biased in the input voltage level
With the output voltage level.
10. voltage generation circuit as claimed in claim 7, it is characterised in that first control signal is with electric from the ground connection
Level to the amplitude of oscillation of the output voltage level, the 3rd control signal and the 4th control signal is pressed to have from the ground voltage position
Accurate and the input voltage level the amplitude of oscillation.
11. voltage generation circuit as claimed in claim 10, it is characterised in that in a period 1, the first control letter
Number it is the ground voltage level, which is the output voltage level, the 3rd signal and the 4th control letter
Number it is the input voltage level, and wherein, the first switch and the 3rd switch are conducting, the second switch and the 4th switch
To be not turned on.
12. voltage generation circuit as claimed in claim 10, it is characterised in that in a second round, the first control letter
Number it is the output voltage level, which is the input voltage level, the 3rd signal and the 4th control letter
Number it is the ground voltage level, and wherein, the first switch and the 3rd switch the second switch and the 4th are opened to be not turned on
Close as conducting.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510485966.3A CN106444943B (en) | 2015-08-10 | 2015-08-10 | Voltage generation circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510485966.3A CN106444943B (en) | 2015-08-10 | 2015-08-10 | Voltage generation circuit |
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| CN106444943A CN106444943A (en) | 2017-02-22 |
| CN106444943B true CN106444943B (en) | 2018-05-08 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107479615B (en) * | 2017-08-28 | 2019-04-30 | 武汉铂芯半导体有限公司 | A method of accelerating stabilized power supply output voltage |
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| US7535281B2 (en) * | 2006-09-29 | 2009-05-19 | Micron Technology, Inc. | Reduced time constant charge pump and method for charging a capacitive load |
| CN101493715A (en) * | 2008-01-21 | 2009-07-29 | 联咏科技股份有限公司 | Charge pumping circuit |
| KR20110106686A (en) * | 2010-03-23 | 2011-09-29 | 삼성전자주식회사 | A charge pump, a method for controlling the same, and a display driving system comprising the charge pump |
| DE102010028149B4 (en) * | 2010-04-23 | 2015-02-19 | Puls Gmbh | Redundancy module with self-supply of the active Entkoppelbauelements of a widely variable and low input voltage |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI293828B (en) * | 2005-04-28 | 2008-02-21 | Novatek Microelectronics Corp | Charge pump |
| TWI349410B (en) * | 2008-01-08 | 2011-09-21 | Novatek Microelectronics Corp | Change pump circuit |
| US20110210712A1 (en) * | 2010-03-01 | 2011-09-01 | Tagare Madhavi V | AC or DC POWER SUPPLY EMPLOYING SAMPLING POWER CIRCUIT |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7535281B2 (en) * | 2006-09-29 | 2009-05-19 | Micron Technology, Inc. | Reduced time constant charge pump and method for charging a capacitive load |
| CN101493715A (en) * | 2008-01-21 | 2009-07-29 | 联咏科技股份有限公司 | Charge pumping circuit |
| KR20110106686A (en) * | 2010-03-23 | 2011-09-29 | 삼성전자주식회사 | A charge pump, a method for controlling the same, and a display driving system comprising the charge pump |
| DE102010028149B4 (en) * | 2010-04-23 | 2015-02-19 | Puls Gmbh | Redundancy module with self-supply of the active Entkoppelbauelements of a widely variable and low input voltage |
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| CN106444943A (en) | 2017-02-22 |
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