CN203396864U - Electrostatic discharge detection circuit and processing system - Google Patents
Electrostatic discharge detection circuit and processing system Download PDFInfo
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- CN203396864U CN203396864U CN201320465621.8U CN201320465621U CN203396864U CN 203396864 U CN203396864 U CN 203396864U CN 201320465621 U CN201320465621 U CN 201320465621U CN 203396864 U CN203396864 U CN 203396864U
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Abstract
The utility model provides an electrostatic discharge detection circuit and a processing system, which comprise a sampling unit, an amplifier unit, and a voltage adjustment unit. The sampling unit is connected with a first power line and a second power line, wherein the voltage of the second power line is smaller than the voltage of the first power line. The sampling unit is used for sampling the voltage of the first power line and the voltage of the second power line to output a control voltage. The amplifier unit connected with the sampling unit is used for outputting a first detection signal when the control voltage is larger than the threshold voltage of the amplifier unit and outputting a second detection signal when the control voltage is smaller than the threshold voltage of the amplifier unit. The voltage adjustment unit connected with the amplifier unit is used for adjusting the threshold voltage of the amplifier unit. According to the utility model, the detection range of the electrostatic discharge detection circuit is widened. In this way, the detection on the interior of a system-level chip of a smaller electrostatic voltage is enabled.
Description
Technical field
The utility model relates to static discharge technical field, particularly a kind of electrostatic discharge testing circuit and disposal system.
Background technology
Static discharge (ESD, Electro-Static Discharge) be to cause most of electronic packages or electronic system to be subject to the excessively electrically principal element of stress rupture, this destruction can cause the permanent damage of semiconductor devices, thereby causes the inefficacy of integrate circuit function.And for system level chip, the electrostatic potential being produced by static discharge on chip internal power lead is more much smaller than the electrostatic potential that static discharge position occurs, the chip failure that static discharge causes is that logical circuit running status is disorderly, rather than directly destroys internal components.Therefore, conventionally adopt electrostatic discharge testing circuit to carry out the static discharge of detection system level chip, and output detection signal, by electrostatic discharge treatment system, according to the detection signal of testing circuit output, electrostatic discharge event is processed.
Fig. 1 is the circuit diagram of existing a kind of electrostatic discharge testing circuit.With reference to figure 1, described electrostatic discharge testing circuit comprises diode group 11 and resistance R.Described diode group 11 comprises the diode of a plurality of series connection, and the negative electrode of first diode D1 is suitable for connecting the first power lead Vdd, the first end of resistance R described in the anodic bonding of last diode Dn; The second end of described resistance R is suitable for connecting second source line Vss, the voltage that the voltage that described second source line Vss provides provides lower than described the first power lead Vdd.The first end of described resistance R, as the output terminal of described electrostatic discharge testing circuit, is suitable for output detection signal V1.
When the upper generation of described the first power lead Vdd static discharge, all diodes in described diode group 11 are breakdown, have electric current through described resistance R, make described detection signal V1 switch to high level signal by low level signal.
Yet, only on described the first power lead Vdd, occur electrostatic potential that static discharge produces be greater than described diode group 11 in during the voltage breakdown sum of all diodes, could be by all diode breakdown in described diode group 11, the detection signal V1 of output high level.Therefore, described electrostatic discharge testing circuit can not detect less electrostatic potential, and sensing range is narrower.
More technical schemes that detect about static discharge can be the Chinese patent application file that CN101650394A, denomination of invention are " electrostatic discharge detection device " with reference to publication number.
Utility model content
What the utility model solved is the narrow problem of existing electrostatic discharge testing circuit sensing range.
For addressing the above problem, the utility model provides a kind of electrostatic discharge testing circuit, and described electrostatic discharge testing circuit comprises: the voltage that the second source line of the voltage providing lower than described the first power lead with the voltage providing with the first power lead is connected, is suitable for sampling on described the first power lead and second source line is controlled the sampling unit of voltage with output; Be connected, be suitable for when described control voltage is greater than the threshold voltage of amplifier unit output detection signal with described sampling unit and be the first detection signal and when described control voltage is less than the threshold voltage of amplifier unit output detection signal be the amplifier unit of the second detection signal; Be connected, be suitable for regulating the voltage-regulation unit of the threshold voltage of described amplifier unit with described amplifier unit.
Optionally, described amplifier unit comprises that a PMOS pipe and a NMOS that grid is connected manage; The grid of a described PMOS pipe is the input end that described amplifier unit receives described control voltage, and the drain electrode of a described PMOS pipe and the drain electrode of a described NMOS pipe are connected and export as described amplifier unit the output terminal of described detection signal.
Optionally, described voltage-regulation unit comprises the PMOS pipe group consisting of at least one PMOS pipe, PMOS pipe in described PMOS pipe group becomes cascaded structure, the grid of each PMOS pipe is connected with drain electrode separately, described PMOS Guan Zu one end is the first input end that the first supply voltage is inputted in described voltage-regulation unit, and the other end of described PMOS pipe group connects the source electrode of a described PMOS pipe.
Optionally, described voltage-regulation unit comprises the NMOS pipe group consisting of at least one NMOS pipe, NMOS pipe in described NMOS pipe group becomes cascaded structure, the grid of each NMOS pipe is connected with drain electrode separately, described NMOS Guan Zu one end is the second input end of described voltage-regulation unit input second source voltage, and the other end of described NMOS pipe group connects the source electrode of a described NMOS pipe.
Optionally, described voltage-regulation unit comprises the PMOS pipe group consisting of at least one PMOS pipe and the NMOS pipe group consisting of at least one NMOS pipe; PMOS pipe in described PMOS pipe group becomes cascaded structure, the grid of each PMOS pipe is connected with drain electrode separately, described PMOS Guan Zu one end is the first input end that the first supply voltage is inputted in described voltage-regulation unit, and the other end of described PMOS pipe group connects the source electrode of a described PMOS pipe; NMOS pipe in described NMOS pipe group becomes cascaded structure, the grid of each NMOS pipe is connected with drain electrode separately, described NMOS Guan Zu one end is that the second input end lower than the second source voltage of described the first supply voltage is inputted in described voltage-regulation unit, and the other end of described NMOS pipe group connects the source electrode of described NMOS pipe; .
Optionally, described sampling unit comprises and is connected in the first impedor and first capacitive reactive element of connecting between described the first power lead and described second source line, and the link of described the first impedor and described the first capacitive reactive element is exported the output terminal of described control voltage as described sampling unit.
Optionally, described the first impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance, and described the first capacitive reactive element is polycrystalline silicon-insulator-polycrystalline silicon capacitance, metal-insulator-polysilicon capacitance, metal-insulator-metal capacitor, metal-oxide-metal capacitor or mos capacitance.
Optionally, described sampling unit also comprises the second impedor, described the first capacitive reactive element is connected with described the first impedor by described the second impedor, and described the first impedor and described the second impedor link are exported the output terminal of described control voltage as described sampling unit.
Optionally, described sampling unit comprises and is connected between described the first power lead and described second source line the 3rd impedor, the 4th impedor of series connection and the transistor group consisting of at least one transistor successively; Transistor in described transistor group becomes cascaded structure, and each transistorized grid is connected with drain electrode separately; Described the 3rd impedor and described the 4th impedor link are exported the output terminal of described control voltage as described sampling unit.
Optionally, described the 3rd impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance, and described the 4th impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance.
Optionally, described electrostatic discharge testing circuit also comprises the latch unit that is connected with described amplifier unit and is suitable for described the first detection signal or the second detection signal to latch rear output.
Based on above-mentioned electrostatic discharge testing circuit, the utility model also provides a kind of electrostatic discharge treatment system, comprise processing unit, discharge cell and at least two above-mentioned electrostatic discharge testing circuits, described processing unit be connected with at least two electrostatic discharge testing circuits with described discharge cell and be suitable for receiving described in the detection signals of at least two electrostatic discharge testing circuit outputs, and when the first detection signal quantity receiving is more than or equal to the quantity of the second detection signal, trigger the electrostatic potential that described discharge cell is released on described the first power lead and second source line.
Optionally, described discharge cell comprises discharge transistor, the first end of described discharge transistor is suitable for connecting described processing unit, and the second end of described discharge transistor is suitable for connecting described the first power lead, and the 3rd end of described discharge transistor is suitable for connecting described second source line.
Optionally, described discharge transistor is metal-oxide-semiconductor or triode.
Compared with prior art, the technical solution of the utility model has the following advantages:
By sampling unit, the voltage on power lead is sampled, to produce control voltage.Amplifier unit is exported different detection signals according to the comparative result of the threshold voltage of described control voltage and described amplifier unit.Because electrostatic discharge testing circuit of the present utility model also comprises the voltage-regulation unit of the threshold voltage of adjustable described amplifier unit, by regulating the threshold voltage of described amplifier unit, the electrostatic potential that can detect can be set, therefore, the sensing range of electrostatic discharge testing circuit broadens.
Because described sampling unit is by forming the device of electrostatic discharge responsive, can catch electrostatic potential less on power lead, therefore, electrostatic discharge testing circuit of the present utility model can be used in the electrostatic detection of the system level chip inside that electrostatic potential is less.
In possibility, described sampling unit consists of resistance device and capacitor element, control capacittance device and resistance device can change the response time of electrostatic discharge testing circuit to electrostatic discharge event, therefore, and the detection sensitivity of adjustable described electrostatic discharge testing circuit.
Further, the electrostatic discharge treatment system that the utility model provides can comprehensively be analyzed according to the detection signal of a plurality of electrostatic discharge testing circuit outputs, after analysis, electrostatic discharge event is processed, and has improved the stability of chip system.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of existing a kind of electrostatic discharge testing circuit;
Fig. 2 is the electrical block diagram of the electrostatic discharge testing circuit of the utility model embodiment;
Fig. 3 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 1;
Fig. 4 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 2;
Fig. 5 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 3;
Fig. 6 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 4;
Fig. 7 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 5;
Fig. 8 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 6;
Fig. 9 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 7;
Figure 10 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 8;
Figure 11 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 9;
Figure 12 is the electrical block diagram of the electrostatic discharge treatment system of the utility model embodiment.
Embodiment
Just as described in the background art, the electrostatic potential that electrostatic discharge testing circuit shown in Fig. 1 produces by static discharge has all diode breakdown in diode group 11 detection signal of high level with generation, the electrostatic potential that therefore, can detect must be greater than the voltage breakdown sum of all diodes.
For example, described diode group 11 adopts the diode series connection that voltage breakdown is identical, the magnitude of voltage of the voltage breakdown of every diode is VBR, if the diode of series connection is one, the electrostatic potential that magnitude of voltage is greater than VBR can be detected, and the electrostatic potential that magnitude of voltage is less than or equal to VBR just can not be detected; If the diode of series connection is two, the electrostatic potential that magnitude of voltage is greater than 2VBR can be detected, and the electrostatic potential that magnitude of voltage is less than or equal to 2VBR just can not be detected.Therefore, existing electrostatic discharge testing circuit can not detect less electrostatic potential, and sensing range is narrower.
Technical solutions of the utility model provide a kind of sensing range wide testing circuit.
For above-mentioned purpose of the present utility model, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiment of the utility model is described in detail.
With reference to the electrical block diagram of the electrostatic discharge testing circuit of the technical solutions of the utility model shown in figure 2, described electrostatic discharge testing circuit comprises sampling unit 21, amplifier unit 22 and voltage-regulation unit 23.
Described sampling unit 21 is coupled between the first power lead Vdd and second source line Vss, and the voltage that is suitable for sampling on described the first power lead Vdd and second source line Vss is controlled voltage Vi with output.The voltage that the voltage that described the first power lead Vdd provides provides higher than described second source line Vss, conventionally, described the first power lead Vdd provides the supply voltage of high level, and described second source line Vss provides ground voltage.
Described amplifier unit 22 couples described sampling unit 21 and described voltage-regulation unit 23, be suitable for receiving described control voltage Vi, according to the threshold voltage output detection signal of described control voltage Vi and described amplifier unit 22, when described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, by output terminal out, export the first detection signal, when described control voltage Vi is less than the threshold voltage of described amplifier unit 22, by output terminal out, export the second detection signal.
Described voltage-regulation unit 23 is suitable for regulating the threshold voltage of described amplifier unit 22.
For understanding better structure and the principle of work of the electrostatic discharge testing circuit that the utility model provides, below in conjunction with accompanying drawing and specific embodiment, be described in detail.
Embodiment 1
Fig. 3 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 1.
With reference to figure 3, sampling unit 21a comprises the first impedor R1 and the first capacitive reactive element C1.Described first impedor R1 one end connects described the first power lead Vdd, and the other end of described the first impedor R1 connects described first capacitive reactive element C1 one end and as described sampling unit 21a, exports the output terminal of described control voltage Vi.The other end of described the first capacitive reactive element C1 connects described second source line Vss.
Described the first impedor R1 can consist of the various devices that contain resistance, comprises polysilicon resistance, active area resistance, trap resistance or MOS channel resistance etc.Described the first capacitive reactive element C1 can consist of capacitor element, comprises polycrystalline silicon-insulator-polycrystalline silicon capacitance, metal-insulator-polysilicon capacitance, metal-insulator-metal capacitor, metal-oxide-metal capacitor or mos capacitance etc.
Described amplifier unit 22 comprises a PMOS pipe P1 and the NMOS pipe N1 that grid is connected.The grid of a described PMOS pipe P1 is the input end that described amplifier unit 22 receives described control voltage Vi, and the drain electrode that the drain electrode of a described PMOS pipe P1 is managed N1 with a described NMOS is connected and as the output terminal out of described amplifier unit 22 output detection signals.
In the present embodiment, the CMOS phase inverter that described amplifier unit 22 is comprised of a PMOS pipe P1 and NMOS pipe N1.The high level signal corresponding digital signals " 1 " of described CMOS phase inverter output, the low level signal corresponding digital signals " 0 " of described CMOS phase inverter output.
When described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, a described PMOS pipe P1 cut-off, a described NMOS pipe N1 conducting, the first detection signal of output is low level signal; When described control voltage Vi is reduced to the threshold voltage that equals described amplifier unit 22, the signal of described CMOS phase inverter output is high level signal by low level signal saltus step; When described control voltage Vi is less than the threshold voltage of described amplifier unit 22, a described PMOS pipe P1 conducting, a described NMOS pipe N1 cut-off, the second detection signal of output is high level signal; When described control voltage Vi is increased to the threshold voltage that equals described amplifier unit 22, the signal of described CMOS phase inverter output is low level signal by high level signal saltus step.
The critical voltage of the threshold voltage of described amplifier unit 22 when controlling the detection signal saltus step of described amplifier unit 22 outputs.Described critical voltage is that device and the circuit structure included to amplifier unit 22 is relevant.In the present embodiment, size, the size of a described NMOS pipe N1 that the threshold voltage of described amplifier unit 22 is managed P1 to a described PMOS are, the source voltage of a described PMOS pipe P1 is relevant with the source voltage of a described NMOS pipe N1.
Described voltage-regulation unit is by regulating the source voltage of a described PMOS pipe P1 and/or the source voltage of a described NMOS pipe N1 to regulate the threshold voltage of described amplifier unit 22.In the present embodiment, described voltage-regulation unit comprises the PMOS pipe group 23a consisting of at least one PMOS pipe.First PMOS pipe P31 in described PMOS pipe group 23a,, a n PMOS pipe P3n becomes cascaded structure, n is the quantity of the PMOS pipe of connecting.
The drain electrode of each PMOS pipe is connected with the source electrode of another PMOS pipe of series connection, and the grid of each PMOS pipe is connected with drain electrode separately.The source electrode of described first PMOS pipe P31 is as the first end of described PMOS pipe group 23a, and the drain electrode of described n PMOS pipe P3n is as the second end of described PMOS pipe group 23a.
The first end of described PMOS pipe group 23a is connected with described the first power lead Vdd, and the second end of described PMOS pipe group 23a connects the source electrode of a described PMOS pipe P1.In the present embodiment, the first end of described PMOS pipe group 23a is suitable for inputting the first supply voltage, and described the first supply voltage is the voltage that described the first power lead Vdd provides.In other embodiments, the first end of described PMOS pipe group 23a also can connect other power supplies, and the utility model is not construed as limiting this.
Because described amplifier unit 22 is inputted described the first supply voltage by described voltage-regulation unit, described voltage-regulation unit carries out dividing potential drop, therefore, the source voltage of a PMOS pipe P1 in described amplifier unit 22 reduces, the ducting capacity of a described PMOS pipe P1 weakens, thereby the threshold voltage of described amplifier unit 22 is reduced.
Pressure drop on described PMOS pipe group 23a is n * Vthp, and Vthp is the threshold voltage of each series connection PMOS pipe.The quantity of PMOS pipe of connecting in described PMOS pipe group 23a is more, the dividing potential drop effect of described PMOS pipe group 23a is stronger, the source voltage of a PMOS pipe P1 in described amplifier unit 22 is lower, therefore, the ducting capacity of a described PMOS pipe P1 is more weak, thereby makes the threshold voltage of described amplifier unit 22 lower.
Below in conjunction with circuit shown in Fig. 3 and the concrete course of work thereof, the utility model advantage is described further.
While there is not the electrostatic potential of static discharge generation on described the first power lead Vdd, described control voltage Vi is pulled to noble potential by described the first impedor R1, therefore, described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, a described NMOS pipe N1 conducting, a described PMOS pipe P1 cut-off, the first detection signal of described amplifier unit 22 output low levels.
While there is the electrostatic potential of static discharge generation on described the first power lead Vdd, described electrostatic potential is pulse voltage, give described the first capacitive reactive element C1 charging, described control voltage Vi is pulled to electronegative potential by described the first capacitive reactive element C1, therefore, described control voltage Vi is less than the threshold voltage of described amplifier unit 22, a described NMOS pipe N1 cut-off, a described PMOS pipe P1 conducting, the second detection signal of described amplifier unit 22 output high level.
Because described PMOS pipe group 23a makes the threshold voltage of described amplifier unit 22, reduce, therefore, while there is the less electrostatic potential of static discharge generation on described the first power lead Vdd, described electrostatic potential also can be detected.
It should be noted that, in the present embodiment, can also regulate the detection sensitivity of described electrostatic discharge testing circuit, the detection sensitivity of electrostatic discharge testing circuit refers to from producing electrostatic potential to the time of the detection signal of the corresponding described electrostatic potential of described electrostatic discharge testing circuit output.Described sampling unit 21a is comprised of described the first impedor R1 and described the first capacitive reactive element C1, due to capacitive reactive element is discharged and recharged and needs the time, therefore, regulate the size of described the first impedor R1 and described the first capacitive reactive element C1, can regulate the response time of described electrostatic discharge testing circuit to electrostatic potential, can regulate the detection sensitivity of described electrostatic discharge testing circuit.
Embodiment 2
Fig. 4 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 2.With reference to figure 4, embodiment 2 is with the difference of embodiment 1: sampling unit 21b comprises described the first impedor R1 and described the first capacitive reactive element C1, also comprise the second impedor R2, described the first capacitive reactive element C1 is connected with described the first impedor R1 by described the second impedor R2, and the link of described the first impedor R1 and described the second impedor R2 is exported the output terminal of described control voltage Vi as described sampling unit 21b.
Described the second impedor R2 can consist of the various devices that contain resistance, comprises polysilicon resistance, active area resistance, trap resistance or MOS channel resistance etc.
In the present embodiment, described sampling unit 21b comprises described the second impedor R2, described the second impedor R2 can change the charging current to described the first capacitive reactive element C1, further regulates the sensitivity of described electrostatic discharge testing circuit, makes adjustment of sensitivity scope wider.
Embodiment 3
Fig. 5 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 3.With reference to figure 5, embodiment 3 is with the difference of embodiment 1: described the first impedor R1 and described the first capacitive reactive element C1 transposition, be that described first impedor R1 one end connects described second source line Vss, the other end of described the first impedor R1 connects described first capacitive reactive element C1 one end and as sampling unit 21c, exports the output terminal of described control voltage Vi, and the other end of described the first capacitive reactive element C1 connects described the first power lead Vdd.
In the present embodiment, while there is not the electrostatic potential of static discharge generation on described the first power lead Vdd, described control voltage Vi is pulled to electronegative potential by described the first impedor R1, therefore, described control voltage Vi is less than the threshold voltage of described amplifier unit 22, a described PMOS pipe P1 conducting, a described NMOS pipe N1 cut-off, the second detection signal of the high level of described amplifier unit 22 outputs.
While there is the electrostatic potential of static discharge generation on described the first power lead Vdd, described electrostatic potential is pulse voltage, give described the first capacitive reactive element C1 charging, described control voltage Vi is pulled to noble potential by described the first capacitive reactive element C1, therefore, described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, a described NMOS pipe N1 conducting, a described PMOS pipe P1 cut-off, low level first detection signal of described amplifier unit 22 outputs.
Because described PMOS pipe group 23a makes the threshold voltage of described amplifier unit 22, reduce, therefore, while there is the less electrostatic potential of static discharge generation on described the first power lead Vdd, described electrostatic potential also can be detected.
Embodiment 4
Fig. 6 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 4.With reference to figure 6, embodiment 4 is with the difference of embodiment 3: sampling unit 21d comprises described the first impedor R1 and described the second capacitive reactive element C1, also comprise the second impedor R2, described the first capacitive reactive element C1 is connected with described the first impedor R1 by described the second impedor R2, and the link of described the first impedor R1 and described the second impedor R2 is exported the output terminal of described control voltage Vi as described sampling unit 21d.
Described the second impedor R2 can consist of the various devices that contain resistance, comprises polysilicon resistance, active area resistance, trap resistance or MOS channel resistance etc.
Described sampling unit 21d comprises described the second impedor R2, and described the second impedor R2 can change the charging current to described the first capacitive reactive element C1, further regulates the sensitivity of described electrostatic discharge testing circuit, makes adjustment of sensitivity scope wider.
Embodiment 5
Fig. 7 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 5.With reference to figure 7, embodiment 5 is with the difference of embodiment 1: sampling unit 21e comprises the 3rd impedor R3, the 4th impedor R4 and the transistor group 24a being formed by least one transistor, described the 3rd impedor R3 one end is suitable for connecting described the first power lead Vdd, the other end of described the 3rd impedor R3 connects described the 4th impedor R4 one end and as described sampling unit 21e, exports the output terminal of described control voltage Vi, the other end of described the 4th impedor R4 connects the first end of described transistor group 24a, the second end of described transistor group 24a is suitable for connecting described second source line Vss.
In the present embodiment, the transistor in described transistor group 24a is NMOS pipe.First NMOS pipe N41 in described transistor group 24a,, a m NMOS pipe N4m becomes cascaded structure, m is the quantity of the NMOS pipe of connecting.The drain electrode of each NMOS pipe is connected with the source electrode of another NMOS pipe of series connection, and the grid of each NMOS pipe is connected with drain electrode separately.The drain electrode of described first NMOS pipe N41 is as the first end of described transistor group 24a, and the source electrode of described m NMOS pipe N4m is as the second end of described transistor group 24a.
In the present embodiment, NMOS pipe in described transistor group 24a becomes diode to connect, and the voltage on described the first power lead Vdd is during lower than m * Vthn, the NMOS pipe cut-off in described transistor group 24a, wherein, Vthn is the threshold voltage of each NMOS pipe in described transistor group 24a.
While there is not the electrostatic potential of static discharge generation on described the first power lead Vdd, NMOS pipe cut-off in described transistor group 24a, described control voltage Vi is pulled to noble potential by described the 3rd impedor R3, therefore, described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, a described PMOS pipe P1 cut-off, a described NMOS pipe N1 conducting, the first detection signal of described amplifier unit 22 output low levels.
While there is the electrostatic potential of static discharge generation on described the first power lead Vdd, voltage on described the first power lead Vdd raises, make the NMOS pipe conducting in described transistor group 24a, described control voltage Vi is pulled to electronegative potential by described the 4th impedor R4 and described transistor group 24a, therefore, described control voltage Vi is less than the threshold voltage of described amplifier unit 22, a described NMOS pipe N1 cut-off, a described PMOS pipe P1 conducting, the second detection signal of described amplifier unit 22 output high level.
Embodiment 6
Fig. 8 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 6.With reference to figure 8, embodiment 6 is with the difference of embodiment 5: the transistor in the transistor group 24b in sampling unit 21f is PMOS pipe, the first end of described transistor group 24b is suitable for connecting described the first power lead Vdd, the second end of described transistor group 24b connects described the 4th impedor R4 one end, the other end of described the 4th impedor R4 and described the 3rd impedor R3 one end are connected and export as described sampling unit 21f the output terminal of described control voltage Vi, and the other end of described the 3rd impedor R3 is suitable for connecting described second source line Vss.
First PMOS pipe N41 in described transistor group 24b,, a m PMOS pipe P4m becomes cascaded structure, m is the quantity of the PMOS pipe of connecting.The drain electrode of each PMOS pipe is connected with the source electrode of another PMOS pipe of series connection, and the grid of each PMOS pipe is connected with drain electrode separately.The source electrode of described first PMOS pipe P41 is as the first end of described transistor group 24b, and the drain electrode of described m PMOS pipe P4m is as the second end of described transistor group 24b.
In the present embodiment, PMOS pipe in described transistor group 24b becomes diode to connect, and the voltage on described the first power lead Vdd is during lower than m * Vthp, the PMOS pipe cut-off in described transistor group 24b, wherein, Vthp is the threshold voltage of each PMOS pipe in described transistor group 24b.
While there is not the electrostatic potential of static discharge generation on described the first power lead Vdd, PMOS pipe cut-off in described transistor group 24b, described control voltage Vi is pulled to electronegative potential by described the 3rd impedor R3, therefore, described control voltage Vi is less than the threshold voltage of described amplifier unit 22, a described PMOS pipe P1 conducting, a described NMOS pipe N1 cut-off, the second detection signal of described amplifier unit 22 output high level.
While there is the electrostatic potential of static discharge generation on described the first power lead Vdd, voltage on described the first power lead Vdd raises, make the PMOS pipe conducting in described transistor group 24b, described control voltage Vi is pulled to noble potential by described the 4th impedor R4 and described transistor group 24b, therefore, described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, a described NMOS pipe N1 conducting, a described PMOS pipe P1 cut-off, the first detection signal of described amplifier unit 22 output low levels.
Embodiment 7
Fig. 9 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 7.With reference to figure 9, embodiment 7 is with the difference of embodiment 1: described voltage-regulation unit comprises the NMOS pipe group 23b consisting of at least one NMOS pipe, the first end of described NMOS pipe group 23b connects the source electrode of a described NMOS pipe N1, and the second end of described NMOS pipe group 23b is suitable for inputting second source voltage.
First NMOS pipe N31 in described NMOS pipe group 23b,, a n NMOS pipe N3n becomes cascaded structure, n is the quantity of the NMOS pipe of connecting.The drain electrode of each NMOS pipe is connected with the source electrode of another NMOS pipe of series connection, and the grid of each NMOS pipe is connected with drain electrode separately.The drain electrode of described first NMOS pipe N31 is as the first end of described NMOS pipe group 23b, and the source electrode of described n NMOS pipe N3n is as the second end of described NMOS pipe group 23b.
In the present embodiment, the second end of described NMOS pipe group 23b is connected with described second source line Vss, and described second source voltage is the voltage that described second source line Vss provides.In other embodiments, the second end of described NMOS pipe group 23b also can connect other power supplies, and the utility model is not construed as limiting this.
Because described amplifier unit 22 is inputted described second source voltage by described voltage-regulation unit, described voltage-regulation unit carries out dividing potential drop, therefore, the source voltage of a NMOS pipe N1 in described amplifier unit 22 raises, the ducting capacity of a described NMOS pipe N1 weakens, thereby the threshold voltage of described amplifier unit 22 is raise.
Pressure drop on described NMOS pipe group 23b is n * Vthn, and Vthn is the threshold voltage of each series connection NMOS pipe.The quantity of NMOS pipe of connecting in described NMOS pipe group 23b is more, the dividing potential drop effect of described NMOS pipe group 23b is stronger, the source voltage of a NMOS pipe N1 in described amplifier unit 22 is higher, therefore, the ducting capacity of a described NMOS pipe N1 is more weak, thereby makes the threshold voltage of described amplifier unit 22 higher.
Due to the threshold voltage rising of described amplifier unit 22, the electrostatic potential that can detect raises, and can prevent the error detection causing due to noise.
Embodiment 8
Figure 10 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 8.With reference to Figure 10, embodiment 8 is with the difference of embodiment 1: the NMOS pipe group 23b that described voltage-regulation unit comprises the PMOS pipe group 23a consisting of at least one PMOS pipe and consists of at least one NMOS pipe, described PMOS Guan Zu23a one end is suitable for inputting the first supply voltage, and the other end of described PMOS pipe group 23a connects the source electrode of a described PMOS pipe P1; Described NMOS Guan Zu23b one end is suitable for receiving second source voltage, and the other end of described NMOS pipe group 23b connects the source electrode of described NMOS pipe N1; Described the first supply voltage is higher than described second source voltage.
In the present embodiment, the described PMOS pipe group of the particular circuit configurations of described PMOS pipe group 23a in can reference example 1, the described NMOS pipe group of the concrete structure of described NMOS pipe group 23b in can reference example 7, described sampling unit 21 can, with reference to previous embodiment, not repeat them here.
Described PMOS pipe group 23a can reduce the source voltage of a described PMOS pipe P1, can the raise source voltage of a described NMOS pipe N1 of described NMOS pipe group 23b, by described PMOS pipe group 23a and described NMOS pipe group 23b, regulate the threshold voltage of described amplifier unit 22, can regulate the sensing range of described electrostatic discharge testing circuit.
Embodiment 9
Figure 11 is the circuit diagram of the electrostatic discharge testing circuit of the utility model embodiment 9.With reference to Figure 11, described electrostatic discharge testing circuit comprises sampling unit 21, amplifier unit 22, voltage-regulation unit 23, also comprises latch unit 25, and described latch unit 25 is suitable for described the first detection signal or the second detection signal to latch rear output.The concrete structure of described sampling unit 21, amplifier unit 22 and voltage-regulation unit 23 can, with reference to previous embodiment, not repeat them here.
Described latch unit 25 can be RS latch, described RS latch can carry out shaping to described the first detection signal and described the second detection signal, described the first detection signal is converted to digital signal " 0 ", described the second detection signal is converted to digital signal " 1 ".
With reference to Figure 12, technical solutions of the utility model also provide a kind of electrostatic discharge treatment system.Described electrostatic discharge treatment system comprises processing unit 122, discharge cell 123 and at least two electrostatic discharge testing circuits: electrostatic discharge testing circuit 1211 ..., electrostatic discharge testing circuit 121N, the quantity that N is described electrostatic discharge circuit.The structure of described electrostatic discharge testing circuit can be any one circuit structure shown in Fig. 3～Figure 11.
The electrostatic potential being produced by static discharge on system level chip internal power cord is more much smaller than the electrostatic potential that static discharge position occurs.For the strong circuit of antistatic interference performance, the electrostatic potential on power lead can not exert an influence to its work, does not need electrostatic potential to process.And for the circuit to electrostatic interference sensitivity, less electrostatic potential also can cause it to work, need to process electrostatic potential.Therefore, a plurality of electrostatic discharge testing circuits can be set in chip, the detection signal by judging different electrostatic discharge testing circuits need to be processed electrostatic potential determining whether.
It should be noted that, the sensing range of a plurality of electrostatic discharge testing circuits and detection sensitivity can be identical, are arranged on the diverse location in chip; The sensing range of a plurality of electrostatic discharge testing circuits and detection sensitivity also can be different, are arranged on the same position in chip; The sensing range of a plurality of electrostatic discharge testing circuits and detection sensitivity can also be different, are arranged on the diverse location in chip.
Due to a detection signal of each electrostatic discharge testing circuit output, therefore, at least two detection signals of the corresponding output of described at least two electrostatic discharge testing circuits.At least two detection signals described in described processing unit 122 is suitable for receiving, and the quantity of the first detection signal in receive at least two detection signals and the quantity of the second detection signal are compared, when the first detection signal quantity receiving is more than or equal to the quantity of the second detection signal, trigger the electrostatic potential that described discharge cell 123 is released on described the first power lead Vdd and described second source line Vss.That is to say, the quantity by the first detection signal and the second detection signal at least two detection signals of at least two electrostatic discharge testing circuit outputs described in analyzing, can determine whether to process electrostatic potential.
Described discharge cell 123 comprises discharge transistor, the first end of described discharge transistor is suitable for connecting described processing unit 122, the second end of described discharge transistor is suitable for connecting described the first power lead Vdd, and the 3rd end of described discharge transistor is suitable for connecting described second source line Vss.Described discharge transistor can be metal-oxide-semiconductor or triode.
The electrostatic discharge treatment system that the utility model provides can be analyzed according to the detection signal of a plurality of electrostatic discharge testing circuits output, after analysis, electrostatic discharge event is processed, and prevents the error detection brought by noise, has improved the stability of chip system.
In sum, the electrostatic discharge testing circuit that the utility model provides, by the threshold voltage of resonance-amplifier unit, voltage-regulation unit, the sensing range of electrostatic discharge testing circuit broadens, and, can catch change in voltage less on power lead, electrostatic discharge testing circuit of the present utility model can be used in the detection of the system level chip inside that electrostatic potential is less.
Although the utility model discloses as above, the utility model is not defined in this.Any those skilled in the art, within not departing from spirit and scope of the present utility model, all can make various changes or modifications, and therefore protection domain of the present utility model should be as the criterion with claim limited range.
Claims (14)
1. an electrostatic discharge testing circuit, is characterized in that, comprising:
The voltage that the second source line of the voltage providing lower than described the first power lead with the voltage providing with the first power lead is connected, is suitable for sampling on described the first power lead and second source line is controlled the sampling unit of voltage with output;
Be connected, be suitable for when described control voltage is greater than the threshold voltage of amplifier unit output detection signal with described sampling unit and be the first detection signal and when described control voltage is less than the threshold voltage of amplifier unit output detection signal be the amplifier unit of the second detection signal;
Be connected, be suitable for regulating the voltage-regulation unit of the threshold voltage of described amplifier unit with described amplifier unit.
2. electrostatic discharge testing circuit according to claim 1, is characterized in that, described amplifier unit comprises a PMOS pipe and the NMOS pipe that grid is connected; The grid of a described PMOS pipe is the input end that described amplifier unit receives described control voltage, and the drain electrode of a described PMOS pipe and the drain electrode of a described NMOS pipe are connected and export as described amplifier unit the output terminal of described detection signal.
3. electrostatic discharge testing circuit according to claim 2, it is characterized in that, described voltage-regulation unit comprises the PMOS pipe group consisting of at least one PMOS pipe, PMOS pipe in described PMOS pipe group becomes cascaded structure, the grid of each PMOS pipe is connected with drain electrode separately, described PMOS Guan Zu one end is the first input end that the first supply voltage is inputted in described voltage-regulation unit, and the other end of described PMOS pipe group connects the source electrode of a described PMOS pipe.
4. electrostatic discharge testing circuit according to claim 2, it is characterized in that, described voltage-regulation unit comprises the NMOS pipe group consisting of at least one NMOS pipe, NMOS pipe in described NMOS pipe group becomes cascaded structure, the grid of each NMOS pipe is connected with drain electrode separately, described NMOS Guan Zu one end is the second input end of described voltage-regulation unit input second source voltage, and the other end of described NMOS pipe group connects the source electrode of a described NMOS pipe.
5. electrostatic discharge testing circuit according to claim 2, is characterized in that, described voltage-regulation unit comprises the PMOS pipe group consisting of at least one PMOS pipe and the NMOS pipe group consisting of at least one NMOS pipe; PMOS pipe in described PMOS pipe group becomes cascaded structure, the grid of each PMOS pipe is connected with drain electrode separately, described PMOS Guan Zu one end is the first input end that the first supply voltage is inputted in described voltage-regulation unit, and the other end of described PMOS pipe group connects the source electrode of a described PMOS pipe; NMOS pipe in described NMOS pipe group becomes cascaded structure, the grid of each NMOS pipe is connected with drain electrode separately, described NMOS Guan Zu one end is that the second input end lower than the second source voltage of described the first supply voltage is inputted in described voltage-regulation unit, and the other end of described NMOS pipe group connects the source electrode of described NMOS pipe.
6. electrostatic discharge testing circuit according to claim 1, it is characterized in that, described sampling unit comprises and is connected in the first impedor and first capacitive reactive element of connecting between described the first power lead and described second source line, and the link of described the first impedor and described the first capacitive reactive element is exported the output terminal of described control voltage as described sampling unit.
7. electrostatic discharge testing circuit according to claim 6, it is characterized in that, described the first impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance, and described the first capacitive reactive element is polycrystalline silicon-insulator-polycrystalline silicon capacitance, metal-insulator-polysilicon capacitance, metal-insulator-metal capacitor, metal-oxide-metal capacitor or mos capacitance.
8. according to the electrostatic discharge testing circuit described in claim 6 or 7 any one, it is characterized in that, described sampling unit also comprises the second impedor, described the first capacitive reactive element is connected with described the first impedor by described the second impedor, and described the first impedor and described the second impedor link are exported the output terminal of described control voltage as described sampling unit.
9. electrostatic discharge testing circuit according to claim 1, it is characterized in that, described sampling unit comprises and is connected between described the first power lead and described second source line the 3rd impedor, the 4th impedor of series connection successively and the transistor group consisting of at least one transistor; Transistor in described transistor group becomes cascaded structure, and each transistorized grid is connected with drain electrode separately; Described the 3rd impedor and described the 4th impedor link are exported the output terminal of described control voltage as described sampling unit.
10. electrostatic discharge testing circuit according to claim 9, it is characterized in that, described the 3rd impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance, and described the 4th impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance.
11. electrostatic discharge testing circuits according to claim 1, is characterized in that, also comprise the latch unit that is connected with described amplifier unit and is suitable for described the first detection signal or the second detection signal to latch rear output.
12. 1 kinds of electrostatic discharge treatment systems, it is characterized in that, comprise the electrostatic discharge testing circuit described in processing unit, discharge cell and at least two claim 1 to 11 any one, described processing unit be connected with at least two electrostatic discharge testing circuits with described discharge cell and be suitable for receiving described in the detection signals of at least two electrostatic discharge testing circuit outputs, and when the first detection signal quantity receiving is more than or equal to the quantity of the second detection signal, trigger the electrostatic potential that described discharge cell is released on described the first power lead and second source line.
13. electrostatic discharge treatment systems according to claim 12, it is characterized in that, described discharge cell comprises discharge transistor, the first end of described discharge transistor is suitable for connecting described processing unit, the second end of described discharge transistor is suitable for connecting described the first power lead, and the 3rd end of described discharge transistor is suitable for connecting described second source line.
14. electrostatic discharge treatment systems according to claim 13, is characterized in that, described discharge transistor is metal-oxide-semiconductor or triode.
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| CN201320465621.8U CN203396864U (en) | 2013-07-31 | 2013-07-31 | Electrostatic discharge detection circuit and processing system |
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| CN201320465621.8U CN203396864U (en) | 2013-07-31 | 2013-07-31 | Electrostatic discharge detection circuit and processing system |
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| CN203396864U true CN203396864U (en) | 2014-01-15 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103412216A (en) * | 2013-07-31 | 2013-11-27 | 格科微电子（上海）有限公司 | Electrostatic discharge detection circuit and processing system |
| CN105990330A (en) * | 2015-01-28 | 2016-10-05 | 旺宏电子股份有限公司 | Electrostatic discharge protection device |
| CN106291187A (en) * | 2016-08-11 | 2017-01-04 | 京东方科技集团股份有限公司 | The electrostatic discharge detection device of a kind of display device and detection method |
| CN107238769A (en) * | 2017-05-31 | 2017-10-10 | 晶晨半导体(上海)股份有限公司 | A kind of method of the Electro-static Driven Comb ability of analysis chip cabling |
| CN109188976A (en) * | 2018-09-14 | 2019-01-11 | 珠海格力电器股份有限公司 | Control chip |
| CN110391650A (en) * | 2018-04-18 | 2019-10-29 | 力旺电子股份有限公司 | Electrostatic discharge circuit |
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2013
- 2013-07-31 CN CN201320465621.8U patent/CN203396864U/en not_active Withdrawn - After Issue
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103412216A (en) * | 2013-07-31 | 2013-11-27 | 格科微电子（上海）有限公司 | Electrostatic discharge detection circuit and processing system |
| CN103412216B (en) * | 2013-07-31 | 2016-03-16 | 格科微电子（上海）有限公司 | Electrostatic discharge testing circuit and disposal system |
| CN105990330A (en) * | 2015-01-28 | 2016-10-05 | 旺宏电子股份有限公司 | Electrostatic discharge protection device |
| CN106291187A (en) * | 2016-08-11 | 2017-01-04 | 京东方科技集团股份有限公司 | The electrostatic discharge detection device of a kind of display device and detection method |
| CN107238769A (en) * | 2017-05-31 | 2017-10-10 | 晶晨半导体(上海)股份有限公司 | A kind of method of the Electro-static Driven Comb ability of analysis chip cabling |
| CN110391650A (en) * | 2018-04-18 | 2019-10-29 | 力旺电子股份有限公司 | Electrostatic discharge circuit |
| US10944258B2 (en) | 2018-04-18 | 2021-03-09 | Ememory Technology Inc. | RC circuit triggered electrostatic discharge circuit |
| CN110391650B (en) * | 2018-04-18 | 2021-11-23 | 力旺电子股份有限公司 | Electrostatic discharge circuit |
| CN109188976A (en) * | 2018-09-14 | 2019-01-11 | 珠海格力电器股份有限公司 | Control chip |
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