CN103412216A - Electrostatic discharge detection circuit and processing system - Google Patents
Electrostatic discharge detection circuit and processing system Download PDFInfo
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- CN103412216A CN103412216A CN2013103304540A CN201310330454A CN103412216A CN 103412216 A CN103412216 A CN 103412216A CN 2013103304540 A CN2013103304540 A CN 2013103304540A CN 201310330454 A CN201310330454 A CN 201310330454A CN 103412216 A CN103412216 A CN 103412216A
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Abstract
An electrostatic discharge detection circuit and a processing system comprise a sampling unit, an amplifier unit and a voltage adjusting unit, wherein the sampling unit is used for sampling the voltage of a first power wire and the voltage of a second power wire so as to output control voltage, the voltage provided by the first power wire is higher than the voltage provided by the second power wire, the amplifier unit is used for outputting first detection signals when the control voltage is larger than the threshold value voltage of the amplifier unit, and outputting second detection signals when the control voltage is less than the threshold value voltage of the amplifier unit, and the voltage adjusting unit is used for adjusting the threshold value voltage of the amplifier unit. The electrostatic discharge detection circuit can be widened in detection range, and can be used for detection of the inside of a system-level chip with little electrostatic voltage.
Description
Technical field
The present invention relates to the static discharge technical field, particularly a kind of electrostatic discharge testing circuit and disposal system.
Background technology
Static discharge (ESD, Electro-Static Discharge) be to cause most of electronic packages or electronic system to be subject to the excessively electrically principal element of stress rupture, this destruction can cause the permanent damage of semiconductor devices, thereby causes the inefficacy of integrate circuit function.And for system level chip, the electrostatic potential produced by static discharge on the chip internal power lead is more much smaller than the electrostatic potential that the static discharge position occurs, the chip failure that static discharge causes is the disorder of logical circuit running status, rather than directly destroys internal components.Therefore, usually adopt electrostatic discharge testing circuit to carry out the static discharge of detection system level chip, and output detection signal, by the electrostatic discharge treatment system, according to the detection signal of testing circuit output, electrostatic discharge event is processed.
Fig. 1 is the circuit diagram of existing a kind of electrostatic discharge testing circuit.With reference to figure 1, described electrostatic discharge testing circuit comprises diode group 11 and resistance R.Described diode group 11 comprises the diode of a plurality of series connection, and the negative electrode of first diode D1 is suitable for connecting the first power lead Vdd, the first end of the described resistance R of anodic bonding of last diode Dn; The second end of described resistance R is suitable for connecting second source line Vss, the voltage that the voltage that described second source line Vss provides provides lower than described the first power lead Vdd.The first end of described resistance R, as the output terminal of described electrostatic discharge testing circuit, is suitable for output detection signal V1.
When the upper generation of described the first power lead Vdd static discharge, all diodes in described diode group 11 are breakdown, electric current arranged through described resistance R, make described detection signal V1 switch to high level signal by low level signal.
Yet, only on described the first power lead Vdd, occur electrostatic potential that static discharge produces be greater than described diode group 11 in during the voltage breakdown sum of all diodes, could be by all diode breakdown in described diode group 11, the detection signal V1 of output high level.Therefore, described electrostatic discharge testing circuit can not detect less electrostatic potential, and sensing range is narrower.
More technical schemes that detect about static discharge can be that CN101650394A, denomination of invention are the Chinese patent application file of " electrostatic discharge detection device " with reference to publication number.
Summary of the invention
What the present invention solved is the narrow problem of existing electrostatic discharge testing circuit sensing range.
For addressing the above problem, the invention provides a kind of electrostatic discharge testing circuit, comprise sampling unit, amplifier unit and voltage-regulation unit, wherein, the voltage that described sampling unit is suitable for sampling on the first power lead and second source line is controlled voltage, the voltage that the voltage that described the first power lead provides provides higher than described second source line with output; The detection signal that described amplifier unit is suitable for exporting when described control voltage is greater than the threshold voltage of described amplifier unit is the first detection signal, and the detection signal of exporting when described control voltage is less than the threshold voltage of described amplifier unit is the second detection signal; Described voltage-regulation unit is suitable for regulating the threshold voltage of described amplifier unit.
Optionally, described amplifier unit comprises that a PMOS pipe and a NMOS that grid is connected manage; The grid of a described PMOS pipe is suitable for receiving described control voltage, and the drain electrode of a described PMOS pipe is connected and exports as described amplifier unit the output terminal of described detection signal with the drain electrode of a described NMOS pipe.
Optionally, described voltage-regulation unit comprises the PMOS pipe group consisted of at least one PMOS pipe, PMOS pipe in described PMOS pipe group becomes cascaded structure, the grid of each PMOS pipe is connected with drain electrode separately, one end of described PMOS pipe group is suitable for inputting the first supply voltage, and the other end of described PMOS pipe group connects the source electrode of a described PMOS pipe.
Optionally, described voltage-regulation unit comprises the NMOS pipe group consisted of at least one NMOS pipe, NMOS pipe in described NMOS pipe group becomes cascaded structure, the grid of each NMOS pipe is connected with drain electrode separately, one end of described NMOS pipe group is suitable for inputting second source voltage, and the other end of described NMOS pipe group connects the source electrode of a described NMOS pipe.
Optionally, described voltage-regulation unit comprises the PMOS pipe group consisted of at least one PMOS pipe and the NMOS pipe group consisted of at least one NMOS pipe; PMOS pipe in described PMOS pipe group becomes cascaded structure, and the grid of each PMOS pipe is connected with drain electrode separately, and an end of described PMOS pipe group is suitable for inputting the first supply voltage, and the other end of described PMOS pipe group connects the source electrode of a described PMOS pipe; NMOS pipe in described NMOS pipe group becomes cascaded structure, and the grid of each NMOS pipe is connected with drain electrode separately, and an end of described NMOS pipe group is suitable for receiving second source voltage, and the other end of described NMOS pipe group connects the source electrode of described NMOS pipe; Described the first supply voltage is higher than described second source voltage.
Optionally, described sampling unit comprises and is connected in the first impedor and first capacitive reactive element of connecting between described the first power lead and described second source line, and the link of described the first impedor and described the first capacitive reactive element is as the output terminal of the described control voltage of described sampling unit output.
Optionally, described the first impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance, and described the first capacitive reactive element is polycrystalline silicon-insulator-polycrystalline silicon capacitance, metal-insulator-polysilicon capacitance, metal-insulator-metal capacitor, metal-oxide-metal capacitor or mos capacitance.
Optionally, described sampling unit also comprises the second impedor, described the first capacitive reactive element is connected with described the first impedor by described the second impedor, and described the first impedor and the described second impedor link are as the output terminal of the described control voltage of described sampling unit output.
Optionally, described sampling unit comprises and is connected between described the first power lead and described second source line the 3rd impedor, the 4th impedor of series connection and the transistor group consisted of at least one transistor successively; Transistor in described transistor group becomes cascaded structure, and each transistorized grid is connected with drain electrode separately; Described the 3rd impedor and described the 4th impedor link are as the output terminal of the described control voltage of described sampling unit output.
Optionally, described the 3rd impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance, and described the 4th impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance.
Optionally, described electrostatic discharge testing circuit also comprises latch unit, is suitable for described the first detection signal or the second detection signal are latched to rear output.
Based on above-mentioned electrostatic discharge testing circuit, the present invention also provides a kind of electrostatic discharge treatment system, comprise processing unit, discharge cell and at least two above-mentioned electrostatic discharge testing circuits, described processing unit is suitable for receiving the detection signal of described at least two electrostatic discharge testing circuits output, and when the first detection signal quantity received is more than or equal to the quantity of the second detection signal, triggers release electrostatic potential on described the first power lead and second source line of described discharge cell.
Optionally, described discharge cell comprises discharge transistor, the first end of described discharge transistor is suitable for connecting described processing unit, and the second end of described discharge transistor is suitable for connecting described the first power lead, and the 3rd end of described discharge transistor is suitable for connecting described second source line.
Optionally, described discharge transistor is metal-oxide-semiconductor or triode.
Compared with prior art, technical scheme of the present invention has the following advantages:
By sampling unit, the voltage on power lead is sampled, control voltage to produce.Amplifier unit is according to the different detection signal of comparative result output of the threshold voltage of described control voltage and described amplifier unit.The voltage-regulation unit that also comprises the threshold voltage that can regulate described amplifier unit due to electrostatic discharge testing circuit of the present invention, by regulating the threshold voltage of described amplifier unit, the electrostatic potential that can detect can be set, and therefore, the sensing range of electrostatic discharge testing circuit broadens.
Due to described sampling unit, by can the device of electrostatic discharge responsive being formed, can catch electrostatic potential less on power lead, therefore, electrostatic discharge testing circuit of the present invention can be used in the electrostatic detection of the system level chip inside that electrostatic potential is less.
In possibility, described sampling unit consists of resistance device and capacitor element, control capacittance device and resistance device can change the response time of electrostatic discharge testing circuit to electrostatic discharge event, therefore, can regulate the detection sensitivity of described electrostatic discharge testing circuit.
Further, electrostatic discharge treatment system provided by the invention can be carried out analysis-by-synthesis according to the detection signal of a plurality of electrostatic discharge testing circuit outputs, after analysis, electrostatic discharge event is processed, and has improved the stability of chip system.
The accompanying drawing explanation
Fig. 1 is the circuit diagram of existing a kind of electrostatic discharge testing circuit;
Fig. 2 is the electrical block diagram of the electrostatic discharge testing circuit of embodiment of the present invention;
Fig. 3 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 1;
Fig. 4 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 2;
Fig. 5 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 3;
Fig. 6 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 4;
Fig. 7 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 5;
Fig. 8 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 6;
Fig. 9 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 7;
Figure 10 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 8;
Figure 11 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 9;
Figure 12 is the electrical block diagram of the electrostatic discharge treatment system of the embodiment of the present invention.
Embodiment
Just as described in the background art, electrostatic discharge testing circuit shown in Figure 1 has the detection signal of high level by the electrostatic potential that static discharge produces by all diode breakdown in diode group 11 with generation, the electrostatic potential that therefore, can detect must be greater than the voltage breakdown sum of all diodes.
For example, described diode group 11 adopts the diode series connection that voltage breakdown is identical, the magnitude of voltage of the voltage breakdown of every diode is VBR, if the diode of series connection is one, the electrostatic potential that magnitude of voltage is greater than VBR can be detected, and the electrostatic potential that magnitude of voltage is less than or equal to VBR just can not be detected; If the diode of series connection is two, the electrostatic potential that magnitude of voltage is greater than 2VBR can be detected, and the electrostatic potential that magnitude of voltage is less than or equal to 2VBR just can not be detected.Therefore, existing electrostatic discharge testing circuit can not detect less electrostatic potential, and sensing range is narrower.
Technical solution of the present invention provides a kind of sensing range wide testing circuit.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
The electrical block diagram of the electrostatic discharge testing circuit of the technical solution of the present invention that reference is shown in Figure 2, described electrostatic discharge testing circuit comprises sampling unit 21, amplifier unit 22 and voltage-regulation unit 23.
Described sampling unit 21 is coupled between the first power lead Vdd and second source line Vss, and the voltage on be suitable for sampling described the first power lead Vdd and second source line Vss is controlled voltage Vi with output.The voltage that the voltage that described the first power lead Vdd provides provides higher than described second source line Vss, usually, described the first power lead Vdd provides the supply voltage of high level, and described second source line Vss provides ground voltage.
Described amplifier unit 22 couples described sampling unit 21 and described voltage-regulation unit 23, be suitable for receiving described control voltage Vi, threshold voltage output detection signal according to described control voltage Vi and described amplifier unit 22, when being greater than the threshold voltage of described amplifier unit 22, described control voltage Vi by output terminal out output the first detection signal, by output terminal out, exports the second detection signal when described control voltage Vi is less than the threshold voltage of described amplifier unit 22.
Described voltage-regulation unit 23 is suitable for regulating the threshold voltage of described amplifier unit 22.
Structure and principle of work for understanding better electrostatic discharge testing circuit provided by the invention, be described in detail below in conjunction with accompanying drawing and specific embodiment.
Embodiment 1
Fig. 3 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 1.
With reference to figure 3, sampling unit 21a comprises the first impedor R1 and the first capacitive reactive element C1.The end of described the first impedor R1 connects described the first power lead Vdd, and the other end of described the first impedor R1 connects the end of described the first capacitive reactive element C1 and as described sampling unit 21a, exports the output terminal of described control voltage Vi.The other end of described the first capacitive reactive element C1 connects described second source line Vss.
Described the first impedor R1 can consist of the various devices that contain resistance, comprises polysilicon resistance, active area resistance, trap resistance or MOS channel resistance etc.Described the first capacitive reactive element C1 can consist of capacitor element, comprises polycrystalline silicon-insulator-polycrystalline silicon capacitance, metal-insulator-polysilicon capacitance, metal-insulator-metal capacitor, metal-oxide-metal capacitor or mos capacitance etc.
Described amplifier unit 22 comprises a PMOS pipe P1 and the NMOS pipe N1 that grid is connected.The grid of a described PMOS pipe P1 is suitable for receiving described control voltage Vi, and the drain electrode of a described PMOS pipe P1 is connected with the drain electrode that a described NMOS manages N1 and as the output terminal out of described amplifier unit 22 output detection signals.
In the present embodiment, described amplifier unit 22 manages by a PMOS pipe P1 and a NMOS CMOS phase inverter that N1 forms.The high level signal corresponding digital signals " 1 " of described CMOS phase inverter output, the low level signal corresponding digital signals " 0 " of described CMOS phase inverter output.
When described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, a described PMOS pipe P1 cut-off, a described NMOS pipe N1 conducting, the first detection signal of output is low level signal; When described control voltage Vi was reduced to the threshold voltage that equals described amplifier unit 22, the signal of described CMOS phase inverter output was high level signal by the low level signal saltus step; When described control voltage Vi is less than the threshold voltage of described amplifier unit 22, a described PMOS pipe P1 conducting, a described NMOS pipe N1 cut-off, the second detection signal of output is high level signal; When described control voltage Vi was increased to the threshold voltage that equals described amplifier unit 22, the signal of described CMOS phase inverter output was low level signal by the high level signal saltus step.
The critical voltage of the threshold voltage of described amplifier unit 22 when controlling the detection signal saltus step of described amplifier unit 22 outputs.Described critical voltage is that device and the circuit structure included to amplifier unit 22 is relevant.In the present embodiment, the source voltage of the threshold voltage of described amplifier unit 22 and the size of the size of a described PMOS pipe P1, a described NMOS pipe N1, a described PMOS pipe P1 is relevant with the source voltage of a described NMOS pipe N1.
The source voltage of N1 is managed to regulate the threshold voltage of described amplifier unit 22 by source voltage and/or a described NMOS who regulates a described PMOS pipe P1 in described voltage-regulation unit.In the present embodiment, described voltage-regulation unit comprises the PMOS pipe group 23a consisted of at least one PMOS pipe.First PMOS pipe P31 in described PMOS pipe group 23a,, a n PMOS pipe P3n becomes cascaded structure, n is the quantity of the PMOS pipe of connecting.
The drain electrode of each PMOS pipe is connected with the source electrode of another PMOS pipe of series connection, and the grid of each PMOS pipe is connected with drain electrode separately.The source electrode of described first PMOS pipe P31 is as the first end of described PMOS pipe group 23a, and the drain electrode of described n PMOS pipe P3n is as the second end of described PMOS pipe group 23a.
The first end of described PMOS pipe group 23a is connected with described the first power lead Vdd, and the second end of described PMOS pipe group 23a connects the source electrode of a described PMOS pipe P1.In the present embodiment, the first end of described PMOS pipe group 23a is suitable for inputting the first supply voltage, and described the first supply voltage is the voltage that described the first power lead Vdd provides.In other embodiments, the first end of described PMOS pipe group 23a also can connect other power supplies, and the present invention is not construed as limiting this.
Because described amplifier unit 22 is inputted described the first supply voltage by described voltage-regulation unit, described voltage-regulation unit carries out dividing potential drop, therefore, the source voltage of a PMOS pipe P1 in described amplifier unit 22 reduces, the ducting capacity of a described PMOS pipe P1 weakens, thereby the threshold voltage of described amplifier unit 22 is reduced.
Pressure drop on described PMOS pipe group 23a is n * Vthp, and Vthp is the threshold voltage of each series connection PMOS pipe.In described PMOS pipe group 23a, the quantity of series connection PMOS pipe is more, the dividing potential drop effect of described PMOS pipe group 23a is stronger, the source voltage of a PMOS pipe P1 in described amplifier unit 22 is lower, therefore, the ducting capacity of a described PMOS pipe P1 is more weak, thereby makes the threshold voltage of described amplifier unit 22 lower.
Below in conjunction with circuit shown in Figure 3 and the concrete course of work thereof, advantage of the present invention is described further.
When the electrostatic potential that static discharge produces on described the first power lead Vdd, not occurring, described control voltage Vi is pulled to noble potential by described the first impedor R1, therefore, described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, a described NMOS pipe N1 conducting, a described PMOS pipe P1 cut-off, the first detection signal of described amplifier unit 22 output low levels.
When the electrostatic potential that static discharge produces on described the first power lead Vdd, occurring, described electrostatic potential is pulse voltage, give described the first capacitive reactive element C1 charging, described control voltage Vi is pulled to electronegative potential by described the first capacitive reactive element C1, therefore, described control voltage Vi is less than the threshold voltage of described amplifier unit 22, a described NMOS pipe N1 cut-off, a described PMOS pipe P1 conducting, the second detection signal of described amplifier unit 22 output high level.
Because described PMOS pipe group 23a makes the threshold voltage of described amplifier unit 22, reduce, therefore, while the less electrostatic potential of static discharge generation on described the first power lead Vdd, occurring, described electrostatic potential also can be detected.
It should be noted that, in the present embodiment, can also regulate the detection sensitivity of described electrostatic discharge testing circuit, the detection sensitivity of electrostatic discharge testing circuit refers to from producing the time of electrostatic potential to the detection signal of the corresponding described electrostatic potential of described electrostatic discharge testing circuit output.Described sampling unit 21a is comprised of described the first impedor R1 and described the first capacitive reactive element C1, due to capacitive reactive element is discharged and recharged and needs the time, therefore, regulate the size of described the first impedor R1 and described the first capacitive reactive element C1, can regulate the response time of described electrostatic discharge testing circuit to electrostatic potential, the detection sensitivity that namely can regulate described electrostatic discharge testing circuit.
Embodiment 2
Fig. 4 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 2.With reference to figure 4, embodiment 2 is with the difference of embodiment 1: sampling unit 21b comprises described the first impedor R1 and described the first capacitive reactive element C1, also comprise the second impedor R2, described the first capacitive reactive element C1 is connected with described the first impedor R1 by described the second impedor R2, and the link of described the first impedor R1 and described the second impedor R2 is as the output terminal of the described control voltage Vi of described sampling unit 21b output.
Described the second impedor R2 can consist of the various devices that contain resistance, comprises polysilicon resistance, active area resistance, trap resistance or MOS channel resistance etc.
In the present embodiment, described sampling unit 21b comprises described the second impedor R2, described the second impedor R2 can change the charging current to described the first capacitive reactive element C1, further regulates the sensitivity of described electrostatic discharge testing circuit, makes the adjustment of sensitivity scope wider.
Embodiment 3
Fig. 5 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 3.With reference to figure 5, embodiment 3 is with the difference of embodiment 1: described the first impedor R1 and described the first capacitive reactive element C1 transposition, an end that is described the first impedor R1 connects described second source line Vss, the other end of described the first impedor R1 connects the end of described the first capacitive reactive element C1 and as sampling unit 21c, exports the output terminal of described control voltage Vi, and the other end of described the first capacitive reactive element C1 connects described the first power lead Vdd.
In the present embodiment, when the electrostatic potential that static discharge produces on described the first power lead Vdd, not occurring, described control voltage Vi is pulled to electronegative potential by described the first impedor R1, therefore, described control voltage Vi is less than the threshold voltage of described amplifier unit 22, a described PMOS pipe P1 conducting, a described NMOS pipe N1 cut-off, the second detection signal of the high level of described amplifier unit 22 outputs.
When the electrostatic potential that static discharge produces on described the first power lead Vdd, occurring, described electrostatic potential is pulse voltage, give described the first capacitive reactive element C1 charging, described control voltage Vi is pulled to noble potential by described the first capacitive reactive element C1, therefore, described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, a described NMOS pipe N1 conducting, a described PMOS pipe P1 cut-off, low level first detection signal of described amplifier unit 22 outputs.
Because described PMOS pipe group 23a makes the threshold voltage of described amplifier unit 22, reduce, therefore, while the less electrostatic potential of static discharge generation on described the first power lead Vdd, occurring, described electrostatic potential also can be detected.
Fig. 6 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 4.With reference to figure 6, embodiment 4 is with the difference of embodiment 3: sampling unit 21d comprises described the first impedor R1 and described the second capacitive reactive element C1, also comprise the second impedor R2, described the first capacitive reactive element C1 is connected with described the first impedor R1 by described the second impedor R2, and the link of described the first impedor R1 and described the second impedor R2 is as the output terminal of the described control voltage Vi of described sampling unit 21d output.
Described the second impedor R2 can consist of the various devices that contain resistance, comprises polysilicon resistance, active area resistance, trap resistance or MOS channel resistance etc.
Described sampling unit 21d comprises described the second impedor R2, and described the second impedor R2 can change the charging current to described the first capacitive reactive element C1, further regulates the sensitivity of described electrostatic discharge testing circuit, makes the adjustment of sensitivity scope wider.
Embodiment 5
Fig. 7 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 5.With reference to figure 7, embodiment 5 is with the difference of embodiment 1: sampling unit 21e comprises the 3rd impedor R3, the 4th impedor R4 and the transistor group 24a formed by least one transistor, the end of described the 3rd impedor R3 is suitable for connecting described the first power lead Vdd, the other end of described the 3rd impedor R3 connects the end of described the 4th impedor R4 and as described sampling unit 21e, exports the output terminal of described control voltage Vi, the other end of described the 4th impedor R4 connects the first end of described transistor group 24a, the second end of described transistor group 24a is suitable for connecting described second source line Vss.
In the present embodiment, the transistor in described transistor group 24a is the NMOS pipe.First NMOS pipe N41 in described transistor group 24a,, a m NMOS pipe N4m becomes cascaded structure, m is the quantity of the NMOS pipe of connecting.The drain electrode of each NMOS pipe is connected with the source electrode of another NMOS pipe of series connection, and the grid of each NMOS pipe is connected with drain electrode separately.The drain electrode of described first NMOS pipe N41 is as the first end of described transistor group 24a, and the source electrode of described m NMOS pipe N4m is as the second end of described transistor group 24a.
In the present embodiment, NMOS pipe in described transistor group 24a becomes diode to connect, when the voltage on described the first power lead Vdd during lower than m * Vthn, and the NMOS pipe cut-off in described transistor group 24a, wherein, Vthn is the threshold voltage of each NMOS pipe in described transistor group 24a.
When the electrostatic potential that static discharge produces on described the first power lead Vdd, not occurring, NMOS pipe cut-off in described transistor group 24a, described control voltage Vi is pulled to noble potential by described the 3rd impedor R3, therefore, described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, a described PMOS pipe P1 cut-off, a described NMOS pipe N1 conducting, the first detection signal of described amplifier unit 22 output low levels.
When the electrostatic potential that static discharge produces on described the first power lead Vdd, occurring, voltage on described the first power lead Vdd raises, make the NMOS pipe conducting in described transistor group 24a, described control voltage Vi is pulled to electronegative potential by described the 4th impedor R4 and described transistor group 24a, therefore, described control voltage Vi is less than the threshold voltage of described amplifier unit 22, a described NMOS pipe N1 cut-off, a described PMOS pipe P1 conducting, the second detection signal of described amplifier unit 22 output high level.
Embodiment 6
Fig. 8 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 6.With reference to figure 8, embodiment 6 is with the difference of embodiment 5: the transistor in the transistor group 24b in sampling unit 21f is the PMOS pipe, the first end of described transistor group 24b is suitable for connecting described the first power lead Vdd, the second end of described transistor group 24b connects the end of described the 4th impedor R4, the other end of described the 4th impedor R4 is connected and exports as described sampling unit 21f the output terminal of described control voltage Vi with the end of described the 3rd impedor R3, the other end of described the 3rd impedor R3 is suitable for connecting described second source line Vss.
First PMOS pipe N41 in described transistor group 24b,, a m PMOS pipe P4m becomes cascaded structure, m is the quantity of the PMOS pipe of connecting.The drain electrode of each PMOS pipe is connected with the source electrode of another PMOS pipe of series connection, and the grid of each PMOS pipe is connected with drain electrode separately.The source electrode of described first PMOS pipe P41 is as the first end of described transistor group 24b, and the drain electrode of described m PMOS pipe P4m is as the second end of described transistor group 24b.
In the present embodiment, PMOS pipe in described transistor group 24b becomes diode to connect, when the voltage on described the first power lead Vdd during lower than m * Vthp, and the PMOS pipe cut-off in described transistor group 24b, wherein, Vthp is the threshold voltage of each PMOS pipe in described transistor group 24b.
When the electrostatic potential that static discharge produces on described the first power lead Vdd, not occurring, PMOS pipe cut-off in described transistor group 24b, described control voltage Vi is pulled to electronegative potential by described the 3rd impedor R3, therefore, described control voltage Vi is less than the threshold voltage of described amplifier unit 22, a described PMOS pipe P1 conducting, a described NMOS pipe N1 cut-off, the second detection signal of described amplifier unit 22 output high level.
When the electrostatic potential that static discharge produces on described the first power lead Vdd, occurring, voltage on described the first power lead Vdd raises, make the PMOS pipe conducting in described transistor group 24b, described control voltage Vi is pulled to noble potential by described the 4th impedor R4 and described transistor group 24b, therefore, described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, a described NMOS pipe N1 conducting, a described PMOS pipe P1 cut-off, the first detection signal of described amplifier unit 22 output low levels.
Embodiment 7
Fig. 9 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 7.With reference to figure 9, embodiment 7 is with the difference of embodiment 1: described voltage-regulation unit comprises the NMOS pipe group 23b consisted of at least one NMOS pipe, the first end of described NMOS pipe group 23b connects the source electrode of a described NMOS pipe N1, and the second end of described NMOS pipe group 23b is suitable for inputting second source voltage.
First NMOS pipe N31 in described NMOS pipe group 23b,, a n NMOS pipe N3n becomes cascaded structure, n is the quantity of the NMOS pipe of connecting.The drain electrode of each NMOS pipe is connected with the source electrode of another NMOS pipe of series connection, and the grid of each NMOS pipe is connected with drain electrode separately.The drain electrode of described first NMOS pipe N31 is as the first end of described NMOS pipe group 23b, and the source electrode of described n NMOS pipe N3n is as the second end of described NMOS pipe group 23b.
In the present embodiment, the second end of described NMOS pipe group 23b is connected with described second source line Vss, and described second source voltage is the voltage that described second source line Vss provides.In other embodiments, the second end of described NMOS pipe group 23b also can connect other power supplies, and the present invention is not construed as limiting this.
Because described amplifier unit 22 is inputted described second source voltage by described voltage-regulation unit, described voltage-regulation unit carries out dividing potential drop, therefore, the source voltage of a NMOS pipe N1 in described amplifier unit 22 raises, the ducting capacity of a described NMOS pipe N1 weakens, thereby the threshold voltage of described amplifier unit 22 is raise.
Pressure drop on described NMOS pipe group 23b is n * Vthn, and Vthn is the threshold voltage of each series connection NMOS pipe.In described NMOS pipe group 23b, the quantity of series connection NMOS pipe is more, the dividing potential drop effect of described NMOS pipe group 23b is stronger, the source voltage of a NMOS pipe N1 in described amplifier unit 22 is higher, therefore, the ducting capacity of a described NMOS pipe N1 is more weak, thereby makes the threshold voltage of described amplifier unit 22 higher.
Due to the threshold voltage rising of described amplifier unit 22, the electrostatic potential that can detect raises, and can prevent the error detection caused due to noise.
Embodiment 8
Figure 10 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 8.With reference to Figure 10, embodiment 8 is with the difference of embodiment 1: described voltage-regulation unit comprises the PMOS pipe group 23a consisted of at least one PMOS pipe and the NMOS pipe group 23b consisted of at least one NMOS pipe, the end of described PMOS pipe group 23a is suitable for inputting the first supply voltage, and the other end of described PMOS pipe group 23a connects the source electrode of a described PMOS pipe P1; The end of described NMOS pipe group 23b is suitable for receiving second source voltage, and the other end of described NMOS pipe group 23b connects the source electrode of described NMOS pipe N1; Described the first supply voltage is higher than described second source voltage.
In the present embodiment, but the described PMOS pipe group in the particular circuit configurations reference example 1 of described PMOS pipe group 23a, but the described NMOS pipe group in the concrete structure reference example 7 of described NMOS pipe group 23b, described sampling unit 21 can, with reference to previous embodiment, not repeat them here.
Described PMOS pipe group 23a can reduce the source voltage of a described PMOS pipe P1, can the raise source voltage of a described NMOS pipe N1 of described NMOS pipe group 23b, by described PMOS pipe group 23a and described NMOS pipe group 23b, regulate the threshold voltage of described amplifier unit 22, the sensing range that can regulate described electrostatic discharge testing circuit.
Embodiment 9
Figure 11 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 9.With reference to Figure 11, described electrostatic discharge testing circuit comprises sampling unit 21, amplifier unit 22, voltage-regulation unit 23, also comprises latch unit 25, and described latch unit 25 is suitable for described the first detection signal or the second detection signal are latched to rear output.The concrete structure of described sampling unit 21, amplifier unit 22 and voltage-regulation unit 23 can, with reference to previous embodiment, not repeat them here.
Described latch unit 25 can be the RS latch, described RS latch can carry out shaping to described the first detection signal and described the second detection signal, described the first detection signal is converted to digital signal " 0 ", described the second detection signal is converted to digital signal " 1 ".
With reference to Figure 12, technical solution of the present invention also provides a kind of electrostatic discharge treatment system.Described electrostatic discharge treatment system comprises processing unit 122, discharge cell 123 and at least two electrostatic discharge testing circuits: electrostatic discharge testing circuit 1211 ..., electrostatic discharge testing circuit 121N, N is the quantity of described electrostatic discharge circuit.The structure of described electrostatic discharge testing circuit can be Fig. 3～any one circuit structure shown in Figure 11.
The electrostatic potential produced by static discharge on the system level chip internal power cord is more much smaller than the electrostatic potential that the static discharge position occurs.For the strong circuit of antistatic interference performance, the electrostatic potential on power lead can not exert an influence to its work, does not need electrostatic potential is processed.And for the circuit to the electrostatic interference sensitivity, less electrostatic potential also can cause it to work, need to process electrostatic potential.Therefore, a plurality of electrostatic discharge testing circuits can be set in chip, the detection signal by judging different electrostatic discharge testing circuits need to be processed electrostatic potential determining whether.
It should be noted that, the sensing range of a plurality of electrostatic discharge testing circuits and detection sensitivity can be identical, are arranged on the diverse location in chip; The sensing range of a plurality of electrostatic discharge testing circuits and detection sensitivity also can be different, are arranged on the same position in chip; The sensing range of a plurality of electrostatic discharge testing circuits and detection sensitivity can also be different, are arranged on the diverse location in chip.
Due to detection signal of each electrostatic discharge testing circuit output, therefore, at least two detection signals of the corresponding output of described at least two electrostatic discharge testing circuits.Described processing unit 122 is suitable for receiving described at least two detection signals, and the quantity of the first detection signal at least two detection signals that receive and the quantity of the second detection signal are compared, when the first detection signal quantity received is more than or equal to the quantity of the second detection signal, trigger release electrostatic potential on described the first power lead Vdd and described second source line Vss of described discharge cell 123.That is to say, the quantity by the first detection signal and the second detection signal at least two detection signals analyzing described at least two electrostatic discharge testing circuits output, can determine whether to process electrostatic potential.
Described discharge cell 123 comprises discharge transistor, the first end of described discharge transistor is suitable for connecting described processing unit 122, the second end of described discharge transistor is suitable for connecting described the first power lead Vdd, and the 3rd end of described discharge transistor is suitable for connecting described second source line Vss.Described discharge transistor can be metal-oxide-semiconductor or triode.
Electrostatic discharge treatment system provided by the invention can be analyzed according to the detection signal of a plurality of electrostatic discharge testing circuit outputs, after analysis, electrostatic discharge event is processed, and prevents the error detection of being brought by noise, has improved the stability of chip system.
In sum, electrostatic discharge testing circuit provided by the invention, threshold voltage by resonance-amplifier unit, voltage-regulation unit, the sensing range of electrostatic discharge testing circuit broadens, and, can catch change in voltage less on power lead, electrostatic discharge testing circuit of the present invention can be used in the detection of the system level chip inside that electrostatic potential is less.
Although the present invention discloses as above, the present invention not is defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (14)
1. an electrostatic discharge testing circuit, is characterized in that, comprising: sampling unit, amplifier unit and voltage-regulation unit, wherein,
The voltage that described sampling unit is suitable for sampling on the first power lead and second source line is controlled voltage, the voltage that the voltage that described the first power lead provides provides higher than described second source line with output;
The detection signal that described amplifier unit is suitable for exporting when described control voltage is greater than the threshold voltage of described amplifier unit is the first detection signal, and the detection signal of exporting when described control voltage is less than the threshold voltage of described amplifier unit is the second detection signal;
Described voltage-regulation unit is suitable for regulating the threshold voltage of described amplifier unit.
2. electrostatic discharge testing circuit according to claim 1, is characterized in that, described amplifier unit comprises a PMOS pipe and the NMOS pipe that grid is connected; The grid of a described PMOS pipe is suitable for receiving described control voltage, and the drain electrode of a described PMOS pipe is connected and exports as described amplifier unit the output terminal of described detection signal with the drain electrode of a described NMOS pipe.
3. electrostatic discharge testing circuit according to claim 2, it is characterized in that, described voltage-regulation unit comprises the PMOS pipe group consisted of at least one PMOS pipe, PMOS pipe in described PMOS pipe group becomes cascaded structure, the grid of each PMOS pipe is connected with drain electrode separately, one end of described PMOS pipe group is suitable for inputting the first supply voltage, and the other end of described PMOS pipe group connects the source electrode of a described PMOS pipe.
4. electrostatic discharge testing circuit according to claim 2, it is characterized in that, described voltage-regulation unit comprises the NMOS pipe group consisted of at least one NMOS pipe, NMOS pipe in described NMOS pipe group becomes cascaded structure, the grid of each NMOS pipe is connected with drain electrode separately, one end of described NMOS pipe group is suitable for inputting second source voltage, and the other end of described NMOS pipe group connects the source electrode of a described NMOS pipe.
5. electrostatic discharge testing circuit according to claim 2, is characterized in that, described voltage-regulation unit comprises the PMOS pipe group consisted of at least one PMOS pipe and the NMOS pipe group consisted of at least one NMOS pipe; PMOS pipe in described PMOS pipe group becomes cascaded structure, and the grid of each PMOS pipe is connected with drain electrode separately, and an end of described PMOS pipe group is suitable for inputting the first supply voltage, and the other end of described PMOS pipe group connects the source electrode of a described PMOS pipe; NMOS pipe in described NMOS pipe group becomes cascaded structure, and the grid of each NMOS pipe is connected with drain electrode separately, and an end of described NMOS pipe group is suitable for receiving second source voltage, and the other end of described NMOS pipe group connects the source electrode of described NMOS pipe; Described the first supply voltage is higher than described second source voltage.
6. electrostatic discharge testing circuit according to claim 1, it is characterized in that, described sampling unit comprises and is connected in the first impedor and first capacitive reactive element of connecting between described the first power lead and described second source line, and the link of described the first impedor and described the first capacitive reactive element is as the output terminal of the described control voltage of described sampling unit output.
7. electrostatic discharge testing circuit according to claim 6, it is characterized in that, described the first impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance, and described the first capacitive reactive element is polycrystalline silicon-insulator-polycrystalline silicon capacitance, metal-insulator-polysilicon capacitance, metal-insulator-metal capacitor, metal-oxide-metal capacitor or mos capacitance.
8. according to claim 6 or the described electrostatic discharge testing circuit of 7 any one, it is characterized in that, described sampling unit also comprises the second impedor, described the first capacitive reactive element is connected with described the first impedor by described the second impedor, and described the first impedor and the described second impedor link are as the output terminal of the described control voltage of described sampling unit output.
9. electrostatic discharge testing circuit according to claim 1, it is characterized in that, described sampling unit comprises the 3rd impedor, the 4th impedor that is connected between described the first power lead and described second source line series connection successively and the transistor group consisted of at least one transistor; Transistor in described transistor group becomes cascaded structure, and each transistorized grid is connected with drain electrode separately; Described the 3rd impedor and described the 4th impedor link are as the output terminal of the described control voltage of described sampling unit output.
10. electrostatic discharge testing circuit according to claim 9, it is characterized in that, described the 3rd impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance, and described the 4th impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance.
11. electrostatic discharge testing circuit according to claim 1, is characterized in that, also comprises latch unit, is suitable for described the first detection signal or the second detection signal are latched to rear output.
12. electrostatic discharge treatment system, it is characterized in that, comprise processing unit, discharge cell and at least two described electrostatic discharge testing circuits of claim 1 to 11 any one, described processing unit is suitable for receiving the detection signal of described at least two electrostatic discharge testing circuits output, and when the first detection signal quantity received is more than or equal to the quantity of the second detection signal, triggers release electrostatic potential on described the first power lead and second source line of described discharge cell.
13. electrostatic discharge treatment system according to claim 12, it is characterized in that, described discharge cell comprises discharge transistor, the first end of described discharge transistor is suitable for connecting described processing unit, the second end of described discharge transistor is suitable for connecting described the first power lead, and the 3rd end of described discharge transistor is suitable for connecting described second source line.
14. electrostatic discharge treatment system according to claim 13, is characterized in that, described discharge transistor is metal-oxide-semiconductor or triode.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106707073A (en) * | 2017-03-08 | 2017-05-24 | 苏州天华超净科技股份有限公司 | Electrostatic discharging detection circuit and system |
| CN108347044A (en) * | 2017-01-25 | 2018-07-31 | 瑞昱半导体股份有限公司 | Electrostatic discharge protection circuit |
| CN108631284A (en) * | 2017-03-21 | 2018-10-09 | 瑞昱半导体股份有限公司 | ESD protection circuit |
| CN109950889A (en) * | 2017-12-20 | 2019-06-28 | 意法半导体国际有限公司 | Full swing for electrostatic discharge (ESD) protection just arrives negative MOSFET power clamp |
| CN111312705A (en) * | 2018-12-11 | 2020-06-19 | 瑞萨电子株式会社 | Semiconductor device and semiconductor device system |
| WO2022056901A1 (en) * | 2020-09-21 | 2022-03-24 | 京东方科技集团股份有限公司 | Display substrate and display device |
| WO2022188326A1 (en) * | 2021-03-10 | 2022-09-15 | 长鑫存储技术有限公司 | Electrostatic protection circuit and semiconductor device |
| US11842995B2 (en) | 2021-03-10 | 2023-12-12 | Changxin Memory Technologies, Inc. | ESD protection circuit and semiconductor device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003264233A (en) * | 2002-03-07 | 2003-09-19 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit |
| US6930612B1 (en) * | 2002-10-04 | 2005-08-16 | Credence Technologies, Inc. | Device and method of monitoring grounding of personnel and equipment in ESD-sensitive areas |
| CN101493489A (en) * | 2008-01-23 | 2009-07-29 | 奇景光电股份有限公司 | Transient detection circuit for ESD protection |
| CN101533051A (en) * | 2008-03-13 | 2009-09-16 | 奇景光电股份有限公司 | Digital converters and electronic products having the same |
| CN101599487A (en) * | 2008-06-05 | 2009-12-09 | 智原科技股份有限公司 | Electrostatic discharge testing circuit and its correlation technique |
| CN101826511A (en) * | 2009-03-03 | 2010-09-08 | 瑞昱半导体股份有限公司 | Electrostatic protection circuit |
| CN203396864U (en) * | 2013-07-31 | 2014-01-15 | 格科微电子（上海）有限公司 | Electrostatic discharge detection circuit and processing system |
-
2013
- 2013-07-31 CN CN201310330454.0A patent/CN103412216B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003264233A (en) * | 2002-03-07 | 2003-09-19 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit |
| US6930612B1 (en) * | 2002-10-04 | 2005-08-16 | Credence Technologies, Inc. | Device and method of monitoring grounding of personnel and equipment in ESD-sensitive areas |
| CN101493489A (en) * | 2008-01-23 | 2009-07-29 | 奇景光电股份有限公司 | Transient detection circuit for ESD protection |
| CN101533051A (en) * | 2008-03-13 | 2009-09-16 | 奇景光电股份有限公司 | Digital converters and electronic products having the same |
| CN101599487A (en) * | 2008-06-05 | 2009-12-09 | 智原科技股份有限公司 | Electrostatic discharge testing circuit and its correlation technique |
| CN101826511A (en) * | 2009-03-03 | 2010-09-08 | 瑞昱半导体股份有限公司 | Electrostatic protection circuit |
| CN203396864U (en) * | 2013-07-31 | 2014-01-15 | 格科微电子（上海）有限公司 | Electrostatic discharge detection circuit and processing system |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108347044A (en) * | 2017-01-25 | 2018-07-31 | 瑞昱半导体股份有限公司 | Electrostatic discharge protection circuit |
| US10931101B2 (en) | 2017-01-25 | 2021-02-23 | Realtek Semiconductor Corporation | Electrostatic discharge protection circuit |
| CN106707073A (en) * | 2017-03-08 | 2017-05-24 | 苏州天华超净科技股份有限公司 | Electrostatic discharging detection circuit and system |
| CN108631284A (en) * | 2017-03-21 | 2018-10-09 | 瑞昱半导体股份有限公司 | ESD protection circuit |
| CN108631284B (en) * | 2017-03-21 | 2020-08-25 | 瑞昱半导体股份有限公司 | Electrostatic discharge protection circuit |
| CN109950889B (en) * | 2017-12-20 | 2022-06-24 | 意法半导体国际有限公司 | Full swing positive-to-negative MOSFET power clamp for electrostatic discharge protection |
| CN109950889A (en) * | 2017-12-20 | 2019-06-28 | 意法半导体国际有限公司 | Full swing for electrostatic discharge (ESD) protection just arrives negative MOSFET power clamp |
| US11081881B2 (en) | 2017-12-20 | 2021-08-03 | Stmicroelectronics International N.V. | Full swing positive to negative MOSFET supply clamp for electrostatic discharge (ESD) protection |
| CN111312705A (en) * | 2018-12-11 | 2020-06-19 | 瑞萨电子株式会社 | Semiconductor device and semiconductor device system |
| WO2022056901A1 (en) * | 2020-09-21 | 2022-03-24 | 京东方科技集团股份有限公司 | Display substrate and display device |
| CN114641862A (en) * | 2020-09-21 | 2022-06-17 | 京东方科技集团股份有限公司 | Display substrate and display device |
| GB2610516A (en) * | 2020-09-21 | 2023-03-08 | Boe Technology Group Co Ltd | Display substrate and display device |
| US11804178B2 (en) | 2020-09-21 | 2023-10-31 | Chengdu Boe Optoelectronics Technology Co., Ltd. | Display substrate and display device |
| CN114641862B (en) * | 2020-09-21 | 2023-10-31 | 京东方科技集团股份有限公司 | Display substrate and display device |
| WO2022188326A1 (en) * | 2021-03-10 | 2022-09-15 | 长鑫存储技术有限公司 | Electrostatic protection circuit and semiconductor device |
| US11842995B2 (en) | 2021-03-10 | 2023-12-12 | Changxin Memory Technologies, Inc. | ESD protection circuit and semiconductor device |
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