CN103412216B - Electrostatic discharge testing circuit and disposal system - Google Patents
Electrostatic discharge testing circuit and disposal system Download PDFInfo
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- CN103412216B CN103412216B CN201310330454.0A CN201310330454A CN103412216B CN 103412216 B CN103412216 B CN 103412216B CN 201310330454 A CN201310330454 A CN 201310330454A CN 103412216 B CN103412216 B CN 103412216B
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Abstract
A kind of electrostatic discharge testing circuit and disposal system, described electrostatic discharge testing circuit and disposal system comprise: sampling unit, amplifier unit and voltage regulation unit, wherein, described sampling unit is suitable for voltage on sampling first power lead and second source line to export control voltage, the voltage that the voltage that described first power lead provides provides higher than described second source line; The detection signal that described amplifier unit is suitable for exporting when described control voltage is greater than the threshold voltage of described amplifier unit is the first detection signal, and the detection signal exported when described control voltage is less than the threshold voltage of described amplifier unit is the second detection signal; Described voltage regulation unit is suitable for the threshold voltage regulating described amplifier unit.Electrostatic discharge testing circuit provided by the invention can widen the sensing range of electrostatic discharge testing circuit, can be used in the detection of the less system level chip inside of electrostatic potential.
Description
Technical field
The present invention relates to static discharge technical field, particularly a kind of electrostatic discharge testing circuit and disposal system.
Background technology
Static discharge (ESD, Electro-StaticDischarge) be the principal element causing most of electronic package or electronic system to be subject to excessively electrically stress rupture, this destruction can cause the permanent damage of semiconductor devices, thus causes the inefficacy of integrate circuit function.And for system level chip, the electrostatic potential that chip internal power lead is produced by static discharge is more much smaller than the electrostatic potential that static discharge position occurs, the chip failure that static discharge causes is that logical circuit running status is disorderly, instead of directly destroys internal components.Therefore, usually adopt electrostatic discharge testing circuit to carry out the static discharge of detection system level chip, and output detections signal, the detection signal exported according to testing circuit by electrostatic discharge treatment system is processed electrostatic discharge event.
Fig. 1 is the circuit diagram of existing a kind of electrostatic discharge testing circuit.With reference to figure 1, described electrostatic discharge testing circuit comprises diode group 11 and resistance R.Described diode group 11 comprises the diode of multiple series connection, and the negative electrode of first diode D1 is suitable for connection first power lead Vdd, and the anode of last diode Dn connects the first end of described resistance R; Second end of described resistance R is suitable for connecting second source line Vss, the voltage that the voltage that described second source line Vss provides provides lower than described first power lead Vdd.The first end of described resistance R, as the output terminal of described electrostatic discharge testing circuit, is suitable for output detections signal V1.
When described first power lead Vdd occurs static discharge, all diodes in described diode group 11 are breakdown, have electric current through described resistance R, make described detection signal V1 switch to high level signal by low level signal.
But, on described first power lead Vdd, only there is electrostatic potential that static discharge produces when being greater than the voltage breakdown sum of all diodes in described diode group 11, by all diode breakdown in described diode group 11, the detection signal V1 of high level could be exported.Therefore, described electrostatic discharge testing circuit can not detect less electrostatic potential, and sensing range is narrower.
The Chinese patent application file that more technical schemes detected about static discharge can be CN101650394A with reference to publication number, denomination of invention is " electrostatic discharge detection device ".
Summary of the invention
What the present invention solved is the narrow problem of existing electrostatic discharge testing circuit sensing range.
For solving the problem, the invention provides a kind of electrostatic discharge testing circuit, comprise sampling unit, amplifier unit and voltage regulation unit, wherein, described sampling unit is suitable for voltage on sampling first power lead and second source line to export control voltage, the voltage that the voltage that described first power lead provides provides higher than described second source line; The detection signal that described amplifier unit is suitable for exporting when described control voltage is greater than the threshold voltage of described amplifier unit is the first detection signal, and the detection signal exported when described control voltage is less than the threshold voltage of described amplifier unit is the second detection signal; Described voltage regulation unit is suitable for the threshold voltage regulating described amplifier unit.
Optionally, described amplifier unit comprises the first connected PMOS of grid and the first NMOS tube; The grid of described first PMOS is suitable for receiving described control voltage, and the drain electrode of described first PMOS is connected with the drain electrode of described first NMOS tube and exports the output terminal of described detection signal as described amplifier unit.
Optionally, described voltage regulation unit comprises the PMOS group be made up of at least one PMOS, PMOS in described PMOS group becomes cascaded structure, the grid of each PMOS is connected with respective drain electrode, one end of described PMOS group is suitable for input first supply voltage, and the other end of described PMOS group connects the source electrode of described first PMOS.
Optionally, described voltage regulation unit comprises the NMOS tube group be made up of at least one NMOS tube, NMOS tube in described NMOS tube group becomes cascaded structure, the grid of each NMOS tube is connected with respective drain electrode, one end of described NMOS tube group is suitable for input second source voltage, and the other end of described NMOS tube group connects the source electrode of described first NMOS tube.
Optionally, described voltage regulation unit comprises the PMOS group be made up of at least one PMOS and the NMOS tube group be made up of at least one NMOS tube; PMOS in described PMOS group becomes cascaded structure, and the grid of each PMOS is connected with respective drain electrode, and one end of described PMOS group is suitable for input first supply voltage, and the other end of described PMOS group connects the source electrode of described first PMOS; NMOS tube in described NMOS tube group becomes cascaded structure, and the grid of each NMOS tube is connected with respective drain electrode, and one end of described NMOS tube group is suitable for receiving second source voltage, and the other end of described NMOS tube group connects the source electrode of described NMOS tube; Described first supply voltage is higher than described second source voltage.
Optionally, described sampling unit comprises the first impedor and the first capacitive reactive element that are connected to and connect between described first power lead and described second source line, and the link of described first impedor and described first capacitive reactive element exports the output terminal of described control voltage as described sampling unit.
Optionally, described first impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance, and described first capacitive reactive element is polycrystalline silicon-insulator-polycrystalline silicon capacitance, metal-insulator-polysilicon capacitance, metal-insulator-metal capacitor, metal-oxide-metal capacitor or mos capacitance.
Optionally, described sampling unit also comprises the second impedor, described first capacitive reactive element is connected with described first impedor by described second impedor, and described first impedor and described second impedor link export the output terminal of described control voltage as described sampling unit.
Optionally, described sampling unit comprises the 3rd impedor, the 4th impedor and the transistor group that is made up of at least one transistor that are connected to and connect successively between described first power lead and described second source line; Transistor in described transistor group becomes cascaded structure, and the grid of each transistor is connected with respective drain electrode; Described 3rd impedor and described 4th impedor link export the output terminal of described control voltage as described sampling unit.
Optionally, described 3rd impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance, and described 4th impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance.
Optionally, described electrostatic discharge testing circuit also comprises latch unit, is suitable for described first detection signal or the second detection signal to latch rear output.
Based on above-mentioned electrostatic discharge testing circuit, present invention also offers a kind of electrostatic discharge treatment system, comprise processing unit, discharge cell and at least two above-mentioned electrostatic discharge testing circuits, the detection signal that described in described processing unit is suitable for receiving, at least two electrostatic discharge testing circuits export, and the electrostatic potential triggering that when the first detection signal quantity received is more than or equal to the quantity of the second detection signal described discharge cell releases on described first power lead and second source line.
Optionally, described discharge cell comprises discharge transistor, the first end of described discharge transistor is suitable for connecting described processing unit, and the second end of described discharge transistor is suitable for connecting described first power lead, and the 3rd end of described discharge transistor is suitable for connecting described second source line.
Optionally, described discharge transistor is metal-oxide-semiconductor or triode.
Compared with prior art, technical scheme of the present invention has the following advantages:
By sampling unit, the voltage on power lead is sampled, to produce control voltage.Amplifier unit exports different detection signals according to the comparative result of the threshold voltage of described control voltage and described amplifier unit.The voltage regulation unit of the threshold voltage of adjustable described amplifier unit is also comprised due to electrostatic discharge testing circuit of the present invention, by regulating the threshold voltage of described amplifier unit, can arrange the electrostatic potential that can detect, therefore, the sensing range of electrostatic discharge testing circuit broadens.
Because described sampling unit is by forming the device of electrostatic discharge responsive, can catch electrostatic potential less on power lead, therefore, electrostatic discharge testing circuit of the present invention can be used in the electrostatic detection of the less system level chip inside of electrostatic potential.
In possibility, described sampling unit is made up of resistance device and capacitor element, control capacittance device and resistance device can change the response time of electrostatic discharge testing circuit to electrostatic discharge event, therefore, and the detection sensitivity of adjustable described electrostatic discharge testing circuit.
Further, the detection signal that electrostatic discharge treatment system provided by the invention can export according to multiple electrostatic discharge testing circuit is comprehensively analyzed, and processes after analysis to electrostatic discharge event, improves the stability of chip system.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of existing a kind of electrostatic discharge testing circuit;
Fig. 2 is the electrical block diagram of the electrostatic discharge testing circuit of embodiment of the present invention;
Fig. 3 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 1;
Fig. 4 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 2;
Fig. 5 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 3;
Fig. 6 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 4;
Fig. 7 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 5;
Fig. 8 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 6;
Fig. 9 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 7;
Figure 10 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 8;
Figure 11 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 9;
Figure 12 is the electrical block diagram of the electrostatic discharge treatment system of the embodiment of the present invention.
Embodiment
Just as described in the background art, the electrostatic potential that electrostatic discharge testing circuit shown in Fig. 1 is produced by static discharge by all diode breakdown in diode group 11 to produce the detection signal with high level, therefore, it is possible to the electrostatic potential detected must be greater than the voltage breakdown sum of all diodes.
Such as, the Diode series that described diode group 11 adopts voltage breakdown identical, the magnitude of voltage of the voltage breakdown of every diode is VBR, if the diode of series connection is one, the electrostatic potential that magnitude of voltage is greater than VBR can be detected, and the electrostatic potential that magnitude of voltage is less than or equal to VBR just can not be detected; If the diode of series connection is two, the electrostatic potential that magnitude of voltage is greater than 2VBR can be detected, and the electrostatic potential that magnitude of voltage is less than or equal to 2VBR just can not be detected.Therefore, existing electrostatic discharge testing circuit can not detect less electrostatic potential, and sensing range is narrower.
Technical solution of the present invention provides the wide testing circuit of a kind of sensing range.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
With reference to the electrical block diagram of the electrostatic discharge testing circuit of the technical solution of the present invention shown in figure 2, described electrostatic discharge testing circuit comprises sampling unit 21, amplifier unit 22 and voltage regulation unit 23.
Described sampling unit 21 is coupled between the first power lead Vdd and second source line Vss, and the voltage being suitable for sampling on described first power lead Vdd and second source line Vss is to export control voltage Vi.The voltage that the voltage that described first power lead Vdd provides provides higher than described second source line Vss, usually, described first power lead Vdd provides the supply voltage of high level, and described second source line Vss provides ground voltage.
Described amplifier unit 22 couples described sampling unit 21 and described voltage regulation unit 23, be suitable for receiving described control voltage Vi, according to the threshold voltage output detections signal of described control voltage Vi and described amplifier unit 22, export the first detection signal when described control voltage Vi is greater than the threshold voltage of described amplifier unit 22 by output terminal out, export the second detection signal when described control voltage Vi is less than the threshold voltage of described amplifier unit 22 by output terminal out.
Described voltage regulation unit 23 is suitable for the threshold voltage regulating described amplifier unit 22.
For understanding structure and the principle of work of electrostatic discharge testing circuit provided by the invention better, be described in detail below in conjunction with accompanying drawing and specific embodiment.
Embodiment 1
Fig. 3 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 1.
With reference to figure 3, sampling unit 21a comprises the first impedor R1 and the first capacitive reactive element C1.The other end that one end of described first impedor R1 connects described first power lead Vdd, described first impedor R1 connects one end of described first capacitive reactive element C1 and exports the output terminal of described control voltage Vi as described sampling unit 21a.The other end of described first capacitive reactive element C1 connects described second source line Vss.
Described first impedor R1 can be made up of the various device containing resistance, comprises polysilicon resistance, active area resistance, trap resistance or MOS channel resistance etc.Described first capacitive reactive element C1 can be made up of capacitor element, comprises polycrystalline silicon-insulator-polycrystalline silicon capacitance, metal-insulator-polysilicon capacitance, metal-insulator-metal capacitor, metal-oxide-metal capacitor or mos capacitance etc.
Described amplifier unit 22 comprises grid the first connected PMOS P1 and the first NMOS tube N1.The grid of described first PMOS P1 is suitable for receiving described control voltage Vi, and the drain electrode of described first PMOS P1 is connected with the drain electrode of described first NMOS tube N1 and as the output terminal out of described amplifier unit 22 output detections signal.
In the present embodiment, the CMOS phase inverter that is made up of the first PMOS P1 and the first NMOS tube N1 of described amplifier unit 22.The high level signal corresponding digital signals " 1 " that described CMOS phase inverter exports, the low level signal corresponding digital signals " 0 " that described CMOS phase inverter exports.
When described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, described first PMOS P1 cut-off, described first NMOS tube N1 conducting, the first detection signal of output is low level signal; When described control voltage Vi is reduced to the threshold voltage equaling described amplifier unit 22, the signal that described CMOS phase inverter exports is high level signal by low level signal saltus step; When described control voltage Vi is less than the threshold voltage of described amplifier unit 22, described first PMOS P1 conducting, described first NMOS tube N1 cut-off, the second detection signal of output is high level signal; When described control voltage Vi is increased to the threshold voltage equaling described amplifier unit 22, the signal that described CMOS phase inverter exports is low level signal by high level signal saltus step.
The critical voltage when threshold voltage of described amplifier unit 22 is the detection signal saltus step controlling the output of described amplifier unit 22.Described critical voltage is relevant with circuit structure to the device included by amplifier unit 22.In the present embodiment, the threshold voltage of described amplifier unit 22 is relevant to the source voltage of the size of the size of described first PMOS P1, described first NMOS tube N1, the source voltage of described first PMOS P1 and described first NMOS tube N1.
Described voltage regulation unit is by regulating the source voltage of described first PMOS P1 and/or the source voltage of described first NMOS tube N1 to regulate the threshold voltage of described amplifier unit 22.In the present embodiment, described voltage regulation unit comprises the PMOS group 23a be made up of at least one PMOS.First PMOS P31 in described PMOS group 23a, n-th PMOS P3n become cascaded structure, n be series connection PMOS quantity.
The drain electrode of each PMOS is connected with the source electrode of another PMOS of series connection, and the grid of each PMOS is connected with respective drain electrode.The source electrode of described first PMOS P31 is as the first end of described PMOS group 23a, and the drain electrode of described n-th PMOS P3n is as second end of described PMOS group 23a.
The first end of described PMOS group 23a is connected with described first power lead Vdd, and second end of described PMOS group 23a connects the source electrode of described first PMOS P1.In the present embodiment, the first end of described PMOS group 23a is suitable for input first supply voltage, and described first supply voltage is the voltage that described first power lead Vdd provides.In other embodiments, the first end of described PMOS group 23a also can connect other power supplies, and the present invention is not construed as limiting this.
Because described amplifier unit 22 is by described first supply voltage of described voltage regulation unit input, described voltage regulation unit carries out dividing potential drop, therefore, the source voltage of the first PMOS P1 in described amplifier unit 22 reduces, the ducting capacity of described first PMOS P1 weakens, thus the threshold voltage of described amplifier unit 22 is reduced.
The threshold voltage of to be n × Vthp, Vthp the be each series connection PMOS of the pressure drop on described PMOS group 23a.The quantity of PMOS of connecting in described PMOS group 23a is more, the dividing potential drop effect of described PMOS group 23a is stronger, the source voltage of the first PMOS P1 in described amplifier unit 22 is lower, therefore, the ducting capacity of described first PMOS P1 is more weak, thus makes the threshold voltage of described amplifier unit 22 lower.
Below in conjunction with circuit shown in Fig. 3 and the concrete course of work thereof, advantage of the present invention is described further.
When described first power lead Vdd there is not the electrostatic potential that static discharge produces, described control voltage Vi is pulled to noble potential by described first impedor R1, therefore, described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, described first NMOS tube N1 conducting, described first PMOS P1 cut-off, the first detection signal of described amplifier unit 22 output low level.
When described first power lead Vdd there is the electrostatic potential that static discharge produces, described electrostatic potential is pulse voltage, to described first capacitive reactive element C1 charging, described control voltage Vi is pulled to electronegative potential by described first capacitive reactive element C1, therefore, described control voltage Vi is less than the threshold voltage of described amplifier unit 22, described first NMOS tube N1 cut-off, described first PMOS P1 conducting, described amplifier unit 22 exports the second detection signal of high level.
Because described PMOS group 23a makes the threshold voltage of described amplifier unit 22 reduce, therefore, when described first power lead Vdd occurring the less electrostatic potential that static discharge produces, described electrostatic potential also can be detected.
It should be noted that, in the present embodiment, can also regulate the detection sensitivity of described electrostatic discharge testing circuit, the detection sensitivity of electrostatic discharge testing circuit refers to from producing the time of electrostatic potential to the detection signal of the corresponding described electrostatic potential of described electrostatic discharge testing circuit output.Described sampling unit 21a is made up of described first impedor R1 and described first capacitive reactive element C1, owing to needing the time to capacitive reactive element discharge and recharge, therefore, regulate the size of described first impedor R1 and described first capacitive reactive element C1, described electrostatic discharge testing circuit can be regulated the response time of electrostatic potential, namely can regulate the detection sensitivity of described electrostatic discharge testing circuit.
Embodiment 2
Fig. 4 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 2.With reference to figure 4, embodiment 2 is with the difference of embodiment 1: sampling unit 21b comprises described first impedor R1 and described first capacitive reactive element C1, also comprise the second impedor R2, described first capacitive reactive element C1 is connected with described first impedor R1 by described second impedor R2, and the link of described first impedor R1 and described second impedor R2 exports the output terminal of described control voltage Vi as described sampling unit 21b.
Described second impedor R2 can be made up of the various device containing resistance, comprises polysilicon resistance, active area resistance, trap resistance or MOS channel resistance etc.
In the present embodiment, described sampling unit 21b comprises described second impedor R2, described second impedor R2 can change the charging current to described first capacitive reactive element C1, regulates the sensitivity of described electrostatic discharge testing circuit further, makes adjustment of sensitivity scope wider.
Embodiment 3
Fig. 5 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 3.With reference to figure 5, embodiment 3 is with the difference of embodiment 1: described first impedor R1 and described first capacitive reactive element C1 transposition, namely one end of described first impedor R1 connects described second source line Vss, the other end of described first impedor R1 connects one end of described first capacitive reactive element C1 and exports the output terminal of described control voltage Vi as sampling unit 21c, and the other end of described first capacitive reactive element C1 connects described first power lead Vdd.
In the present embodiment, when described first power lead Vdd there is not the electrostatic potential that static discharge produces, described control voltage Vi is pulled to electronegative potential by described first impedor R1, therefore, described control voltage Vi is less than the threshold voltage of described amplifier unit 22, described first PMOS P1 conducting, described first NMOS tube N1 cut-off, the second detection signal of the high level that described amplifier unit 22 exports.
When described first power lead Vdd there is the electrostatic potential that static discharge produces, described electrostatic potential is pulse voltage, to described first capacitive reactive element C1 charging, described control voltage Vi is pulled to noble potential by described first capacitive reactive element C1, therefore, described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, described first NMOS tube N1 conducting, described first PMOS P1 cut-off, low level first detection signal that described amplifier unit 22 exports.
Because described PMOS group 23a makes the threshold voltage of described amplifier unit 22 reduce, therefore, when described first power lead Vdd occurring the less electrostatic potential that static discharge produces, described electrostatic potential also can be detected.
Embodiment 4
Fig. 6 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 4.With reference to figure 6, embodiment 4 is with the difference of embodiment 3: sampling unit 21d comprises described first impedor R1 and described second capacitive reactive element C1, also comprise the second impedor R2, described first capacitive reactive element C1 is connected with described first impedor R1 by described second impedor R2, and the link of described first impedor R1 and described second impedor R2 exports the output terminal of described control voltage Vi as described sampling unit 21d.
Described second impedor R2 can be made up of the various device containing resistance, comprises polysilicon resistance, active area resistance, trap resistance or MOS channel resistance etc.
Described sampling unit 21d comprises described second impedor R2, and described second impedor R2 can change the charging current to described first capacitive reactive element C1, regulates the sensitivity of described electrostatic discharge testing circuit further, makes adjustment of sensitivity scope wider.
Embodiment 5
Fig. 7 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 5.With reference to figure 7, embodiment 5 is with the difference of embodiment 1: sampling unit 21e comprises the 3rd impedor R3, 4th impedor R4 and the transistor group 24a be made up of at least one transistor, one end of described 3rd impedor R3 is suitable for connecting described first power lead Vdd, the other end of described 3rd impedor R3 connects one end of described 4th impedor R4 and exports the output terminal of described control voltage Vi as described sampling unit 21e, the other end of described 4th impedor R4 connects the first end of described transistor group 24a, second end of described transistor group 24a is suitable for connecting described second source line Vss.
In the present embodiment, the transistor in described transistor group 24a is NMOS tube.First NMOS tube N41 in described transistor group 24a, m NMOS tube N4m becomes cascaded structure, m is the quantity of series connection NMOS tube.The drain electrode of each NMOS tube is connected with the source electrode of another NMOS tube of series connection, and the grid of each NMOS tube is connected with respective drain electrode.The drain electrode of described first NMOS tube N41 is as the first end of described transistor group 24a, and the source electrode of described m NMOS tube N4m is as second end of described transistor group 24a.
In the present embodiment, NMOS tube in described transistor group 24a becomes diode to connect, when the voltage on described first power lead Vdd is lower than m × Vthn, and the NMOS tube cut-off in described transistor group 24a, wherein, Vthn is the threshold voltage of each NMOS tube in described transistor group 24a.
When described first power lead Vdd there is not the electrostatic potential that static discharge produces, NMOS tube cut-off in described transistor group 24a, described control voltage Vi is pulled to noble potential by described 3rd impedor R3, therefore, described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, described first PMOS P1 cut-off, described first NMOS tube N1 conducting, the first detection signal of described amplifier unit 22 output low level.
When described first power lead Vdd there is the electrostatic potential that static discharge produces, voltage on described first power lead Vdd raises, make the NMOS tube conducting in described transistor group 24a, described control voltage Vi is pulled to electronegative potential by described 4th impedor R4 and described transistor group 24a, therefore, described control voltage Vi is less than the threshold voltage of described amplifier unit 22, described first NMOS tube N1 cut-off, described first PMOS P1 conducting, described amplifier unit 22 exports the second detection signal of high level.
Embodiment 6
Fig. 8 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 6.With reference to figure 8, embodiment 6 is with the difference of embodiment 5: the transistor in the transistor group 24b in sampling unit 21f is PMOS, the first end of described transistor group 24b is suitable for connecting described first power lead Vdd, second end of described transistor group 24b connects one end of described 4th impedor R4, the other end of described 4th impedor R4 is connected with one end of described 3rd impedor R3 and exports the output terminal of described control voltage Vi as described sampling unit 21f, and the other end of described 3rd impedor R3 is suitable for connecting described second source line Vss.
First PMOS N41 in described transistor group 24b, m PMOS P4m becomes cascaded structure, m is the quantity of series connection PMOS.The drain electrode of each PMOS is connected with the source electrode of another PMOS of series connection, and the grid of each PMOS is connected with respective drain electrode.The source electrode of described first PMOS P41 is as the first end of described transistor group 24b, and the drain electrode of described m PMOS P4m is as second end of described transistor group 24b.
In the present embodiment, PMOS in described transistor group 24b becomes diode to connect, when the voltage on described first power lead Vdd is lower than m × Vthp, and the PMOS cut-off in described transistor group 24b, wherein, Vthp is the threshold voltage of each PMOS in described transistor group 24b.
When described first power lead Vdd there is not the electrostatic potential that static discharge produces, PMOS cut-off in described transistor group 24b, described control voltage Vi is pulled to electronegative potential by described 3rd impedor R3, therefore, described control voltage Vi is less than the threshold voltage of described amplifier unit 22, described first PMOS P1 conducting, described first NMOS tube N1 cut-off, described amplifier unit 22 exports the second detection signal of high level.
When described first power lead Vdd there is the electrostatic potential that static discharge produces, voltage on described first power lead Vdd raises, make the PMOS conducting in described transistor group 24b, described control voltage Vi is pulled to noble potential by described 4th impedor R4 and described transistor group 24b, therefore, described control voltage Vi is greater than the threshold voltage of described amplifier unit 22, described first NMOS tube N1 conducting, described first PMOS P1 cut-off, the first detection signal of described amplifier unit 22 output low level.
Embodiment 7
Fig. 9 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 7.With reference to figure 9, embodiment 7 is with the difference of embodiment 1: described voltage regulation unit comprises the NMOS tube group 23b be made up of at least one NMOS tube, the first end of described NMOS tube group 23b connects the source electrode of described first NMOS tube N1, and second end of described NMOS tube group 23b is suitable for input second source voltage.
First NMOS tube N31 in described NMOS tube group 23b, n-th NMOS tube N3n become cascaded structure, n be series connection NMOS tube quantity.The drain electrode of each NMOS tube is connected with the source electrode of another NMOS tube of series connection, and the grid of each NMOS tube is connected with respective drain electrode.The drain electrode of described first NMOS tube N31 is as the first end of described NMOS tube group 23b, and the source electrode of described n-th NMOS tube N3n is as second end of described NMOS tube group 23b.
In the present embodiment, second end of described NMOS tube group 23b is connected with described second source line Vss, and described second source voltage is the voltage that described second source line Vss provides.In other embodiments, second end of described NMOS tube group 23b also can connect other power supplies, and the present invention is not construed as limiting this.
Because described amplifier unit 22 inputs described second source voltage by described voltage regulation unit, described voltage regulation unit carries out dividing potential drop, therefore, the source voltage of the first NMOS tube N1 in described amplifier unit 22 raises, the ducting capacity of described first NMOS tube N1 weakens, thus the threshold voltage of described amplifier unit 22 is raised.
The threshold voltage of to be n × Vthn, Vthn the be each series connection NMOS tube of the pressure drop on described NMOS tube group 23b.The quantity of NMOS tube of connecting in described NMOS tube group 23b is more, the dividing potential drop effect of described NMOS tube group 23b is stronger, the source voltage of the first NMOS tube N1 in described amplifier unit 22 is higher, therefore, the ducting capacity of described first NMOS tube N1 is more weak, thus makes the threshold voltage of described amplifier unit 22 higher.
Because the threshold voltage of described amplifier unit 22 raises, the electrostatic potential that can detect raises, and can prevent the error detection because noise causes.
Embodiment 8
Figure 10 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 8.With reference to Figure 10, embodiment 8 is with the difference of embodiment 1: described voltage regulation unit comprises the PMOS group 23a be made up of at least one PMOS and the NMOS tube group 23b be made up of at least one NMOS tube, one end of described PMOS group 23a is suitable for input first supply voltage, and the other end of described PMOS group 23a connects the source electrode of described first PMOS P1; One end of described NMOS tube group 23b is suitable for receiving second source voltage, and the other end of described NMOS tube group 23b connects the source electrode of described NMOS tube N1; Described first supply voltage is higher than described second source voltage.
In the present embodiment, the particular circuit configurations of described PMOS group 23a can described PMOS group in reference example 1, the concrete structure of described NMOS tube group 23b can described NMOS tube group in reference example 7, and described sampling unit 21 with reference to previous embodiment, can not repeat them here.
Described PMOS group 23a can reduce the source voltage of described first PMOS P1, described NMOS tube group 23b can raise the source voltage of described first NMOS tube N1, regulated the threshold voltage of described amplifier unit 22 by described PMOS group 23a and described NMOS tube group 23b, the sensing range of described electrostatic discharge testing circuit can be regulated.
Embodiment 9
Figure 11 is the circuit diagram of the electrostatic discharge testing circuit of the embodiment of the present invention 9.With reference to Figure 11, described electrostatic discharge testing circuit comprises sampling unit 21, amplifier unit 22, voltage regulation unit 23, also comprises latch unit 25, and described latch unit 25 is suitable for described first detection signal or the second detection signal to latch rear output.The concrete structure of described sampling unit 21, amplifier unit 22 and voltage regulation unit 23 with reference to previous embodiment, can not repeat them here.
Described latch unit 25 can be RS latch, described RS latch can carry out shaping to described first detection signal and described second detection signal, described first detection signal is converted to digital signal " 0 ", described second detection signal is converted to digital signal " 1 ".
With reference to Figure 12, technical solution of the present invention additionally provides a kind of electrostatic discharge treatment system.Described electrostatic discharge treatment system comprises processing unit 122, discharge cell 123 and at least two electrostatic discharge testing circuits: electrostatic discharge testing circuit 1211 ..., electrostatic discharge testing circuit 121N, N be the quantity of described electrostatic discharge circuit.The structure of described electrostatic discharge testing circuit can be any one circuit structure shown in Fig. 3 ~ Figure 11.
The electrostatic potential that system level chip internal power cord is produced by static discharge is more much smaller than the electrostatic potential that static discharge position occurs.For the circuit that antistatic interference performance is strong, the electrostatic potential on power lead can not have an impact to its work, does not need to process electrostatic potential.And for the circuit to electrostatic interference sensitivity, less electrostatic potential also can cause it normally to work, need to process electrostatic potential.Therefore, can multiple electrostatic discharge testing circuit be set in chip, by judging that the detection signal of different electrostatic discharge testing circuit is to determine whether to need to process electrostatic potential.
It should be noted that, the sensing range of multiple electrostatic discharge testing circuit can be identical with detection sensitivity, is arranged on the diverse location in chip; The sensing range of multiple electrostatic discharge testing circuit and detection sensitivity also can be different, are arranged on the same position in chip; The sensing range of multiple electrostatic discharge testing circuit and detection sensitivity can also be different, are arranged on the diverse location in chip.
Because each electrostatic discharge testing circuit exports a detection signal, therefore, described at least two electrostatic discharge testing circuits correspondence exports at least two detection signals.Described processing unit 122 is suitable at least two detection signals described in reception, and the quantity of the first detection signal at least two detection signals received and the quantity of the second detection signal are compared, when the first detection signal quantity received is more than or equal to the quantity of the second detection signal, trigger the electrostatic potential that described discharge cell 123 is released on described first power lead Vdd and described second source line Vss.That is, at least two detection signals exported by least two electrostatic discharge testing circuits described in analyzing, the quantity of the first detection signal and the second detection signal, can determine whether to need to process electrostatic potential.
Described discharge cell 123 comprises discharge transistor, the first end of described discharge transistor is suitable for connecting described processing unit 122, second end of described discharge transistor is suitable for connecting described first power lead Vdd, and the 3rd end of described discharge transistor is suitable for connecting described second source line Vss.Described discharge transistor can be metal-oxide-semiconductor or triode.
The detection signal that electrostatic discharge treatment system provided by the invention can export according to multiple electrostatic discharge testing circuit is analyzed, and processes after analysis to electrostatic discharge event, prevents the error detection brought by noise, improves the stability of chip system.
In sum, electrostatic discharge testing circuit provided by the invention, by the threshold voltage of voltage regulation unit resonance-amplifier unit, the sensing range of electrostatic discharge testing circuit broadens, and, can catch change in voltage less on power lead, electrostatic discharge testing circuit of the present invention can be used in the detection of the less system level chip inside of electrostatic potential.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. an electrostatic discharge testing circuit, is characterized in that, comprising: sampling unit, amplifier unit and voltage regulation unit, wherein,
Described sampling unit is suitable for voltage on sampling first power lead and second source line to export control voltage, the voltage that the voltage that described first power lead provides provides higher than described second source line;
The detection signal that described amplifier unit is suitable for exporting when described control voltage is greater than the threshold voltage of described amplifier unit is the first detection signal, and the detection signal exported when described control voltage is less than the threshold voltage of described amplifier unit is the second detection signal;
Described voltage regulation unit is suitable for the threshold voltage regulating described amplifier unit;
Described sampling unit comprises the 3rd impedor, the 4th impedor and the transistor group that is made up of at least one transistor that are connected to and connect successively between described first power lead and described second source line; Transistor in described transistor group becomes cascaded structure, and the grid of each transistor is connected with respective drain electrode; Described 3rd impedor and described 4th impedor link export the output terminal of described control voltage as described sampling unit.
2. electrostatic discharge testing circuit according to claim 1, is characterized in that, described amplifier unit comprises the first connected PMOS of grid and the first NMOS tube; The grid of described first PMOS is suitable for receiving described control voltage, and the drain electrode of described first PMOS is connected with the drain electrode of described first NMOS tube and exports the output terminal of described detection signal as described amplifier unit.
3. electrostatic discharge testing circuit according to claim 2, it is characterized in that, described voltage regulation unit comprises the PMOS group be made up of at least one PMOS, PMOS in described PMOS group becomes cascaded structure, the grid of each PMOS is connected with respective drain electrode, one end of described PMOS group is suitable for input first supply voltage, and the other end of described PMOS group connects the source electrode of described first PMOS.
4. electrostatic discharge testing circuit according to claim 2, it is characterized in that, described voltage regulation unit comprises the NMOS tube group be made up of at least one NMOS tube, NMOS tube in described NMOS tube group becomes cascaded structure, the grid of each NMOS tube is connected with respective drain electrode, one end of described NMOS tube group is suitable for input second source voltage, and the other end of described NMOS tube group connects the source electrode of described first NMOS tube.
5. electrostatic discharge testing circuit according to claim 2, is characterized in that, described voltage regulation unit comprises the PMOS group be made up of at least one PMOS and the NMOS tube group be made up of at least one NMOS tube; PMOS in described PMOS group becomes cascaded structure, and the grid of each PMOS is connected with respective drain electrode, and one end of described PMOS group is suitable for input first supply voltage, and the other end of described PMOS group connects the source electrode of described first PMOS; NMOS tube in described NMOS tube group becomes cascaded structure, and the grid of each NMOS tube is connected with respective drain electrode, and one end of described NMOS tube group is suitable for receiving second source voltage, and the other end of described NMOS tube group connects the source electrode of described first NMOS tube; Described first supply voltage is higher than described second source voltage.
6. electrostatic discharge testing circuit according to claim 1, it is characterized in that, described 3rd impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance, and described 4th impedor is polysilicon resistance, active area resistance, trap resistance or MOS channel resistance.
7. electrostatic discharge testing circuit according to claim 1, is characterized in that, also comprises latch unit, is suitable for described first detection signal or the second detection signal to latch rear output.
8. an electrostatic discharge treatment system, it is characterized in that, comprise processing unit, discharge cell and the electrostatic discharge testing circuit described at least two any one of claim 1 to 7, the detection signal that described in described processing unit is suitable for receiving, at least two electrostatic discharge testing circuits export, and the electrostatic potential triggering that when the first detection signal quantity received is more than or equal to the quantity of the second detection signal described discharge cell releases on described first power lead and second source line.
9. electrostatic discharge treatment system according to claim 8, it is characterized in that, described discharge cell comprises discharge transistor, the first end of described discharge transistor is suitable for connecting described processing unit, second end of described discharge transistor is suitable for connecting described first power lead, and the 3rd end of described discharge transistor is suitable for connecting described second source line.
10. electrostatic discharge treatment system according to claim 9, is characterized in that, described discharge transistor is metal-oxide-semiconductor or triode.
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| TWI627809B (en) * | 2017-01-25 | 2018-06-21 | 瑞昱半導體股份有限公司 | Electrostatic discharge protection circuit |
| CN106707073A (en) * | 2017-03-08 | 2017-05-24 | 苏州天华超净科技股份有限公司 | Electrostatic discharging detection circuit and system |
| CN108631284B (en) * | 2017-03-21 | 2020-08-25 | 瑞昱半导体股份有限公司 | Electrostatic discharge protection circuit |
| US11081881B2 (en) * | 2017-12-20 | 2021-08-03 | Stmicroelectronics International N.V. | Full swing positive to negative MOSFET supply clamp for electrostatic discharge (ESD) protection |
| JP7089463B2 (en) * | 2018-12-11 | 2022-06-22 | ルネサスエレクトロニクス株式会社 | Semiconductor devices and semiconductor device systems |
| WO2022056901A1 (en) * | 2020-09-21 | 2022-03-24 | 京东方科技集团股份有限公司 | Display substrate and display device |
| KR20220129608A (en) | 2021-03-10 | 2022-09-23 | 창신 메모리 테크놀로지즈 아이엔씨 | Electrostatic protection circuits and semiconductor devices |
| CN115084125A (en) * | 2021-03-10 | 2022-09-20 | 长鑫存储技术有限公司 | Electrostatic protection circuit and semiconductor device |
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