CN105634454B

CN105634454B - A kind of electrification reset circuit reinforced suitable for aerospace with the single-particle of SRAM type FPGA

Info

Publication number: CN105634454B
Application number: CN201610108491.0A
Authority: CN
Inventors: 陈雷; 李学武; 王文锋; 赵元富; 孙华波; 倪劼; 李智; 张健
Original assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Current assignee: Beijing Microelectronic Technology Institute; Mxtronics Corp
Priority date: 2016-02-26
Filing date: 2016-02-26
Publication date: 2018-07-06
Anticipated expiration: 2036-02-26
Also published as: CN105634454A

Abstract

A kind of electrification reset circuit reinforced suitable for aerospace with the single-particle of SRAM type FPGA, it is internal identical to power on redundant module, fluffing check and redundancy output control module and three controllable output buffers comprising power supply VCC, three, fluffing check and redundancy output control module can detect that malfunctions powers on redundant module, and resetted redundant module is powered on, remove the accumulation of single particle effect；Fluffing check and redundancy output control module can control the output for powering on redundant module of controllable output buffer cut-out error, it is ensured that the output of electrification reset circuit is correct.This electrification reset circuit removes the error accumulation phenomenon as caused by Single event upset effecf, while module output is controlled, and eliminates influence of the single particle effect to output, realizes the ability of significant anti-single particle effect.

Description

A kind of electrification reset circuit reinforced suitable for aerospace with the single-particle of SRAM type FPGA

Technical field

The present invention relates to a kind of electrification reset circuits reinforced suitable for aerospace with the single-particle of SRAM type FPGA, belong to anti- Single particle effect reinforces integrated circuit fields.

Background technology

SRAM type fpga chip is starting one electrification reset process of needs.Electrification reset circuit starts in fpga chip When, a reset signal is provided, is always maintained at effective level, can be worked normally until supply voltage is raised to other circuits Degree after change reset signal, other circuits on bootrom power on and successfully keep stable state afterwards, make the normal work of chip Make.When existing electrification reset circuit is used for aerospace with SRAM type FPGA, serious integrity problem will be faced：It is disliked in space Electrification reset circuit will generate the single particle effects such as single-particle inversion (SEU) and single-ion transient state (SET) in bad environment.When powering on Single-particle inversion (SEU) occurs for reset circuit with that will generate the power-on reset signal of mistake during single-ion transient state (SET), causes Chip power-down, user function are lost, and the reliability of aerospace SRAM type FPGA are seriously affected, with the progress of technique, SRAM type Fpga chip continues to increase the sensibility of single particle effect, and higher requirement is proposed to the reliability of electrification reset circuit. Aerospace SRAM type FPGA Jing Guo Design of Reinforcement simultaneously, inside include a variety of storage units, these storage units are because of radioresistance The difference of demand employs different reinforcement measures, causes these storage units normal work required voltage different, during clearing Between it is different, existing electrification reset circuit is difficult to ensure that rational reseting pulse width, is reduced in particular with process, no The deviation of same type storage unit constantly increases, and requirements at the higher level are improved to the correctness of reseting pulse width.

Invention content

Present invention solves the technical problem that it is：It overcomes the shortage of prior art, provides a kind of suitable for aerospace SRAM type The electrification reset circuit that the single-particle of FPGA is reinforced, by fluffing check and redundancy output control module generation single particle effect Error powers on redundant module output shutdown, and final electrification reset output is made to keep correct；Using with the delay for resetting input Deburring circuit, the transient wave generated by power-supply fluctuation and single particle effect of removal level monitoring module, while on this During electric redundant module error, delay deburring circuit is answered by the output of fluffing check and redundancy output control module Position；Using with the digital assistant time delay module for resetting input, when this powers on redundant module error, by fluffing check and superfluous The output of remaining output control module carries out reset clearing to digital assistant time delay module, removes the accumulation effect of single-particle inversion Should, correct status is returned to, effect and anti-single particle transient effect ability are overturn so as to fulfill anti-single particle；It is deposited by inside The monitoring of storage unit state monitoring module carries out the reinforcing storage unit in FPGA minimum time needed for primary complete read-write operation, It ensure that reseting pulse width can meet FPGA to all proper resets for reinforcing storage unit.

The technical solution that the present invention solves is：It is replied by cable in a kind of single-particle reinforcing suitable for aerospace SRAM type FPGA Position circuit identical powers on redundant module, fluffing check and redundancy output control module and three can including power supply VCC, three Control output buffer；Three identical to power on redundant module, respectively first power on redundant module, second power on redundant module, Third powers on redundant module；Three controllable output buffers are respectively the first controllable output buffer, the second controllable output buffering The controllable output buffer of device, third；

Redundant module each is powered on, including level monitoring module, delay deburring circuit, internal storage unit status monitoring Module, digital assistant time delay module；

Power supply gives level monitoring module for power supply, and level monitoring module detects the voltage value of power supply in real time, when the voltage of power supply When value is more than or equal to the upper threshold voltage Vthr set, level monitoring module exports a high level signal and send to delay deburring Circuit, the high level signal terminate reset signal, when the voltage value of power supply is less than the upper threshold voltage Vthr set, level Monitoring modular exports a low level signal and send to delay deburring circuit；

Be delayed deburring circuit, receives high level signal or low level signal that level monitoring module is sent, judges to malfunction When detection and redundancy output control module feedback are high level signal, while when the high level letter received from level monitoring module Number or low level signal single pulse width be less than or equal to setting pulse width when, using the single pulse as burr filter It removes, the high level signal or the low level signal of smooth-going smoothed out is sent to internal storage unit state monitoring module；Judge When false retrieval is surveyed and redundancy output control module feedback is low level signal, when fluffing check and redundancy output control module are fed back Low level signal in pulse be less than or equal to setting pulse width when, filter out, put down using the single pulse as burr Suitable low level signal is sent to internal storage unit state monitoring module；

Internal storage unit state monitoring module, including multiple storage units；

Internal storage unit state monitoring module, when the low level signal of smooth-going that reception delay deburring circuit is sent, Multiple storage units in internal storage unit state monitoring module are locked, that is, stop that data are written to the storage unit, together When to digital assistant time delay module export high level signal；Internal storage unit state monitoring module, when reception delay deburring The high level signal for the smooth-going that circuit is sent, internally multiple storage units write-in in state of memory cells monitoring modular is with depositing The opposite value of the value that is stored in storage unit, then locks multiple storage units, that is, stops that data are written to the storage unit, together Shi Houxiang digital assistants time delay module exports low level signal；

Digital assistant time delay module includes multiple registers and an oscillator；

Digital assistant time delay module receives high level signal or low level that internal storage unit state monitoring module is sent Signal, when receiving high level signal from internal storage unit state monitoring module and fluffing check and redundancy output control mould When being fed back to high level of block, multiple registers in digital assistant time delay module are in the lock state, i.e., register memory stores up Numerical value it is constant, export low level signal, i.e., the output of digital assistant time delay module be low level signal；

When receiving high level signal from internal storage unit state monitoring module and fluffing check and redundancy output control Molding block when being fed back to low level or when receiving low level signal from internal storage unit state monitoring module and error Detection and redundancy output control module when being fed back to high level or when be received from internal storage unit state monitoring module it is low During level signal and fluffing check and when being fed back to low level of redundancy output control module, oscillator start oscillation output clock Signal vibrates late register and counts once, after register is posted completely, exports high level, i.e. digital assistant time delay module each time Output be high level signal；

The output for powering on redundant module by first be denoted as POR_Good1 signals, second power on redundant module POR_Good2 letter Number, third power on redundant module POR_Good3 signals；The output for powering on redundant module by first is denoted as POR_Good1 signals, Two power on redundant module POR_Good2 signals, third powers on redundant module POR_Good3 signals and send to fluffing check and redundancy Output control module；The output for powering on redundant module by first is denoted as POR_Good1 signals and send to the first controllable output buffer； The output for powering on redundant module by second is denoted as POR_Good2 signals and send to the second controllable output buffer；Third is powered on superfluous The output of complementary modul block is denoted as POR_Good3 signals and send to the controllable output buffer of third；

Input that there are three fluffing checks and redundancy output control module and three outputs, three outputs respectively OUT1, OUT2 and OUT3, OUT1 output feed back to first and power on the delay deburring circuit of redundant module, digital assistant time delay module simultaneously It send to the first controllable output buffer, OUT2 outputs feed back to second, and to power on the delay deburring circuit of redundant module, number auxiliary It helps time delay module and send to the second controllable output buffer, OUT3 outputs feed back to the delay deburring that third powers on redundant module Circuit, digital assistant time delay module are simultaneously sent to the controllable output buffer of third；

Three inputs of fluffing check and redundancy output control module are respectively by POR_Good1 signals, the POR_ of reception Good2 signals, POR_Good3 signals are compared, if POR_Good1 signals, POR_Good2 signals, POR_Good3 signals are equal Identical, then three outputs OUT1, OUT2 and OUT3 of fluffing check and redundancy output control module are high level；If POR_ Good1 signals are different from POR_Good2 signals and POR_Good3 signals, then it is high electric that OUT1, which is low level, OUT2 and OUT3, It is flat；If POR_Good2 signals are different from POR_Good1 signals and POR_Good3 signals, OUT2 be low level, OUT1 and OUT3 is high level；If POR_Good3 signals are different from POR_Good1 signals and POR_Good2 signals, OUT3 is low electricity Flat, OUT1 and OUT2 are high level；

It is height in the output signal for receiving fluffing check and redundancy output control module when the first controllable output buffer During level, exported after first being powered on the output POR_Good1 signal inversions of redundant module；When the first controllable output buffer, When the output signal for receiving fluffing check and redundancy output control module is low level, the first controllable output buffer is not defeated Go out signal；

It is height in the output signal for receiving fluffing check and redundancy output control module when the second controllable output buffer During level, exported after second being powered on the output POR_Good2 signal inversions of redundant module；When the second controllable output buffer, When the output signal for receiving fluffing check and redundancy output control module is low level, the second controllable output buffer is not defeated Go out signal；

It is height in the output signal for receiving fluffing check and redundancy output control module when the controllable output buffer of third During level, exported after third to be powered on to the output POR_Good3 signal inversions of redundant module；When the controllable output buffer of third, When the output signal for receiving fluffing check and redundancy output control module is low level, the controllable output buffer of third is not defeated Go out signal.

The level monitoring module includes：PMOS tube M2, PMOS tube M3, PMOS tube M5, PMOS tube M5, NMOS tube M1, NMOS tube M4, NMOS tube M7, capacitance C1, capacitance C2, phase inverter；

The grounded-grid of PMOS tube M2, the source electrode connection power supply VCC of PMOS tube M2, the drain electrode of PMOS tube M2 connect simultaneously The grid of NMOS tube M1 and one end of capacitance of drain C1, the grid of PMOS tube M3；The source electrode ground connection of NMOS tube M1；

The source electrode connection of grid connection the power supply VCC, PMOS tube M3 of another termination power VCC of capacitance C1, NMOS tube M4 The drain electrode of the drain electrode connection NMOS tube M4 of power supply VCC, PMOS tube M3, one end of capacitance C2, the drain electrode of PMOS tube M5, PMOS tube M6 Grid, NMOS tube M7 grid；The source electrode ground connection of NMOS tube M4；The other end ground connection of capacitance C2；The source electrode of PMOS tube M5 connects The drain electrode of the grid connection PMOS tube M6 of power supply VCC, PMOS tube M5 and the drain electrode of NMOS tube M7, the input terminal of phase inverter；PMOS The source electrode connection power supply VCC of pipe M6；The source electrode ground connection of NMOS tube M7；The output terminal VCC_Good of phase inverter is as level monitoring mould The output of block.

The delay deburring circuit includes：With door AND31, phase inverter INV31, phase inverter INV32, phase inverter INV33, Phase inverter INV34, capacitance C31, capacitance C32, capacitance C33 and NAND gate NAND31；

The output VCC_Good of level monitoring module is connect for VCC_Good with an input terminal of door AND31, another Output of the input terminal for ER_RST connection fluffing checks and redundancy output control module, wherein first powers on the delay of redundant module Deburring circuit connects the output OUT1 of fluffing check and redundancy output control module, second powers on the delay unhairing of redundant module The thorn circuit connection fluffing check and output OUT2 of redundancy output control module is connected, third powers on the delay unhairing of redundant module Pierce the output OUT3 of circuit connection fluffing check and redundancy output control module；Phase inverter is connect with the output terminal of door AND31 The input terminal of INV31, while connect an input terminal of NAND gate NAND31 and one end of capacitance C31；The other end of capacitance C31 Connect power supply VCC；The input of connection phase inverter INV32 while one end of the output terminal connection capacitance C32 of phase inverter INV31 End；The other end ground connection of capacitance C32；The input terminal of the output terminal connection phase inverter INV33 of phase inverter INV32；Phase inverter INV33 Output terminal connection phase inverter INV34 input terminal；Connect while one end of the output terminal connection capacitance C33 of phase inverter INV34 Connect another input terminal of NAND gate NAND31；The other end of capacitance C33 is connected to power supply VCC；The output of NAND gate NAND31 Hold outputs of the Power_Good as delay deburring circuit.

The internal storage unit state monitoring module includes：Phase inverter INV41, phase inverter INV42 ..., phase inverter INV4n, storage unit SRAM41, storage unit SRAM42 ..., storage unit SRAM4n, NMOS tube M41, NMOS tube M42 ..., NMOS tube M4n or door OR4n；

The input terminal of phase inverter INV41 is connected to the output terminal Power_Good of delay deburring circuit, is connected to simultaneously The input terminal of phase inverter INV42, the input terminal of phase inverter INV4n, the R input of storage unit SRAM41, storage unit The R input of SRAM42, the R input of storage unit SRAM4n, the grid of NMOS tube M41, NMOS tube M42 grid, NMOS The grid of pipe M4n；The output terminal of phase inverter INV41 is connected to the RN input terminals of storage unit SRAM41；Phase inverter INV42's is defeated Outlet is connected to the RN input terminals of storage unit SRAM42；The output terminal of phase inverter INV4n is connected to storage unit SRAM4n's RN input terminals；The Z output terminals of storage unit SRAM41 are connected to or the first input end of door OR4n；The ZN of storage unit SRAM41 Output terminal is connected to the drain electrode of NMOS tube M41；The Z output terminals of storage unit SRAM42 are connected to or the second input of door OR4n End；The ZN output terminals of storage unit SRAM42 are connected to the drain electrode of NMOS tube M42；The Z output terminals connection of storage unit SRAM4n It arrives or the n-th input terminal of door OR4n；The ZN output terminals of storage unit SRAM4n are connected to the drain electrode of NMOS tube M4n；NMOS tube M41 Source electrode ground connection；The source electrode ground connection of NMOS tube M42；The source electrode ground connection of NMOS tube M4n；Or the POR_Latch output terminals of door OR4n The WL input terminals of the WL of storage unit SRAM41, the WL input terminals of storage unit SRAM42, storage unit SRAM4n are connected to, together The output of Shi Zuowei internal storage unit state monitoring modules.

The digital assistant time delay module includes：With door AND51, oscillator OSC, register FF51, register FF52, post Storage FF53, register FF54, register FF55, register FF56, register FF57, register FF58, register FF59；

The output of fluffing check and redundancy output control module is connect for ER_RST with an input terminal of door AND51, In first power on the delay deburring circuit connection fluffing check of redundant module and the output OUT1 of redundancy output control module, the The two output OUT2 for powering on the delay deburring circuits connection fluffing check of redundant module and redundancy output control module are connected, the Three power on the delay deburring circuit connection fluffing check of redundant module and the output OUT3 of redundancy output control module；With door The R input of the output terminal connection register registers FF51 of AND51, while the control signal of connection oscillator OSC；Deposit The R input of device FF52 is POR_Latch, receives the output POR_Latch of internal storage unit state monitoring module, connects simultaneously It is defeated to meet the R input of register FF53, the R input of register FF54, the R input of register FF55, the R of register FF56 Enter end, the R input of register FF57, the R input of register FF58, register FF59 R input；Oscillator OSC's Output terminal is connected to the input end of clock of register FF51；The D inputs of the QN output terminals connection register FF51 of register FF51 End；The input end of clock of the Q output connection register FF52 of register FF51；The QN output terminals connection deposit of register FF52 The D input terminals of device FF52；The input end of clock of the Q output connection register FF53 of register FF51；The QN of register FF53 The D input terminals of output terminal connection register FF53；The input end of clock of the Q output connection register FF54 of register FF53； The D input terminals of the QN output terminals connection register FF54 of register FF54；The Q output connection register FF55 of register FF54 Input end of clock；The D input terminals of the QN output terminals connection register FF55 of register FF55；The Q output of register FF55 Connect the input end of clock of register FF56；The D input terminals of the QN output terminals connection register FF56 of register FF56；Register The input end of clock of the Q output connection register FF57 of FF56；The D of the QN output terminals connection register FF57 of register FF57 Input terminal；The input end of clock of the Q output connection register FF58 of register FF57；The QN output terminals connection of register FF58 The D input terminals of register FF58；The input end of clock of the Q output connection register FF59 of register FF58；Register FF59 D input terminals be connected to power supply VCC；While the Q output of register FF59 is connected to another input terminal with door AND51 Output POR_Good as digital assistant time delay module simultaneously.

The fluffing check and redundancy output control module include：XOR gate XOR61, XOR gate XOR62, XOR gate XOR63, NAND gate NAND61, NAND gate NAND62, NAND gate NAND63；

An input terminal POR_Good1 connection first of XOR gate XOR61 powers on the digital assistant delay mould of redundant module The output of block, while connect an input terminal of XOR gate XOR62；Another input terminal POR_Good2 of XOR gate XOR62 connects The output of the second digital assistant time delay module for powering on redundant module is connect, while connects an input terminal of XOR gate XOR63；It is different Or another input terminal POR_Good3 connections third of door XOR63 powers on the output of the digital assistant time delay module of redundant module, Another input terminal of XOR gate XOR61 is connected simultaneously；One of the output terminal connection NAND gate NAND61 of XOR gate XOR61 is defeated Enter to connect an input terminal of NAND gate NAND63 while end；The output terminal connection NAND gate NAND62's of XOR gate XOR62 Another input terminal of NAND gate NAND61 is connected while one input terminal；The output terminal connection NAND gate of XOR gate XOR63 Another input terminal of NAND gate NAND62 is connected while another input terminal of NAND63；The output terminal of NAND gate NAND61 As fluffing check and the output terminal OUT1 of redundancy output control module；The output terminal of NAND gate NAND62 as fluffing check and The output terminal OUT2 of redundancy output control module；The output terminal of NAND gate NAND63 is as fluffing check and redundancy output control mould The output terminal OUT3 of block.

NMOS tube M1 is large-size device in the level monitoring module, which is 10；PMOS tube M2 is down than pipe, is somebody's turn to do wider than the tube long than being 1/10；NMOS tube M1 breadth length ratios are 100 times of PMOS tube M2 breadth length ratios；PMOS tube For M3 large-size devices, which is 10；NMOS tube M4 is down than pipe, is somebody's turn to do wider than the tube long than being 1/20； The breadth length ratio of PMOS tube M3 is 200 times of NMOS tube M4 breadth length ratios.

The advantages of the present invention over the prior art are that：

(1) output of the invention that using fluffing check and redundancy output control module three are powered on redundant module is examined It surveys, the redundant module output that powers on that generation single particle effect causes output to malfunction is closed, is ensureing final electrification reset output just Really, while the sub-circuit is reset and resetted, be returned to correct status, remove the accumulation of single-particle inversion, so as to fulfill anti- Single event upset effecf and anti-single particle transient effect ability.

(2) present invention realizes level monitoring using 4 PMOS tube, 3 NMOS tubes and two capacitances, with traditional level Monitoring is compared, and the delay unit that the present invention uses is less, makes entire area smaller.

(3) using the delay deburring circuit with the RESET input originally powering on redundant module simple grain occurs for the present invention During sub- effect, the output of fluffing check and redundancy output control module can be conducted to internal storage unit status monitoring mould Block.

(4) internal storage unit state monitoring module ensures that level meets the needs of a variety of storage units, ensures a variety of deposit Storage unit can be with proper reset.

(5) using the digital assistant time delay module with the RESET input originally powering on redundant module list occurs for the present invention During particle effect, can digital assistant time delay module be resetted by the output of fluffing check and redundancy output control module, removed The influence that the single-particle inversion generated generates, avoids its accumulation.

(6) fluffing check of the present invention and redundancy output control module can detect that three by three XOR gates and three with door Arbitrary mistake all the way in road, and pass through output and cut off the output on the road and the road is resetted.

(7) PMOS tube M2 is wider than the tube long than being 1/10 in level monitoring module of the present invention, and NMOS tube M4 is Than pipe, its breadth length ratio is 1/20, makes the sub-threshold region of PMOS tube M1 and NMOS tube M4 electric leakage very little, reduces entire module Power consumption；NMOS tube M1 breadth length ratios are 100 times of PMOS tube M2, make to be more than the unlatching threshold value and PMOS tube of NMOS tube as power supply VCC Unlatching threshold value when, node NOD1 voltages are close to the unlatching threshold value of NMOS tube；The breadth length ratio of PMOS tube M3 is NMOS tube M4 wide 200 times of long ratio, when making power supply VCC equal to the sum of the unlatching threshold value of NMOS tube and the unlatching threshold value of PMOS tube, node NOD2 electricity Pressure can be drawn high by M3 to the voltage value of power supply VCC with moment.

Description of the drawings

Fig. 1 is the electrification reset circuit entire block diagram of the present invention；

Fig. 2 is the level monitoring module circuit diagram of the present invention；

Fig. 3 is the delay deburring circuit diagram of the present invention；

The internal storage unit state monitoring module circuit diagram of Fig. 4 present invention；

The digital assistant time delay module circuit diagram of Fig. 5 present invention；

The fluffing check of Fig. 6 present invention and redundancy output control module circuit diagram；

The single-particle experimental result of the electrification reset circuit of Fig. 7 present invention is real with the single-particle of original electrification reset circuit Test the comparison diagram of result.

Specific embodiment

The present invention basic ideas be：A kind of electrification reset electricity reinforced suitable for aerospace with the single-particle of SRAM type FPGA Road, it is internal identical to power on redundant module, fluffing check and redundancy output control module and three comprising power supply VCC, three Controllable output buffer, fluffing check and redundancy output control module can detect that malfunctions powers on redundant module, and upper Electric redundant module is resetted, and removes the accumulation of single particle effect；Fluffing check and redundancy output control module can control can Control the output for powering on redundant module of output buffer cut-out error, it is ensured that the output of electrification reset circuit is correct.It is replied by cable on this Position circuit removes the error accumulation phenomenon as caused by Single event upset effecf, while module output is controlled, and eliminates single The ability of significant anti-single particle effect is realized in influence of the particle effect to output.

The present invention is described in further detail in the following with reference to the drawings and specific embodiments.

As shown in Figure 1, the present invention proposes a kind of anti-single particle reinforcing electrification reset suitable for aerospace SRAM type FPGA Circuit, structure as shown in Fig. 2, it is characterized by comprising：It identical power on redundant module including power supply VCC, three, go out false retrieval Survey and redundancy output control module and three controllable output buffers；Three identical to power on redundant module, on respectively first Electric redundant module, second power on redundant module, third powers on redundant module；Three controllable output buffers are respectively first controllable Output buffer, the second controllable output buffer, the controllable output buffer of third；

The output that the present invention powers on three using fluffing check and redundancy output control module redundant module is detected. When Space Particle hits electrification reset circuit, if Space Particle impinges upon the level monitoring module that some powers on redundant module On, the output of level detection module will generate a current impulse, when this current impulse is transmitted to delay deburring circuit, this A current impulse will be delayed by deburring circuit and be removed as burr, will not continue to be transmitted to next stage；When Space Particle is hit In the storage unit or register on internal state of memory cells monitoring modular or in digital assistant time delay module, all may These storage units or register are overturn, redundant module is finally powered on and generates a wrong output, fluffing check and superfluous This can be powered on redundant module and detected by remaining output control module, then by the way that generation single particle effect is caused to export out The wrong redundant module output that powers on is closed, and is ensured that final electrification reset output is correct, while the sub-circuit is reset and is resetted, is made it Correct status is returned to, removes the accumulation of single-particle inversion, effect and anti-single particle transient state effect are overturn so as to fulfill anti-single particle It should be able to power.

Level monitoring module of the present invention as shown in Fig. 2, including：PMOS tube M2, PMOS tube M3, PMOS tube M5, PMOS tube M6, NMOS tube M1, NMOS tube M4, NMOS tube M7, capacitance C1, capacitance C2, phase inverter；The grounded-grid of PMOS tube M2, The drain electrode of source electrode connection the power supply VCC, PMOS tube M2 of PMOS tube M2 connect the grid of NMOS tube M1 and capacitance of drain C1 simultaneously One end, the grid of PMOS tube M3；The source electrode ground connection of NMOS tube M1；Another termination power VCC of capacitance C1, the grid of NMOS tube M4 Connect power supply VCC, the drain electrode of the drain electrode connection NMOS tube M4 of source electrode connection the power supply VCC, PMOS tube M3 of PMOS tube M3, capacitance C2 One end, the drain electrode of PMOS tube M5, the grid of PMOS tube M6, NMOS tube M7 grid；The source electrode ground connection of NMOS tube M4；Capacitance C2 The other end ground connection；The source electrode of PMOS tube M5 connects power supply VCC, the drain electrode of the grid connection PMOS tube M6 of PMOS tube M5 and NMOS tube The drain electrode of M7, the input terminal of phase inverter；The source electrode connection power supply VCC of PMOS tube M6；The source electrode ground connection of NMOS tube M7；Phase inverter Outputs of the output terminal VCC_Good as level monitoring module.It is only with 4 PMOS tube, 3 NMOS tubes and two capacitance realities Level monitoring is showed, compared with traditional level monitoring, the delay unit that the present invention uses is less, makes entire area smaller.

It is 10 that NMOS tube M1, which is its breadth length ratio of large-size device, in level monitoring module of the present invention, and PMOS tube M2 is Wider than the tube long than being 1/10, NMOS tube M1 breadth length ratios are 100 times of PMOS tube M2 breadth length ratios；PMOS tube M3 large-size devices its Breadth length ratio is 10, and NMOS tube M4 is down that its breadth length ratio is 1/20 than pipe, and the breadth length ratio of PMOS tube M3 is NMOS tube M4 breadth length ratios 200 times.PMOS tube M2 and NMOS tube M4 is long much larger than wide ratio pipe, leaks the sub-threshold region of PMOS tube M2 and NMOS tube M4 Electric very little reduces the power consumption of entire module.Power supply VCC is less than the unlatching threshold value of NMOS tube and the unlatching threshold value of PMOS tube simultaneously When, capacitance C1 makes the voltage value that node NOD1 voltages are power supply VCC, and capacitance C2 makes node NOD2 voltage values for ground；Power supply VCC is big During one in the unlatching threshold value of NMOS tube and the unlatching threshold value of PMOS tube, since NMOS and PMOS cannot be simultaneously turned on, only There are sub-threshold region electric leakage, so high current will not be generated；When power supply VCC is more than the unlatching threshold value of NMOS tube and opening for PMOS tube When opening threshold value, and less than NMOS tube unlatching threshold value and PMOS tube the sum of unlatching threshold value when, since NMOS tube M1 sizes are long-range In PMOS tube M2, so unlatching threshold value of the NOD1 voltages close to NMOS tube；Since PMOS tube M3 gate source voltages are less than PMOS tube Unlatching threshold value, PMOS tube M3 cut-offs, NMOS tube M4 makes node NOD2 voltages remain ground.Final level monitoring module output VCC_Good is low level；Node NOD1 when power supply VCC is equal to the sum of the unlatching threshold value of NMOS tube and the unlatching threshold value of PMOS tube Voltage is approximately the unlatching threshold value of NMOS tube, and PMOS tube M3 gate source voltages are begun to turn on for the unlatching threshold value of PMOS tube.Due to PMOS tube M3 sizes are much larger than NMOS tube M4, and node NOD2 voltage instantaneous is drawn high by M3 to the voltage value of power supply VCC, level monitoring Module output VCC_Good becomes high level from low level；When power supply VCC is more than the unlatching threshold value of NMOS tube and opening for PMOS tube When opening the sum of threshold value, node NOD1 voltages are always the unlatching threshold value of NMOS tube, and PMOS tube M3 is normally opened, and node NOD2 voltages are always For power supply VCC voltages, level monitoring module output VCC_Good is high level.

It is of the present invention delay deburring circuit as shown in figure 3, including：With door AND31, phase inverter INV31, phase inverter INV32, phase inverter INV33, phase inverter INV34, capacitance C31, capacitance C32, capacitance C33 and NAND gate NAND31；

When originally powering on redundant module single particle effect not occurring, what the ER_RST input terminals of delay deburring circuit received The output of fluffing check and redundancy output control module is high level, when originally powering on redundant module generation single particle effect, is prolonged When deburring circuit the fluffing check that receives of ER_RST input terminals and the output of redundancy output control module become low level, prolong When deburring circuit this low level signal is transmitted to internal storage unit state monitoring module.

Internal storage unit state monitoring module of the present invention as shown in figure 4, including：Phase inverter INV41, phase inverter INV42 ..., phase inverter INV4n, storage unit SRAM41, storage unit SRAM42 ..., storage unit SRAM4n, NMOS Pipe M41, NMOS tube M42, NMOS tube ..., NMOS tube M4n or door OR4n；N is positive integer, and n is more than or equal to 3, and concrete numerical value can It is adjusted according to actual circuit needs；

The input terminal of phase inverter INV41 is connected to the output terminal Power_Good of delay deburring circuit, is connected to simultaneously It is the input terminal (connection relation of phase inverter INV43 to phase inverter INV4n-1 is identical with phase inverter INV42) of phase inverter INV42, anti- The input terminal of phase device INV4n, the R input of storage unit SRAM41, storage unit SRAM42 R input (storage unit The connection mode of SRAM43 to storage unit SRAM4n-1 is identical with storage unit SRAM42's), the R of storage unit SRAM4n it is defeated Enter end, the grid of NMOS tube M41, NMOS tube M42 the grid (connection relation and NMOS tube of NMOS tube M43 to NMOS tube M4n-1 M42 is identical), the grid of NMOS tube M4n；The output terminal of phase inverter INV41 is connected to the RN input terminals of storage unit SRAM41；Instead The output terminal of phase device INV42 is connected to the RN input terminals of storage unit SRAM42；The output terminal of phase inverter INV4n is connected to storage The RN input terminals of cell S RAM4n；The Z output terminals of storage unit SRAM41 are connected to or the first input end of door OR4n；Storage is single The ZN output terminals of first SRAM41 are connected to the drain electrode of NMOS tube M41；The Z output terminals of storage unit SRAM42 are connected to or door OR4n The second input terminal；The ZN output terminals of storage unit SRAM42 are connected to the drain electrode of NMOS tube M42；The Z of storage unit SRAM4n Output terminal is connected to or the n-th input terminal of door OR4n；The ZN output terminals of storage unit SRAM4n are connected to the leakage of NMOS tube M4n Pole；The source electrode ground connection of NMOS tube M41；The source electrode ground connection of NMOS tube M42；The source electrode ground connection of NMOS tube M4n；Or the POR_ of door OR4n Latch output terminals are connected to the WL of storage unit SRAM41, the WL input terminals of storage unit SRAM42, storage unit SRAM4n WL input terminals, while as the output of internal storage unit state monitoring module.

When Power_Good is high, (storage unit SRAM43 is single to storage by storage unit SRAM41, storage unit SRAM42 The state change of first SRAM4n-1 is identical with storage unit SRAM42), storage unit SRAM4n be in write high level state or The input of door OR4n is high level, and output POR_Latch is height.When Power_Good is from high to low, storage unit SRAM41, storage unit SRAM42, storage unit SRAM4n are written into low level, and after the completion of write-in or the input of door OR4n is complete Portion becomes low level or the output POR_Latch of door OR4n becomes low.By storage unit SRAM41, storage unit SRAM42, The ablation process of storage unit SRAM4n, it is ensured that the storage unit that the voltage value of power supply VCC is in these types is all can be with The section being smoothly written ensures a variety of storage units all

Digital assistant time delay module of the present invention is as shown in Figure 5, including：With door AND51, oscillator OSC, register FF51, register FF52, register FF53, register FF54, register FF55, register FF56, register FF57, register FF58, register FF59；

When originally powering on redundant module mistake not occurring, false retrieval is connect out for ER_RST with an input terminal of door AND51 It surveys and the value of the output of redundancy output control module is height, the output with door AND51 is with the POR_Good's of another output terminal It is worth identical；When the output POR_Latch of internal storage unit state monitoring module is high, the R input of register FF59 is height, Register FF59 output POR_Good are low, and oscillator OSC oscillations, the R input of register FF51 can be counted normally to be low, But register FF52, register FF53, register FF54, register FF55, register FF56, register FF57, register The R input of FF58 is all height, in cleared condition；When the output POR_Latch of internal storage unit state monitoring module is When low, register FF52, register FF53, register FF54, register FF55, register FF56, register FF57, register The R input of FF58 is low, in normal writable state, as oscillator OSC vibrates, by register FF51, register FF52, register FF53, register FF54, register FF55, register FF56, register FF57, register FF58, register FF59 counters start counting up, and after counter counts are full, i.e. the output POR_Good of register FF59 becomes high from low, and number is auxiliary The output POR_Good of time delay module is helped to become high from low, POR_OUT signals close oscillator OSC.

It is with an input terminal of door AND51 when originally powering on redundant module and single particle effect generation mistake output occurring The value of the output of ER_RST connection fluffing checks and redundancy output control module is low, and the value of AND51 is low, and oscillator OSC shakes It swings, the R input of register FF51 can be counted normally to be low, register FF52, register FF53, register FF54, deposit Device FF55, register FF56, register FF57, register FF58 R input to be low, in normal writable state, with Oscillator OSC vibrates, by register FF51, register FF52, register FF53, register FF54, register FF55, register FF56, register FF57, register FF58, register FF59 counters start counting up, after counter counts are full, i.e. register The output POR_Good of FF59 becomes high from low, and the output POR_Good of digital assistant time delay module becomes high from low, POR_OUT Signal closes oscillator OSC.The output of fluffing check and redundancy output control module carries out digital assistant time delay module Resetting makes the output for originally powering on redundant module become high again, removes the influence that the single-particle inversion generated generates, avoids it Accumulation.

Fluffing check of the present invention and redundancy output control module are as shown in Figure 6, including：XOR gate XOR61, exclusive or Door XOR62, XOR gate XOR63, NAND gate NAND61, NAND gate NAND62, NAND gate NAND63；

The truth table of fluffing check of the present invention and redundancy output control module is as shown in table 1 below, can be with from table Find out that three inputs of fluffing check and redundancy output control module respectively believe the POR_Good1 signals of reception, POR_Good2 Number, POR_Good3 signals be compared, if POR_Good1 signals, POR_Good2 signals, POR_Good3 signal all sames, Three outputs OUT1, OUT2 and OUT3 of fluffing check and redundancy output control module are high level；If POR_Good1 signals Different from POR_Good2 signals and POR_Good3 signals, then OUT1 is low level, and OUT2 and OUT3 are high level；If POR_ Good2 signals are different from POR_Good1 signals and POR_Good3 signals, then it is high electric that OUT2, which is low level, OUT1 and OUT3, It is flat；If POR_Good3 signals are different from POR_Good1 signals and POR_Good2 signals, OUT3 be low level, OUT1 and OUT2 is high level；Fluffing check and redundancy output control module can detect that with door in three tunnels by three XOR gates and three Arbitrary mistake all the way, be connected to by the output of the module and power on redundant module, can be answered redundant module is powered on The accumulation of single particle effect is removed in position；The output for powering on redundant module can be cut off by being connected to controllable output buffer, be avoided The output of mistake influences the output of entire electrification reset circuit.

1 fluffing check of table and redundancy output control module truth table

The single-particle experimental result of the electrification reset circuit of the present invention is tested with the single-particle of original electrification reset circuit As a result comparison is as shown in fig. 7, the abscissa in figure is LET, i.e. linear energy transfer；Ordinate is crosssection, i.e., Upset cross section；Its medium and small black box represents the single-particle experimental result of the electrification reset circuit before reinforcing, according to thick curve The weibull curves that experimental result fits, the turn threshold LETTH that the electrification reset circuit is can be calculated from curve are 3.07MeV.cm2/mg, saturation section are 2.13E-6cm2/device；Its medium and small black triangle represents the electrification reset of the present invention The single-particle experimental result of circuit, because simple grain sub-error does not occur in the case of low LET values for it, so it is less than in LET Overturning number during 22MeV.cm2/mg is zero, only mistake occurs 1 time in 22MeV.cm2/mg, is occurred in 37MeV.cm2/mg wrong Accidentally 2 times, mistake occurs in 79MeV.cm2/mg 1 time, error number is very little, can not be fitted weibull curves, directly from error number On can obtain the present invention electrification reset circuit turn threshold LETTH between 13MeV.cm2/mg and 22MeV.cm2/mg, It is 4.23 to 7.16 times of original circuit, and its saturation section is 2E-7cm2/device, is original electrification reset circuit 10 times, consolidation effect is notable.

In conclusion the present invention generation single particle effect malfunctioned by fluffing check and redundancy output control module it is upper Electric redundant module detected, and by being resetted redundant module is powered on, remove the accumulation of single particle effect；It is connected to controllable Output buffer can cut off the output for powering on redundant module, avoid the output of mistake and influence the defeated of entire electrification reset circuit Go out, so as to obtain significant single particle effect consolidation effect.

Claims

1. a kind of electrification reset circuit reinforced suitable for aerospace with the single-particle of SRAM type FPGA, it is characterised in that：Including electricity Source VCC, three identical power on redundant module, fluffing check and redundancy output control module and three controllable output buffers； Three identical to power on redundant module, respectively first power on redundant module, second power on redundant module, third powers on redundancy mould Block；Three controllable output buffers are respectively that the first controllable output buffer, the second controllable output buffer, third controllably export Buffer；

Redundant module each is powered on, including level monitoring module, delay deburring circuit, internal storage unit status monitoring mould Block, digital assistant time delay module；

Power supply gives level monitoring module for power supply, and level monitoring module detects the voltage value of power supply in real time, when the voltage value of power supply is big When equal to the upper threshold voltage Vthr of setting, level monitoring module exports a high level signal and send to delay deburring electricity Road, the high level signal terminate reset signal, when the voltage value of power supply is less than the upper threshold voltage Vthr set, level prison Module one low level signal of output is surveyed to send to delay deburring circuit；

Be delayed deburring circuit, receives high level signal or low level signal that level monitoring module is sent, judges fluffing check And redundancy output control module feedback is when being high level signal, while when the high level signal received from level monitoring module or When the single pulse width of low level signal is less than or equal to the pulse width of setting, filters out, obtain using the single pulse as burr The low level signal of high level signal or smooth-going to smooth-going is sent to internal storage unit state monitoring module；Judge fluffing check And redundancy output control module feedback is when being low level signal, when the low electricity that fluffing check and redundancy output control module are fed back When pulse in ordinary mail number is less than or equal to the pulse width of setting, filtered out using the single pulse as burr, what is smoothed out is low Level signal is sent to internal storage unit state monitoring module；

Internal storage unit state monitoring module, when the low level signal of smooth-going that reception delay deburring circuit is sent, by Multiple storage units locking in portion's state of memory cells monitoring modular stops to storage unit write-in data, while to Digital assistant time delay module exports high level signal；Internal storage unit state monitoring module, when reception delay deburring circuit The high level signal for the smooth-going sent, internally multiple storage units write-in in state of memory cells monitoring modular and storage are single The opposite value of the value that is stored in member, then locks multiple storage units, that is, stops being written data to the storage unit, while after Low level signal is exported to digital assistant time delay module；

Digital assistant time delay module receives high level signal or low level letter that internal storage unit state monitoring module is sent Number, when receiving high level signal from internal storage unit state monitoring module and fluffing check and redundancy output control module When being fed back to high level, multiple registers in digital assistant time delay module are in the lock state, i.e., register memory storage Numerical value is constant, exports low level signal, i.e. the output of digital assistant time delay module is low level signal；

When receiving high level signal from internal storage unit state monitoring module and fluffing check and redundancy output control mould Block when being fed back to low level or when receiving low level signal from internal storage unit state monitoring module and fluffing check And when being fed back to high level or when from internal storage unit state monitoring module receiving low level of redundancy output control module During signal and fluffing check and when being fed back to low level of redundancy output control module, oscillator start oscillation output clock letter Number, late register is vibrated each time to be counted once, after register is posted completely, output high level, i.e. digital assistant time delay module It exports as high level signal；

The output for powering on redundant module by first be denoted as POR_Good1 signals, second power on redundant module POR_Good2 signals, Third powers on redundant module POR_Good3 signals；The output for powering on redundant module by first is denoted as POR_Good1 signals, second Power on redundant module POR_Good2 signals, third power on redundant module POR_Good3 signals send it is defeated to fluffing check and redundancy Go out control module；The output for powering on redundant module by first is denoted as POR_Good1 signals and send to the first controllable output buffer；It will Second output for powering on redundant module is denoted as POR_Good2 signals and send to the second controllable output buffer；Third is powered on into redundancy The output of module is denoted as POR_Good3 signals and send to the controllable output buffer of third；

Fluffing check and redundancy output control module there are three input and three outputs, three outputs be respectively OUT1, OUT2 and OUT3, OUT1 output feed back to the first delay deburring circuit for powering on redundant module, digital assistant time delay module and send to the One controllable output buffer, OUT2 outputs feed back to second and power on the delay deburring circuit of redundant module, digital assistant delay Module is simultaneously sent to the second controllable output buffer, OUT3 outputs feed back to third power on redundant module delay deburring circuit, Digital assistant time delay module is simultaneously sent to the controllable output buffer of third；

Three inputs of fluffing check and redundancy output control module respectively believe the POR_Good1 signals of reception, POR_Good2 Number, POR_Good3 signals be compared, if POR_Good1 signals, POR_Good2 signals, POR_Good3 signal all sames, Three outputs OUT1, OUT2 and OUT3 of fluffing check and redundancy output control module are high level；If POR_Good1 signals Different from POR_Good2 signals and POR_Good3 signals, then OUT1 is low level, and OUT2 and OUT3 are high level；If POR_ Good2 signals are different from POR_Good1 signals and POR_Good3 signals, then it is high electric that OUT2, which is low level, OUT1 and OUT3, It is flat；If POR_Good3 signals are different from POR_Good1 signals and POR_Good2 signals, OUT3 be low level, OUT1 and OUT2 is high level；

It is high level in the output signal for receiving fluffing check and redundancy output control module when the first controllable output buffer When, it is exported after first being powered on the output POR_Good1 signal inversions of redundant module；When the first controllable output buffer, connecing When receiving the output signal of fluffing check and redundancy output control module as low level, the first controllable output buffer does not export letter Number；

It is high level in the output signal for receiving fluffing check and redundancy output control module when the second controllable output buffer When, it is exported after second being powered on the output POR_Good2 signal inversions of redundant module；When the second controllable output buffer, connecing When receiving the output signal of fluffing check and redundancy output control module as low level, the second controllable output buffer does not export letter Number；

It is high level in the output signal for receiving fluffing check and redundancy output control module when the controllable output buffer of third When, it is exported after third to be powered on to the output POR_Good3 signal inversions of redundant module；When the controllable output buffer of third, connecing When receiving the output signal of fluffing check and redundancy output control module as low level, the controllable output buffer of third does not export letter Number.

2. a kind of electrification reset electricity reinforced suitable for aerospace with the single-particle of SRAM type FPGA according to claim 1 Road, it is characterised in that：The level monitoring module includes：PMOS tube M2, PMOS tube M3, PMOS tube M5, NMOS tube M1, NMOS tube M4, NMOS tube M7, capacitance C1, capacitance C2, phase inverter；

The grounded-grid of PMOS tube M2, the source electrode connection power supply VCC of PMOS tube M2, the drain electrode of PMOS tube M2 connect NMOS tube simultaneously The grid of M1 and drain electrode, one end of capacitance C1, PMOS tube M3 grid；The source electrode ground connection of NMOS tube M1；

The source electrode connection power supply of grid connection the power supply VCC, PMOS tube M3 of another termination power VCC of capacitance C1, NMOS tube M4 The drain electrode of the drain electrode connection NMOS tube M4 of VCC, PMOS tube M3, one end of capacitance C2, the drain electrode of PMOS tube M5, PMOS tube M6 grid Pole, the grid of NMOS tube M7；The source electrode ground connection of NMOS tube M4；The other end ground connection of capacitance C2；The source electrode of PMOS tube M5 connects power supply The drain electrode of the grid connection PMOS tube M6 of VCC, PMOS tube M5 and the drain electrode of NMOS tube M7, the input terminal of phase inverter；PMOS tube M6 Source electrode connection power supply VCC；The source electrode ground connection of NMOS tube M7；The output terminal VCC_Good of phase inverter is as level monitoring module Output.

3. a kind of electrification reset electricity reinforced suitable for aerospace with the single-particle of SRAM type FPGA according to claim 1 Road, it is characterised in that：The delay deburring circuit includes：With door AND31, phase inverter INV31, phase inverter INV32, phase inverter INV33, phase inverter INV34, capacitance C31, capacitance C32, capacitance C33 and NAND gate NAND31；

The output VCC_Good of level monitoring module, another input are connect for VCC_Good with an input terminal of door AND31 The output for ER_RST connection fluffing checks and redundancy output control module is held, wherein first powers on the delay unhairing of redundant module The output OUT1 of thorn circuit connection fluffing check and redundancy output control module, second power on redundant module delay deburring it is electric The output OUT2 that road connects fluffing check and redundancy output control module is connected, third power on redundant module delay deburring it is electric Road connects the output OUT3 of fluffing check and redundancy output control module；It connect phase inverter INV31's with the output terminal of door AND31 Input terminal, while connect an input terminal of NAND gate NAND31 and one end of capacitance C31；The other end connection electricity of capacitance C31 Source VCC；The input terminal of connection phase inverter INV32 while one end of the output terminal connection capacitance C32 of phase inverter INV31；Capacitance The other end ground connection of C32；The input terminal of the output terminal connection phase inverter INV33 of phase inverter INV32；The output of phase inverter INV33 The input terminal of end connection phase inverter INV34；While one end of the output terminal connection capacitance C33 of phase inverter INV34 connection with it is non- Another input terminal of door NAND31；The other end of capacitance C33 is connected to power supply VCC；The output terminal of NAND gate NAND31 Outputs of the Power_Good as delay deburring circuit.

4. a kind of electrification reset electricity reinforced suitable for aerospace with the single-particle of SRAM type FPGA according to claim 1 Road, it is characterised in that：The internal storage unit state monitoring module includes：Phase inverter INV41, phase inverter INV42 ..., Phase inverter INV4n, storage unit SRAM41, storage unit SRAM42 ..., storage unit SRAM4n, NMOS tube M41, NMOS Pipe M42 ..., NMOS tube M4n or door OR4n；

The input terminal of phase inverter INV41 is connected to the output terminal Power_Good of delay deburring circuit, while is connected to reverse phase The input terminal of device INV42, the input terminal of phase inverter INV4n, the R input of storage unit SRAM41, storage unit SRAM42 R Input terminal, the R input of storage unit SRAM4n, the grid of NMOS tube M41, the grid of NMOS tube M42, NMOS tube M4n grid Pole；The output terminal of phase inverter INV41 is connected to the RN input terminals of storage unit SRAM41；The output terminal connection of phase inverter INV42 To the RN input terminals of storage unit SRAM42；The output terminal of phase inverter INV4n is connected to the RN input terminals of storage unit SRAM4n； The Z output terminals of storage unit SRAM41 are connected to or the first input end of door OR4n；The ZN output terminals of storage unit SRAM41 connect It is connected to the drain electrode of NMOS tube M41；The Z output terminals of storage unit SRAM42 are connected to or the second input terminal of door OR4n；Storage is single The ZN output terminals of first SRAM42 are connected to the drain electrode of NMOS tube M42；The Z output terminals of storage unit SRAM4n are connected to or door OR4n The n-th input terminal；The ZN output terminals of storage unit SRAM4n are connected to the drain electrode of NMOS tube M4n；The source electrode of NMOS tube M41 connects Ground；The source electrode ground connection of NMOS tube M42；The source electrode ground connection of NMOS tube M4n；Or the POR_Latch output terminals of door OR4n are connected to and deposit The WL of storage unit SRAM41, the WL input terminals of storage unit SRAM42, storage unit SRAM4n WL input terminals, while be used as in The output of portion's state of memory cells monitoring modular.

5. a kind of electrification reset electricity reinforced suitable for aerospace with the single-particle of SRAM type FPGA according to claim 1 Road, it is characterised in that：The digital assistant time delay module includes：With door AND51, oscillator OSC, register FF51, register FF52, register FF53, register FF54, register FF55, register FF56, register FF57, register FF58, register FF59；

The output of fluffing check and redundancy output control module is connect for ER_RST with an input terminal of door AND51, wherein the One powers on the output OUT1 of the delay deburring circuit connection fluffing check of redundant module and redundancy output control module, on second The delay deburring circuit connection fluffing check of electric redundant module and the output OUT2 of redundancy output control module are connected, in third The delay deburring circuit connection fluffing check of electric redundant module and the output OUT3 of redundancy output control module；With door AND51 Output terminal connection register FF51 R input, while the control signal of connection oscillator OSC；The R of register FF52 is defeated Enter end for POR_Latch, receive the output POR_Latch of internal storage unit state monitoring module, while connect register The R input of FF53, the R input of register FF54, the R input of register FF55, register FF56 R input, post The R input of storage FF57, the R input of register FF58, register FF59 R input；The output terminal of oscillator OSC connects It is connected to the input end of clock of register FF51；The D input terminals of the QN output terminals connection register FF51 of register FF51；Register The input end of clock of the Q output connection register FF52 of FF51；The D of the QN output terminals connection register FF52 of register FF52 Input terminal；The input end of clock of the Q output connection register FF53 of register FF51；The QN output terminals connection of register FF53 The D input terminals of register FF53；The input end of clock of the Q output connection register FF54 of register FF53；Register FF54 QN output terminals connection register FF54 D input terminals；The clock input of the Q output connection register FF55 of register FF54 End；The D input terminals of the QN output terminals connection register FF55 of register FF55；The Q output connection register of register FF55 The input end of clock of FF56；The D input terminals of the QN output terminals connection register FF56 of register FF56；The Q of register FF56 is defeated The input end of clock of outlet connection register FF57；The D input terminals of the QN output terminals connection register FF57 of register FF57；It posts The input end of clock of the Q output connection register FF58 of storage FF57；The QN output terminals connection register of register FF58 The D input terminals of FF58；The input end of clock of the Q output connection register FF59 of register FF58；The D inputs of register FF59 End is connected to power supply VCC；As number while the Q output of register FF59 is connected to another input terminal with door AND51 Word assists the output POR_Good of time delay module.

6. a kind of electrification reset electricity reinforced suitable for aerospace with the single-particle of SRAM type FPGA according to claim 1 Road, it is characterised in that：The fluffing check and redundancy output control module include：XOR gate XOR61, XOR gate XOR62, exclusive or Door XOR63, NAND gate NAND61, NAND gate NAND62, NAND gate NAND63；

An input terminal POR_Good1 connection first of XOR gate XOR61 powers on the digital assistant time delay module of redundant module Output, while connect an input terminal of XOR gate XOR62；Another input terminal POR_Good2 connections of XOR gate XOR62 Two power on the output of the digital assistant time delay module of redundant module, while connect an input terminal of XOR gate XOR63；XOR gate Another input terminal POR_Good3 connections third of XOR63 powers on the output of the digital assistant time delay module of redundant module, simultaneously Connect another input terminal of XOR gate XOR61；An input terminal of the output terminal connection NAND gate NAND61 of XOR gate XOR61 While connection NAND gate NAND63 an input terminal；One of the output terminal connection NAND gate NAND62 of XOR gate XOR62 Another input terminal of NAND gate NAND61 is connected while input terminal；The output terminal connection NAND gate of XOR gate XOR63 Another input terminal of NAND gate NAND62 is connected while another input terminal of NAND63；The output terminal of NAND gate NAND61 As fluffing check and the output terminal OUT1 of redundancy output control module；The output terminal of NAND gate NAND62 as fluffing check and The output terminal OUT2 of redundancy output control module；The output terminal of NAND gate NAND63 is as fluffing check and redundancy output control mould The output terminal OUT3 of block.

7. a kind of electrification reset electricity reinforced suitable for aerospace with the single-particle of SRAM type FPGA according to claim 2 Road, it is characterised in that：NMOS tube M1 is large-size device in the level monitoring module, which is 10； PMOS tube M2 is down than pipe, is somebody's turn to do wider than the tube long than being 1/10；NMOS tube M1 breadth length ratios are 100 times of PMOS tube M2 breadth length ratios； PMOS tube is M3 large-size devices, which is 10；NMOS tube M4 is down that than pipe being somebody's turn to do long ratio wider than the tube is 1/20；The breadth length ratio of PMOS tube M3 is 200 times of NMOS tube M4 breadth length ratios.