CN101794241A - Circuit of power-on reset of triple redundancecy fault-tolerance computer based on programmable logic device - Google Patents
Circuit of power-on reset of triple redundancecy fault-tolerance computer based on programmable logic device Download PDFInfo
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- CN101794241A CN101794241A CN201010101910A CN201010101910A CN101794241A CN 101794241 A CN101794241 A CN 101794241A CN 201010101910 A CN201010101910 A CN 201010101910A CN 201010101910 A CN201010101910 A CN 201010101910A CN 101794241 A CN101794241 A CN 101794241A
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Abstract
The invention provides a circuit of the power-on reset of a triple redundancecy fault-tolerance computer based on a programmable logic device, which comprises a power-on reset soft filtering circuit, a power-on reset triple redundancecy state register circuit, a power-on reset triple redundancecy synchronous waiting circuit, a power-on reset triple redundancecy voting output circuit, a power-on reset soft watchdog circuit and the like. The power-on reset process of the triple redundancecy fault-tolerance computer is monitored by the circuit; each computer writes a power-on reset state into a power-on reset triple redundancecy state register through the power-on reset soft filtering circuit; the power-on reset triple redundancecy synchronous waiting circuit controls synchronous waiting time, and a power-on reset control command bit is output to each computer by the power-on reset triple redundancecy voting output circuit to start a main program to operate; and operation states of each computer are detected in real time by the power-on reset soft watchdog circuit when the main program operates to remove the fault computer in the triple redundancecy fault-tolerance computer. The circuit of the triple redundancecy fault-tolerance computer for the power-on reset based on the programmable logic device solves the problem of real-time control of the power-on reset of the triple redundancecy fault-tolerance computer, realizes the intelligent management of the power-on reset of the triple redundancecy fault-tolerance computer and ensures high reliability of the power-on reset of the triple redundancecy fault-tolerance computer.
Description
Technical field
The present invention relates to the cybernation technology, based on programmable logic device (PLD) designed cheaply, the circuit of triple redundance fault-tolerant computer electrification reset dirigibility, modular and open, solved the real-time control problem of triple redundance fault-tolerant computer electrification reset, realize triple redundance fault-tolerant computer electrification reset intelligent management, guaranteed triple redundance fault-tolerant computer electrification reset high reliability.
Background technology
From the sixties, along with the application of computing machine at some key areas, the inefficacy of computing machine can cause tremendous loss, and the remaining fault-tolerant high-reliability control system with functions such as fault detection and diagnosis begins to use in fields such as space flight and aviation.To the seventies, adopt the fault-tolerant highly reliable system of three remainings, be applied to fields such as communication and space flight, possessed backup functionality, self-checking function, self-recovering function, and some representative large-scale Tolerate and redundance systems succeed in developing during this period also.In recent years, the develop rapidly of microelectric technique makes embedded control system widespread use every field, the fault-tolerant high-reliability control system of tradition framework can not satisfy in key areas embedded control system application demands such as Aero-Space, defence and military, commercial production, security controls, and programmable logic device (PLD) loads the technical development of a plurality of microprocessor cores, provides condition for programmable logic device (PLD) designs fault-tolerant embedded control system.
The field-programmable chip is meant the special IC of being realized required function by user program, adopt programmable gate array (Field Programmable Gate Array) technology, promptly be arranged in array and form, and connect the required design of these logic function blocks realizations by programmable interconnect resource by logic function block.At present the field-programmable chip-scale is done very greatly, along with the embedded processor Application of Nuclear Technology, and realization with better function, the dirigibility of design is bigger.
Circuit based on the programmable logic device (PLD) electrification reset is used for the triple redundance fault-tolerant computer, does not domesticly see relevant product and relevant patent.
Summary of the invention
The object of the present invention is to provide a kind of cheaply, the circuit based on programmable logic device (PLD) electrification reset dirigibility, modular and open, be used for the triple redundance fault-tolerant computer, solved the real-time control problem of triple redundance fault-tolerant computer electrification reset, realize triple redundance fault-tolerant computer electrification reset intelligent management, guaranteed triple redundance fault-tolerant computer electrification reset high reliability.
Circuit system structure based on programmable logic device (PLD) triple redundance fault-tolerant computer electrification reset is seen accompanying drawing 1, comprise the soft filtering circuit of electrification reset, electrification reset triple redundance status register circuit, the electrification reset triple redundance is waited for circuit synchronously, electrification reset triple redundance voting output circuit, the soft watchdog circuit of electrification reset etc., triple redundance fault-tolerant computer electrification reset process is monitored by this circuit, by the soft filtering circuit of electrification reset, each computing machine writes the electrification reset state to electrification reset triple redundance status register, the electrification reset triple redundance waits for that synchronously circuit controls the synchronous stand-by period, export electrification reset control command position by electrification reset triple redundance voting output circuit to each computing machine, start the master routine operation, when master routine moves, detect the running status of each computing machine in real time, realize the excision of faulty channel in the triple redundance fault-tolerant computer by the soft watchdog circuit of electrification reset.
The soft filtering circuit of electrification reset is seen accompanying drawing 2, comprise 3 paths altogether, each path is by the high peak counter of programmable logic cells design, the low peak counter, OR circuit is formed, and the high peak counter mainly shields effective clutter of disarmed state, and the low peak counter mainly shields the invalid clutter of effective status, by OR circuit output power-on reset signal, guarantee the authenticity of signal at last.
Electrification reset triple redundance status register circuit structure is seen accompanying drawing 3, by the register of programmable logic cells design, deposits A machine power-on reset signal state respectively, B machine power-on reset signal state, C machine power-on reset signal state.
The electrification reset triple redundance waits for that synchronously circuit sees accompanying drawing 4, compare by programmable logic cells design comparator circuit and electrification reset triple redundance status register state, if also do not write the synchronous latency counter of triple redundance that affiliation starts the programmable logic cells design fully, in official hour, wait for and do not write reset mode, exceeding the stand-by period thinks that then this reset mode is invalid, starts triple redundance voting output circuit.
Electrification reset triple redundance voting output circuit I system or II are that principle of work is seen accompanying drawing 5, triple redundance voting output circuit waits for that the electrification reset triple redundance waits for that synchronously the circuit requests signal will carry out that electrification reset is redundant decides by vote to A machine and B machine with the C machine, two states are arranged in A machine and B machine and the C machine, and all this is an output electrification reset useful signal effectively the time, and this is to export the electrification reset invalid signals when invalid when there being two in A machine and B machine and the C machine.
A machine pulse signal when the triple redundance fault-tolerant computer normally moves, B machine pulse signal, the soft watchdog circuit of C machine pulse signal input electrification reset, do not have normal output pulse signal when the soft watchdog circuit of electrification reset detects certain computing machine, then put invalid mode bit to triple redundance status register circuit.
The beneficial effect of the embodiment of the invention is, based on programmable logic device (PLD) designed cheaply, the circuit of triple redundance fault-tolerant computer electrification reset dirigibility, modular and open, solved the real-time control problem of triple redundance fault-tolerant computer electrification reset, realize triple redundance fault-tolerant computer electrification reset intelligent management, guaranteed triple redundance fault-tolerant computer electrification reset high reliability.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, does not constitute limitation of the invention.In the accompanying drawings:
The circuit system structure of the triple redundance fault-tolerant computer electrification reset of Fig. 1 Programmable Design;
The soft filtering circuit of Fig. 2 electrification reset;
Fig. 3 electrification reset triple redundance status register circuit structure;
Fig. 4 electrification reset triple redundance is waited for the circuit FB(flow block) synchronously;
Fig. 5 electrification reset triple redundance voting output circuit principle of work;
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer,, the present invention is described in further details below in conjunction with embodiment and accompanying drawing.At this, exemplary embodiment of the present invention and explanation thereof are used to explain the present invention, but not as a limitation of the invention.
Present embodiment provides the circuit based on the triple redundance fault-tolerant computer electrification reset of programmable device FPGA design, solved the real-time control problem of triple redundance fault-tolerant computer electrification reset, realize triple redundance fault-tolerant computer electrification reset intelligent management, guaranteed triple redundance fault-tolerant computer electrification reset high reliability.
Adopt programmable gate array (Field Programmable Gate Array-FPGA) technology, promptly be arranged in array and form, and connect the required design of these logic function blocks realizations by programmable interconnect resource by logic function block.Utilize the electric design automation eda tool, adopt programming device, realize systemic-function by design chips, this method for designing based on chip, can define the internal logic and the pin of device by the deviser, the major part work that former cause board design is finished is placed in the chip design and carries out, not only realize multiple digital logic system function by chip design, and workload and the difficulty of circuit diagram design and board design have been significantly reduced, strengthen design flexibility, improved work efficiency.
The soft filtering circuit of electrification reset, electrification reset triple redundance status register circuit, the electrification reset triple redundance is waited for circuit synchronously, electrification reset triple redundance voting output circuit, functional modules such as the soft watchdog circuit of electrification reset are based on the EPM3128ATI64 programming device design of Altra company, based on programmable logic device (PLD) designed cheaply, the circuit of triple redundance fault-tolerant computer electrification reset dirigibility, modular and open.
Above-described embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is the specific embodiment of the present invention; and be not intended to limit the scope of the invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. circuit based on programmable logic device (PLD) triple redundance fault-tolerant computer electrification reset is characterized in that:
Comprise the soft filtering circuit of electrification reset, electrification reset triple redundance status register circuit, the electrification reset triple redundance is waited for circuit synchronously, electrification reset triple redundance voting output circuit, the soft watchdog circuit of electrification reset etc., triple redundance fault-tolerant computer electrification reset process is monitored by this circuit, by the soft filtering circuit of electrification reset, each computing machine writes the electrification reset state to electrification reset triple redundance status register, the electrification reset triple redundance waits for that synchronously circuit controls the synchronous stand-by period, export electrification reset control command position by electrification reset triple redundance voting output circuit to each computing machine, start the master routine operation, when master routine moves, detect the running status of each computing machine in real time, realize the excision of faulty channel in the triple redundance fault-tolerant computer by the soft watchdog circuit of electrification reset.
2. the soft filtering circuit of electrification reset according to claim 1 is characterized in that:
A machine power-on reset signal in the triple redundance fault-tolerant computer, B machine power-on reset signal, C machine power-on reset signal filters spike in the start-up course and burr by the soft filtering circuit of electrification reset, guarantees the authenticity of signal.
3. electrification reset triple redundance status register circuit according to claim 1 is characterised in that:
A machine power-on reset signal in the triple redundance fault-tolerant computer, B machine power-on reset signal, C machine power-on reset signal writes triple redundance status register circuit mode bit separately by the useful signal of the soft filtering circuit of electrification reset.
4. electrification reset triple redundance according to claim 1 is waited for circuit synchronously, it is characterized in that:
The electrification reset triple redundance waits for synchronously in the electric circuit inspection triple redundance fault-tolerant computer whether triple redundance status register circuit A machine and B machine and C machine write reset mode, do not start the synchronous latency counter of triple redundance if also write affiliation fully, in official hour, wait for and do not write reset mode, exceeding the stand-by period thinks that then this reset mode is invalid, starts triple redundance voting output circuit.
5. electrification reset triple redundance voting output circuit according to claim 1 is characterized in that:
Triple redundance voting output circuit waits for that the electrification reset triple redundance waits for that synchronously the circuit requests signal will carry out that electrification reset is redundant decides by vote to A machine and B machine with the C machine, two states are arranged in A machine and B machine and the C machine, and all this is an output electrification reset useful signal effectively the time, and this is to export the electrification reset invalid signals when invalid when there being two in A machine and B machine and the C machine.
6. the soft watchdog circuit of electrification reset according to claim 1 is characterized in that:
A machine pulse signal when the triple redundance fault-tolerant computer normally moves, B machine pulse signal, the soft watchdog circuit of C machine pulse signal input electrification reset, do not have normal output pulse signal when the soft watchdog circuit of electrification reset detects certain computing machine, then put invalid mode bit to triple redundance status register circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010101910A CN101794241A (en) | 2010-01-27 | 2010-01-27 | Circuit of power-on reset of triple redundancecy fault-tolerance computer based on programmable logic device |
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| CN201010101910A CN101794241A (en) | 2010-01-27 | 2010-01-27 | Circuit of power-on reset of triple redundancecy fault-tolerance computer based on programmable logic device |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101968756A (en) * | 2010-09-29 | 2011-02-09 | 航天东方红卫星有限公司 | Satellite-borne computer autonomously computer switching system based on field programmable gata array (FPGA) |
| CN102331786A (en) * | 2011-07-18 | 2012-01-25 | 北京航空航天大学 | Dual-computer cold-standby system of attitude and orbit control computer |
| CN103529691A (en) * | 2012-07-04 | 2014-01-22 | 北京精密机电控制设备研究所 | Table look-up three-redundant-signal processing method |
| CN105634454A (en) * | 2016-02-26 | 2016-06-01 | 北京时代民芯科技有限公司 | Single-particle reinforced power-on reset circuit applicable to SRAM type FPGA for aerospace |
| CN110442073A (en) * | 2019-08-30 | 2019-11-12 | 四川腾盾科技有限公司 | A kind of redundance Aircraft Management Computer MIO board channel fault logic judgment method |
| CN110737234A (en) * | 2019-10-21 | 2020-01-31 | 江苏云涌电子科技股份有限公司 | internal network safety monitoring device |
| CN111722020A (en) * | 2019-03-18 | 2020-09-29 | 深圳市汇顶科技股份有限公司 | Burr detection circuit |
-
2010
- 2010-01-27 CN CN201010101910A patent/CN101794241A/en active Pending
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101968756A (en) * | 2010-09-29 | 2011-02-09 | 航天东方红卫星有限公司 | Satellite-borne computer autonomously computer switching system based on field programmable gata array (FPGA) |
| CN101968756B (en) * | 2010-09-29 | 2012-07-18 | 航天东方红卫星有限公司 | Satellite-borne computer autonomously computer switching system based on field programmable gata array (FPGA) |
| CN102331786A (en) * | 2011-07-18 | 2012-01-25 | 北京航空航天大学 | Dual-computer cold-standby system of attitude and orbit control computer |
| CN102331786B (en) * | 2011-07-18 | 2013-05-08 | 北京航空航天大学 | Dual-computer cold-standby system of attitude and orbit control computer |
| CN103529691A (en) * | 2012-07-04 | 2014-01-22 | 北京精密机电控制设备研究所 | Table look-up three-redundant-signal processing method |
| CN105634454A (en) * | 2016-02-26 | 2016-06-01 | 北京时代民芯科技有限公司 | Single-particle reinforced power-on reset circuit applicable to SRAM type FPGA for aerospace |
| CN105634454B (en) * | 2016-02-26 | 2018-07-06 | 北京时代民芯科技有限公司 | A kind of electrification reset circuit reinforced suitable for aerospace with the single-particle of SRAM type FPGA |
| CN111722020A (en) * | 2019-03-18 | 2020-09-29 | 深圳市汇顶科技股份有限公司 | Burr detection circuit |
| CN110442073A (en) * | 2019-08-30 | 2019-11-12 | 四川腾盾科技有限公司 | A kind of redundance Aircraft Management Computer MIO board channel fault logic judgment method |
| CN110442073B (en) * | 2019-08-30 | 2020-07-10 | 四川腾盾科技有限公司 | Logical judgment method for redundant airplane management computer MIO board channel fault |
| CN110737234A (en) * | 2019-10-21 | 2020-01-31 | 江苏云涌电子科技股份有限公司 | internal network safety monitoring device |
| CN110737234B (en) * | 2019-10-21 | 2021-04-13 | 江苏云涌电子科技股份有限公司 | Intranet safety monitoring device |
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Open date: 20100804 |