CN203858624U - Dual-backup type bus watchdog circuit - Google Patents
Dual-backup type bus watchdog circuit Download PDFInfo
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- CN203858624U CN203858624U CN201420289198.5U CN201420289198U CN203858624U CN 203858624 U CN203858624 U CN 203858624U CN 201420289198 U CN201420289198 U CN 201420289198U CN 203858624 U CN203858624 U CN 203858624U
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Abstract
The utility model discloses a dual-backup type bus watchdog circuit. The dual-backup type bus watchdog circuit comprises a first watchdog chip, a second watchdog chip and a reset/automatic switch module. A pin of the first watchdog chip and a pin of the second watchdog chip are connected with a single-chip microcomputer through an address bus, a control bus and a data bus. The reset/automatic switch module is connected with the first watchdog chip, the second watchdog chip and the single-chip microcomputer. According to the dual-backup type bus watchdog circuit, bus detection can be achieved, a watchdog self-checking link is added, and leakproofness of the watchdog circuit is improved; meanwhile, when the first watchdog chip or the second watchdog chip fails, the normal watchdog chip is switched into through the reset/automatic switch module so as to reset the single-chip microcomputer, the 'failure-to-operation' purpose is achieved, reliability of an electronic system is improved, and the dual-backup type bus watchdog circuit is suitable for application occasions with high reliability requirements.
Description
Technical field
The utility model relates to a kind of watchdog circuit, relates in particular to a kind of double copies formula bus watchdog circuit.
Background technology
At present common house dog design is that an input and output pin of watchdog chip and single-chip microcomputer is connected, by programmed control, it periodically sends into height (low) level to this input and output pin of single-chip microcomputer on this pin of watchdog chip, once single-chip microcomputer, cause program fleet for a certain reason and be absorbed in dead cruising condition, the program of writing house dog pin just can not be performed, this time, watchdog circuit will be due to the signal that can not get single-chip microcomputer and send here, to reset pin, send a reset signal, single-chip microcomputer is resetted, be that single-chip microcomputer starts to carry out from the reference position of program storage, realized automatically reseting of single-chip microcomputer.But, because the input and output pin by single is fed dog, cannot check the Welding Problems of monolithic power traction pin, more cannot coordinate carrying out smoothly of single-chip microcomputer self-checking function, and when house dog was lost efficacy, system has just lost automatically reset ability forever.
Utility model content
The purpose of this utility model is, by a kind of double copies formula bus watchdog circuit, to solve the problem that above background technology is partly mentioned.
For reaching this object, the utility model by the following technical solutions:
A double copies formula bus watchdog circuit, it comprises the first watchdog chip, the second watchdog chip and reset/automatic switching module; Wherein, the pin of described the first watchdog chip and the second watchdog chip is connected single-chip microcomputer by address bus, control bus, data bus; Described reset/automatic switching module is connected with the first watchdog chip, the second watchdog chip, single-chip microcomputer, for when the first watchdog chip and the arbitrary inefficacy of the second watchdog chip, switches the normal watchdog chip described single-chip microcomputer that resets.
The double copies formula bus watchdog circuit tool that the utility model provides has the following advantages: one, can carry out bus detection, increase house dog self check link, improve the tightness of watchdog circuit.Single-chip microcomputer is write specific data toward corresponding address register, detects the correctness of address bus, data bus line.And, detecting after the correctness of line, single-chip microcomputer is opened arbitrary watchdog chip, does not but deliberately feed dog, if watchdog chip can overtime reset single-chip microcomputer, illustrate that watchdog chip can normally work, and just continues afterwards other codes of execution.The double watchdogs redundancy design that two, can automatically switch is realized " fault-work ", has increased the reliability of electronic system, adapts to the application scenario of high reliability request.In the first watchdog chip and the second watchdog chip, during arbitrary inefficacy, reset/automatic switching module switches the work that normal watchdog chip completes the described single-chip microcomputer that resets.
Accompanying drawing explanation
The double copies formula bus watchdog circuit structural drawing that Fig. 1 provides for the utility model embodiment;
The timing diagram of the watchdog chip input/output signal that Fig. 2 provides for the utility model embodiment;
The watchdog chip structured flowchart that Fig. 3 provides for the utility model embodiment;
The state conversion schematic diagram of the state modular converter that Fig. 4 provides for the utility model embodiment;
The configurable counter module structured flowchart that Fig. 5 provides for the utility model embodiment;
The number of resets that Fig. 6 provides for the utility model embodiment is overflowed modular structure block diagram;
The channel switching module switching schematic diagram that Fig. 7 provides for the utility model embodiment.
Embodiment
Below in conjunction with drawings and Examples, the utility model is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the utility model, but not to restriction of the present utility model.It also should be noted that, for convenience of description, in accompanying drawing, only show the part relevant to the utility model but not full content.
Please refer to shown in Fig. 1 the double copies formula bus watchdog circuit structural drawing that Fig. 1 provides for the utility model embodiment.
In the present embodiment, double copies formula bus watchdog circuit specifically comprises the first watchdog chip 101, the second watchdog chip 102 and reset/automatic switching module 103.
The pin of described the first watchdog chip 101 and the second watchdog chip 102 is connected single-chip microcomputer 107 by address bus 104, control bus 105, data bus 106.
Described reset/automatic switching module 103 is connected with the first watchdog chip 101, the second watchdog chip 102, single-chip microcomputer 107, for when the first watchdog chip 101 and the arbitrary inefficacy of the second watchdog chip 102, switch the normal watchdog chip described single-chip microcomputer 107 that resets.Concrete, after the normal work of system, if one of them inefficacy in the first watchdog chip 101 and the second watchdog chip 102, by reset/automatic switching module 103, the power of reset single-chip microcomputer 107 is switched to normally functioning that watchdog chip, realize the redundancy design of " fault-work ", the reliability of the normal work of increase system.
In order to ensure the first watchdog chip 101, the second watchdog chip 102, can normally work, the work that first will do is exactly the correctness that detects the pin line of single-chip microcomputer 107 and watchdog chip self check.Single-chip microcomputer 107 is write specific data toward corresponding address register, detects the correctness (for example write continuously data 0x5555 and 0xAAAA, every data line all can be traveled through) of address bus 104, data bus 106 lines.Detect after the correctness of line, single-chip microcomputer 107 is opened the first watchdog chip 101, the second watchdog chip 102, does not but deliberately feed dog, if the overtime reset single-chip microcomputer 107 of watchdog chip energy, illustrate that watchdog chip can normally work, just continue to carry out afterwards other codes.
Concrete, in the present embodiment, the main input/output signal of described the first watchdog chip 101 and the second watchdog chip 102 is as shown in the table:
The sequential relationship of the first watchdog chip 101 and the second watchdog chip 102 input/output signals as shown in Figure 2.In Fig. 2, the concrete meaning of each signal is as follows:
Powered: input, system is under-voltage power-on reset signal.During low level, whole watchdog chip resets; Invalid during high level.
State: output, house dog condition indicative signal.During low level, expression system is in self check and init state, and during high level, expression system is in periodic duty state.
Reset: output, watchdog reset MCU signal.Low level is invalid; During high level, reset MCU.
Overflow: output, watchdog reset counter overflow signal.During low level, represent that watchdog reset number of times accumulative total surpasses the upper limit, is about to switch to subaisle; During high level, represent that this passage is still main channel.
Channel: output, by overflow and the coefficient master/subaisle of state signal switching signal.During low level, this passage switches to subaisle; High level represents that this passage is still main channel.
The feature of analyzing house dog is known, in the present embodiment, watchdog chip 101 and the second watchdog chip 102 can adopt finite state machine design, and it comprises that state modular converter, single-chip microcomputer write that action sign generation module, address data bus decoding module, configurable counter module, reset single-chip microcomputer number of times statistical counter module, reset signal generation module, number of resets overflow module, house dog freezes module and channel switching module forms.Watchdog chip 101 and the second watchdog chip 102 structured flowcharts are as shown in Figure 3.
Analyze house dog designing requirement, design a coding finite state machine with 12 kinds of states.State machine transition diagram is illustrated in fig. 4 shown below.In figure, each state description is as follows:
State S0: after system powers on, state machine enters original state S0, and when next clock arrives, unconditionally forward state S1 to.State S1: watchdog reset single-chip microcomputer timer, the time is relevant to single-chip microcomputer used.State S2: house dog internal counter initialization.State S3: configuration house dog overtime reset time.State S4: house dog internal counter initialization.State S5: house dog internal counter subtracts counting.State S6: house dog internal counter initialization.State S7: single-chip microcomputer is fed dog for the first time to house dog.State S8: single-chip microcomputer is fed dog for the second time to house dog.State S9: house dog internal counter initialization.State S10: number of resets counter increases counting or subtracts counting.State S11: watchdog reset single-chip microcomputer.
Single-chip microcomputer is write action sign in the inner generation of house dog, as a state transition condition of state machine.This signal is drawn from the pin of chip simultaneously, meet the needs of system testing.Whenever single-chip microcomputer is write data toward address register, in watchdog chip, will produce a single-chip microcomputer and write action sign, normality remains low level; Whenever single-chip microcomputer is once write action, single-chip microcomputer is write action sign production module will produce the high level of a clock period.
Address data bus decoding module is translated into two bit codes by the value on corresponding address bus and data bus, as shown in the table:
Configurable counter module can configure by software, and concrete Configuration Values is with definite according to the singlechip interruption time.The in the situation that of software upgrading, can not need to change hardware by the value upgrade-system of configure interrupt task timer, for software upgrading later offers convenience.The structured flowchart of configurable counter module as shown in Figure 5.
The initial value of reset single-chip microcomputer number of times statistical counter module is 0.When watchdog reset single-chip microcomputer, reset single-chip microcomputer number of times statistical counter module will increase 1; Every 15 minutes, single-chip microcomputer can make again this counter subtract 1.It is to realize by writing predetermined value toward predetermined counter that single-chip microcomputer makes this counter subtract 1.It is because just think that it is to allow that system broke down in 15 minutes during design that every 15 minutes single-chip microcomputers can initiatively make this counter subtract 1.
Effective during watchdog reset signal high level, single-chip microcomputer resets during high level.Watchdog reset signal is effective when number of resets statistical counter does not overflow; If overflowed, reset signal keeps low level.
Number of resets is overflowed module and is realized by a holding circuit.Rough schematic view is illustrated in fig. 6 shown below.The initial value of overflow indicator is 1, and the input signal initial value of high order end is 0.When if number of resets does not reach the maximal value of permission, the input signal of module is 0 always, and non-return signal is in front of the door also 0, so or door output signal be still 0, it is high level that overflow indicator remains 1; If when number of resets has reached the maximal value allowing, the input signal of module becomes 1, or a door output signal becomes 1, and overflow indicator becomes 0 by 1 is low level and irreversible, and after this overflow indicator remains low level always.
House dog is freezed module can produce a house dog freeze flag.Low level represents that electronic system is in self check state; High level represents that electronic system is in periodic duty.After electronic system powers on, house dog freeze flag is set to low level, and house dog coordinates single-chip microcomputer self check simultaneously; After self check finishes, single-chip microcomputer is set to high level by the bit7 pin of data bus by house dog freeze flag, represents that single-chip microcomputer is in periodic duty.If after operational process in, single-chip microcomputer cannot be in time fed dog for a certain reason, house dog is by reset single-chip microcomputer, Single Chip Microcomputer (SCM) program starts anew to carry out, house dog freeze flag, from being newly set to low level, so moves in circles.
The input signal of channel switching module is channel switching signal channelA and the channelB of two passages, output signal is channel selecting signal switch, and the Chip Microcomputer A group output signal of two passage outputs and single-chip microcomputer B group output signal are carried out to the selectivity output of alternative.Wherein, it is main channel that switch=0 represents to select A channel, and B passage is secondary channels; It is main channel that switch=1 represents to select B passage, and A channel is secondary channels.If the number of resets in house dog is overflowed, channel switching signal is low level, and this passage is abandoned forever; If the number of resets in house dog is not overflowed, the height of channel switching signal level is determined by house dog freeze flag.When electronic system has just started, the channel switching signal of two passages is high level.First the passage that first sends handshake becomes main channel, and another is in Hot Spare state.During main channel allows, cannot feed dog or other make the situation of watchdog reset single-chip microcomputer if occur, channel switching signal can become low level: (1) temporarily becomes subaisle when prepass, and another passage in Hot Spare state becomes main channel.(2) after current channel reset, from new startup, enter in self check, periodic duty, in Hot Spare state simultaneously.Major-minor passage so moves in circles, until a certain channel reset number of times overflows, causes being activated, even whole electronic system paralysis.The mode bit of passage switching state machine forms (channelA, channelB) by the channel switching signal of two passages, and state machine as shown in Figure 7.Attention: 1. suppose that first A channel shake hands herein, so while entering 11 state at first, A channel is main channel.2. to make system normally work, in A, B passage, have a passage at least normally, so two passages are all abnormal when state is 00, represent that two passages all cannot work, systemic breakdown.By following form, can clearly find out the channel switching signal of module input and the relation of output signal and corresponding main channel.
The technical solution of the utility model tool has the following advantages: one, can carry out bus detection, increase house dog self check link, improve the tightness of watchdog circuit.Single-chip microcomputer is write specific data toward corresponding address register, detects the correctness of address bus, data bus line.And, detecting after the correctness of line, single-chip microcomputer is opened arbitrary watchdog chip, does not but deliberately feed dog, if watchdog chip can overtime reset single-chip microcomputer, illustrate that watchdog chip can normally work, and just continues afterwards other codes of execution.The double watchdogs redundancy design that two, can automatically switch is realized " fault-work ", has increased the reliability of electronic system, adapts to the application scenario of high reliability request.In the first watchdog chip and the second watchdog chip, during arbitrary inefficacy, reset/automatic switching module switches the work that normal watchdog chip completes the described single-chip microcomputer that resets.In addition, design configurable counter module and make can revise house dog when software upgrading, for software upgrading later offers convenience.Design reset single-chip microcomputer number of times statistical counter module and number of resets are overflowed module, make the single-chip microcomputer number of times that is reset have a maximum limit, and reliability control system is higher.
Note, above are only preferred embodiment of the present utility model and institute's application technology principle.Skilled person in the art will appreciate that the utility model is not limited to specific embodiment described here, can carry out for a person skilled in the art various obvious variations, readjust and substitute and can not depart from protection domain of the present utility model.Therefore, although the utility model is described in further detail by above embodiment, but the utility model is not limited only to above embodiment, in the situation that not departing from the utility model design, can also comprise more other equivalent embodiment, and scope of the present utility model is determined by appended claim scope.
Claims (1)
1. a double copies formula bus watchdog circuit, is characterized in that, comprises the first watchdog chip, the second watchdog chip and reset/automatic switching module; Wherein, the pin of described the first watchdog chip and the second watchdog chip is connected single-chip microcomputer by address bus, control bus, data bus; Described reset/automatic switching module is connected with the first watchdog chip, the second watchdog chip, single-chip microcomputer, for when the first watchdog chip and the arbitrary inefficacy of the second watchdog chip, switches the normal watchdog chip described single-chip microcomputer that resets.
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| CN201420289198.5U CN203858624U (en) | 2014-05-30 | 2014-05-30 | Dual-backup type bus watchdog circuit |
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| CN201420289198.5U CN203858624U (en) | 2014-05-30 | 2014-05-30 | Dual-backup type bus watchdog circuit |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104484237A (en) * | 2014-12-12 | 2015-04-01 | 北京控制工程研究所 | Three-machine hot backup computer watchdog reset realization method and reset circuit |
| CN106354596A (en) * | 2016-09-26 | 2017-01-25 | 积成电子股份有限公司 | Method for checking whether external watchdog chip works normally |
| CN108958988A (en) * | 2018-06-13 | 2018-12-07 | 中国北方发动机研究所(天津) | A kind of minimum SCM system with redundant reset and redundancy control capability |
| CN110457158A (en) * | 2019-08-16 | 2019-11-15 | 深圳市智微智能软件开发有限公司 | House dog implementation method, device, equipment and storage medium based on finite state machine |
| CN110727529A (en) * | 2019-09-06 | 2020-01-24 | 深圳市智微智能科技开发有限公司 | Watchdog resetting method and system |
| CN112650093A (en) * | 2020-09-25 | 2021-04-13 | 合肥恒烁半导体有限公司 | Digital reset circuit applied to MCU chip |
-
2014
- 2014-05-30 CN CN201420289198.5U patent/CN203858624U/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104484237A (en) * | 2014-12-12 | 2015-04-01 | 北京控制工程研究所 | Three-machine hot backup computer watchdog reset realization method and reset circuit |
| CN104484237B (en) * | 2014-12-12 | 2017-06-27 | 北京控制工程研究所 | A kind of three machine Hot Spare computer watchdog reset implementation methods and reset circuit |
| CN106354596A (en) * | 2016-09-26 | 2017-01-25 | 积成电子股份有限公司 | Method for checking whether external watchdog chip works normally |
| CN108958988A (en) * | 2018-06-13 | 2018-12-07 | 中国北方发动机研究所(天津) | A kind of minimum SCM system with redundant reset and redundancy control capability |
| CN110457158A (en) * | 2019-08-16 | 2019-11-15 | 深圳市智微智能软件开发有限公司 | House dog implementation method, device, equipment and storage medium based on finite state machine |
| CN110727529A (en) * | 2019-09-06 | 2020-01-24 | 深圳市智微智能科技开发有限公司 | Watchdog resetting method and system |
| CN112650093A (en) * | 2020-09-25 | 2021-04-13 | 合肥恒烁半导体有限公司 | Digital reset circuit applied to MCU chip |
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