CN103389914B - Based on the spaceborne triple-modular redundancy system of Clock Synchronization Technology - Google Patents
Based on the spaceborne triple-modular redundancy system of Clock Synchronization Technology Download PDFInfo
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Abstract
The invention discloses a kind of spaceborne triple-modular redundancy system, comprising: three module isomorphism microprocessor modules, clock synchronization module, redundancy judging module, schema management module, its core technology is Clock Synchronization Technology.Clock synchronization module can be divided into synchronous loading start unit and high precision clock alignment module, the running status of the multistage counting unit monitoring microprocessor realized by FPGA also obtains its asynchronous side-play amount, and makes three be in the state of synchronous operation by the incoming frequency of adjustment three module isomorphism microprocessor module and retention time.This system is mainly used in skin satellite carried computer system, and synchronization accuracy can up to 10 nanosecond orders, highly versatile, effectively can improve the reliability of board computer system.
Description
Technical field
The present invention relates to a kind of triple-modular redundancy system, particularly relate to the spaceborne triple-modular redundancy system based on Clock Synchronization Technology.
Background technology
Skin satellite refers to the microsatellite of weight range at 1 ~ 10Kg, compare conventional satellite, skin satellite broadly adopts MNT(Micro-Nano Technology, micro & nano technology) and MEMS(MicroElectronic Mechanical System, Micro Electro Mechanical System) etc. new and high technology, functional density is high, lead time is short, cost is low, and volume is little, lightweight.
Spacecraft is in all the time when space flight among the radiation environment of charged particle.In this radiation environment, microprocessor may cause function to interrupt even losing because of single-particle disturbance, thus leads to disastrous consequence.Cause this serious problems mainly total radiation dose effect and single particle effect, single particle effect is divided into again SEU(Signal Event Upset, single-particle inversion) and SEL(Signal EventLatch-up, single event latchup) 2 aspects.Single event upset effecf can cause a certain position in the storage unit of digital circuit to overturn because being interfered, thus cause the change storing content, also can introduce an of short duration pulse in the output of combinational logic circuit, be the main cause causing microprocessor operational failure at present.In skin satellite carried computer system, microprocessor carries the important process such as the management of satellite Star Service, instruction transmitting-receiving, data acquisition, computing and process, the stable Stability and dependability index with reliably directly affecting whole star of its performance, therefore carries out fault-tolerant design to spaceborne computer and is necessary.
Triplication redundancy technology is a kind of to the effective fault-tolerant technique of single-particle inversion, greatly can improve the reliability of circuit.Its basic thought is for the identical module of solid CMOS macro cell 2 to be added, then is exported by majority voting, even if there is the module system that breaks down still can normally work like this.The basis that triple-modular redundancy system realizes is that guarantee 3 module synchronization run, and therefore simultaneous techniques is the key realizing triple-modular redundancy system.Simultaneous techniques is divided into again clock synchronous and tasks synchronization 2 kinds of modes.
At present, domestic and international spaceborne triple-modular redundancy system many employings tasks synchronization technology, compare Clock Synchronization Technology, its deficiency is: (1) synchronous degree of accuracy is relatively low.Synchronization levels is that function level is synchronous, and clock synchronous can to reach instruction-level synchronous; (2) versatility is poor.Tasks synchronization only can adapt to the triple-modular redundancy system under appointed function demand; (3) higher to software requirement, take software ample resources.
Summary of the invention
The invention provides the spaceborne triple-modular redundancy system based on Clock Synchronization Technology, adopt Clock Synchronization Technology, this system improves synchronous degree of accuracy, highly versatile, effectively can improve the reliability of board computer system.
Based on a spaceborne triple-modular redundancy system for Clock Synchronization Technology, it is characterized in that, described spaceborne triple-modular redundancy system comprises three module isomorphism microprocessor modules, redundancy judging module, schema management module and clock synchronization module; Described three module isomorphism microprocessor modules comprise 3 DSP, and described clock synchronization module comprises level synchronization decision unit, secondary synchronization decision unit, clock alignment unit, synchronously loads start unit;
Described Clock Synchronization Technology comprises the steps:
Step S1,3 DSP described in described synchronous loading start unit synchronous averaging, described 3 DSP timing outputs 3 square-wave signals are to described level synchronization decision unit;
Step S2, described level synchronization decision unit counts the rising edge of described 3 square-wave signals, obtain the one-level count value of each square-wave signal and the level synchronization marking signal of correspondence, one-level count value is inputted described secondary synchronization decision unit, and at the rising edge of each square-wave signal, the level synchronization marking signal of correspondence is inputted described secondary synchronization decision unit;
Step S3, in described level synchronization decision unit, with one of them one-level count value for benchmark, described 3 one-level count values are all identical then synchronous, the output data of described 3 DSP are sent to described redundancy judging module, put to the vote by the signal condition of described redundancy judging module to described output data, export the correct result after voting, described schema management module counts for the situation that the signal condition that exports data described in described redundancy judging module is different, obtains the count value that signal condition is different; If at least one is different from the one-level count value as benchmark, then asynchronous for other 2 one-level count values, judge asynchronous side-play amount by described secondary synchronization decision unit;
Step S4, described secondary synchronization decision unit calculates described asynchronous side-play amount according to the level synchronization marking signal of input, described asynchronous side-play amount is inputted described clock alignment unit, the asynchronous DSP of described clock alignment unit corresponding to described asynchronous offset calibration;
Step S5, described secondary synchronization decision unit counts asynchronous number of times according to the one-level count value of input, obtains asynchronous count value, described asynchronous count value is inputted described schema management module;
Step S6, in described schema management module setting threshold value, when described asynchronous count value exceedes described threshold value, makes corresponding DSP enter fault mode, and handling failure; The count value that described signal condition is different exceedes described threshold value, also makes DSP corresponding to described signal enter fault mode, and handling failure.
Modules in the spaceborne triple-modular redundancy system of the present invention by FPGA(Field ProgrammableGate Array, field programmable gate array) realize.
In described step S3, described redundancy judging module adopts 3 to get 2 majority voting and obtains correct result.Redundancy judging module adopts 3 to get the reliability that 2 majority voting modes can improve system.
In described step S4, described clock alignment unit adjusts the retention time of asynchronous DSP incoming frequency and described incoming frequency according to described asynchronous side-play amount, to calibrate described asynchronous DSP.Wherein clock calibration module inserts multiple phaselocked loop IP kernel for exporting the incoming frequency of multi-frequency as DSP by FPGA, and determines an optimal frequency retention time, calibrates asynchronous DSP with this.
In described step S6, described schema management module carrys out handling failure by the DSP of reset fault mode.There is interface in schema management module and power-supply system and DSP, after DSP enters fault mode, by carrying out power-off restarting or direct enable DSP reset signal pin to the DSP of fault mode, reset this DSP, and System recover is normally worked.
In described step S6, described schema management module is passed through in three mould patterns, is independently switched between two mould patterns and single mode, falls the described spaceborne triple-modular redundancy system of mould operation in a failure mode and carrys out handling failure.Schema management module ensures isolation of system fault and long-play by falling mould process.
Compared with prior art, the present invention has following useful technique effect:
The Clock Synchronization Technology that the spaceborne triple-modular redundancy system of the present invention adopts, synchronous compared to the function level of tasks synchronization technology, it is synchronous that synchronization accuracy can be promoted to instruction-level by Clock Synchronization Technology, greatly improves its synchronization accuracy.
The Clock Synchronization Technology that the spaceborne triple-modular redundancy system of the present invention adopts, compared to tasks synchronization technology, its versatility is higher, compensate for the weakness that triple-modular redundancy system portability is in the past poor, be only applicable to determine functional requirement system.
The spaceborne triple-modular redundancy system of the present invention has schema management module, and adopt adhesive logic FPGA to carry out expanding, check, manage, all software and hardware resources all meet war products one-level derate standard, add itself reliability and processing power, and dirigibility extensibility.
Rely on programming logic gate array FPGA, system operations speed is fast, efficient solution can soften part, improves software work efficiency.
Be equipped on microsatellite, Primary Component all adopts low-power chip, overcomes the weakness that triple-modular redundancy system power consumption is larger in the past.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the spaceborne triple-modular redundancy system of the present invention;
Fig. 2 is the schematic diagram of clock synchronization module of the present invention;
Fig. 3 is that the present invention synchronously loads start-up operation process flow diagram;
Fig. 4 is the operational flowchart of high precision clock alignment module of the present invention;
Fig. 5 is the operational flowchart of schema management module of the present invention.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail.
Fig. 1 is the schematic diagram of the spaceborne triple-modular redundancy system of the present invention, comprising: three module isomorphism microprocessor modules, clock synchronization module, redundancy judging module, schema management module, interfacing expansion module.Three module isomorphism microprocessor modules are connected with clock synchronization module, schema management module; Clock synchronization module is connected with redundancy judging module, schema management module; Redundancy judging module is connected with interfacing expansion module and schema management module.
The modules of spaceborne triple-modular redundancy system realizes by FPGA.
Three module isomorphism microprocessor modules are made up of 3 isomorphism low-power consumption DSP, its outside exented memory selects 2 capacity to be the SDRAM of 256Mb, input clock both can be provided by 24MHz crystal oscillator, also can input homology V-CLK by FPGA, all designs comprise its supply module on hardware, all keep highly consistent.Three module isomorphism microprocessor modules send instruction, operation result to FPGA by EMIFA interface, receive the data that FPGA gathers from each subsystem simultaneously; Design interrupt priority level administration module, responds each road external interrupt by GPIO interface; After choosing DSP loading mode, by general SPI interface for loading dsp software program; In addition, GPIO interface timing output synchronous square-wave signal is used for the high precision alignment of clock synchronization module.Three module isomorphism microprocessor modules are as the master devices of triple-modular redundancy system, and this module is mainly used in realizing the functions such as the management of skin satellite Star Service, instruction transmitting-receiving, data acquisition, computing, process, and coordinates clock synchronization module to realize instruction-level clock synchronous.
Clock synchronization module is the improvement part of the spaceborne triple-modular redundancy system of the present invention, and its synchronization accuracy directly affects the accuracy of redundancy judging module.As shown in Figure 2, clock synchronization module can be divided into synchronous loading start unit and high precision clock alignment module two parts, and wherein high precision clock alignment module is made up of level synchronization decision unit, secondary synchronization decision unit and clock alignment unit.
The operating process of synchronous loading start unit as shown in Figure 3.First, use loading DSP, by same program programming to a 3 isomorphism Flash, after choosing DSP loading mode, power-off restarting.The implementation method of synchronous loading start unit is as follows:
(1) 3 DSP loads successively;
(2) loading Success Flag is exported to FPGA;
(3) enter Idle pattern and wait for external interrupt wakeup;
(4) 3 DSP receive the external interrupt from FPGA simultaneously;
(5) in outside interrupt processing function, output wakes Success Flag up to FPGA;
(6) normal mode of operation is entered.
High precision clock alignment module operation flow process as shown in Figure 4.First, level synchronization decision unit is realized in FPGA by 3 level synchronization counters, and 3 level synchronization counters receive synchronous square-wave signal from 3 DSP respectively.At the rising edge of each synchronous square wave, synchronous counter adds 1, exports an one-level count flag signal to next stage synchronization decisions unit simultaneously.
Then, with synchronous counter corresponding to DSP1 for benchmark, if the count value of 3 level synchronization counters is all identical, then directly enters redundancy judging module and carry out 3 and get 2 majority votes and export; If the count value of the synchronous counter that the count value of other any 1 synchronous counter is corresponding with DSP1 is not identical, then judges that the DSP that this synchronous counter is corresponding is asynchronous, enter secondary synchronization decision unit.
Secondary synchronization decision unit is realized in FPGA by 2 secondary synchronization counters.With the level synchronization marking signal of DSP1 for benchmark, in the time interval between another two level synchronization marking signals, the system clock rising edge of FPGA being sampled, exporting to clock alignment unit by calculating asynchronous side-play amount.Meanwhile, secondary synchronization decision unit is added up nonsynchronous number of times, exports asynchronous count value to schema management module, if more than a given threshold, then schema management module is carried out fault recovery to corresponding DSP, fallen the process such as mould; If asynchronous number of times does not exceed threshold value, then enter level synchronization decision unit, continue to judge whether 3 DSP are in synchronous regime.
Finally, first clock alignment unit can insert multiple phaselocked loop IP kernel for exporting multi-frequency by FPGA, needs in addition to determine an optimal frequency retention time.According to the asynchronous side-play amount obtained, clock alignment unit adjusts the incoming frequency of corresponding DSP, thus reaches the object of 3 DSP synchronous operations.
Redundancy judging module realizes with 3 shift registers in FPGA.After clock synchronization module calibration, 3 DSP synchronous operations, it exports data and pass to interfacing expansion module after 3 gets 2.
Schema management module has been mainly used in the conversion when house keeping computer mode of operation, and it needs design 2 monitor counters in FPGA, for counting the out of step conditions of DSP2 and DSP3; In addition, also need separately to design 3 counters, the situation that the output signal for recording DSP is different from all the other.
First under normal circumstances, Star Service counter is in triplication redundancy clock synchronization module, if the asynchronous Count of Status value of certain DSP exceedes given threshold, then house keeping computer enters fault mode; If 2 DSP are different for the output of certain DSP and all the other, and its different number of times also exceedes given threshold, then house keeping computer enters fault mode equally.
After house keeping computer enters fault mode, the corresponding DSP of reseting signal reset can be sent by FPGA, also can be cut off the power supply of corresponding DSP by power management module, thus fall mould to 2 mould backup mode or single mode.
The interfacing expansion module of house keeping computer is by general SPI, I
2c, UART interface are connected with subsystems such as skin Satellite TT subsystem, appearance control subsystem, load subsystem, rail control subsystem, thermal control subsystems, the sequence of operations such as data acquisition, instruction transmission.
This spaceborne triple-modular redundancy system is mainly used in skin satellite carried computer system, and synchronization accuracy can up to 10 nanosecond orders, highly versatile, effectively can improve the reliability of board computer system.
Claims (5)
1. based on a spaceborne triple-modular redundancy system for Clock Synchronization Technology, it is characterized in that, described spaceborne triple-modular redundancy system comprises three module isomorphism microprocessor modules, redundancy judging module, schema management module and clock synchronization module; Described three module isomorphism microprocessor modules comprise 3 DSP, and described clock synchronization module comprises level synchronization decision unit, secondary synchronization decision unit, clock alignment unit, synchronously loads start unit;
Described Clock Synchronization Technology comprises the steps:
Step S1,3 DSP described in described synchronous loading start unit synchronous averaging, described 3 DSP timing outputs 3 square-wave signals are to described level synchronization decision unit;
Step S2, described level synchronization decision unit counts the rising edge of described 3 square-wave signals, obtain the one-level count value of each square-wave signal and the level synchronization marking signal of correspondence, one-level count value is inputted described secondary synchronization decision unit, and at the rising edge of each square-wave signal, the level synchronization marking signal of correspondence is inputted described secondary synchronization decision unit;
Step S3, in described level synchronization decision unit, with one of them one-level count value for benchmark, described 3 one-level count values are all identical then synchronous, the output data of described 3 DSP are sent to described redundancy judging module, put to the vote by the signal condition of described redundancy judging module to described output data, export the correct result after voting, described schema management module counts for the situation that the signal condition that exports data described in described redundancy judging module is different, obtains the count value that signal condition is different; If at least one is different from the one-level count value as benchmark, then asynchronous for other 2 one-level count values, judge asynchronous side-play amount by described secondary synchronization decision unit;
Step S4, described secondary synchronization decision unit calculates described asynchronous side-play amount according to the level synchronization marking signal of input, described asynchronous side-play amount is inputted described clock alignment unit, the described clock alignment unit asynchronous DSP that asynchronous side-play amount is corresponding according to described asynchronous offset calibration;
Step S5, described secondary synchronization decision unit counts asynchronous number of times according to the one-level count value of input, obtains asynchronous count value, described asynchronous count value is inputted described schema management module;
Step S6, in described schema management module setting threshold value, when described asynchronous count value exceedes described threshold value, makes DSP corresponding to described asynchronous count value enter fault mode, and handling failure; The count value that described signal condition is different exceedes described threshold value, also makes DSP corresponding to described signal enter fault mode, and handling failure.
2. as claimed in claim 1 based on the spaceborne triple-modular redundancy system of Clock Synchronization Technology, it is characterized in that, in described step S3, described redundancy judging module adopts 3 to get 2 majority voting and obtains correct result.
3. as claimed in claim 1 based on the spaceborne triple-modular redundancy system of Clock Synchronization Technology, it is characterized in that, in described step S4, described clock alignment unit adjusts the incoming frequency of asynchronous DSP and the retention time of described incoming frequency according to described asynchronous side-play amount, to calibrate described asynchronous DSP.
4. as claimed in claim 1 based on the spaceborne triple-modular redundancy system of Clock Synchronization Technology, it is characterized in that, in described step S6, described schema management module carrys out handling failure by the DSP of reset fault mode.
5. as claimed in claim 1 based on the spaceborne triple-modular redundancy system of Clock Synchronization Technology, it is characterized in that, in described step S6, described schema management module is passed through in three mould patterns, is independently switched between two mould patterns and single mode, falls the described spaceborne triple-modular redundancy system of mould operation in a failure mode and carrys out handling failure.
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| CN104062923B (en) * | 2014-07-01 | 2016-11-02 | 中国科学院长春光学精密机械与物理研究所 | Space flight multichannel TDICCD camera synchronous method |
| CN104182304A (en) * | 2014-08-12 | 2014-12-03 | 西北工业大学 | Universal multi-mode redundant pico/nano satellite on-board computer system |
| CN106533601A (en) * | 2016-10-27 | 2017-03-22 | 中国电子科技集团公司第三十二研究所 | Method for clock synchronization in modular redundancy system |
| CN107239433A (en) * | 2017-06-06 | 2017-10-10 | 上海航天控制技术研究所 | A kind of triple redundance computer synchronous method |
| CN108762828B (en) * | 2018-04-24 | 2021-11-16 | 桂林长海发展有限责任公司 | DSP multi-core array secondary starting method and device |
| CN109828449A (en) * | 2019-01-25 | 2019-05-31 | 杭州电子科技大学 | A kind of triplication redundancy control calculating voting system and method |
| JP7439474B2 (en) * | 2019-11-25 | 2024-02-28 | 富士電機株式会社 | Programmable controller systems and modules |
| CN111176890B (en) * | 2019-12-16 | 2023-09-05 | 上海航天控制技术研究所 | Satellite-borne software data storage and anomaly recovery method |
| CN111431651B (en) * | 2020-03-04 | 2021-12-07 | 上海航天控制技术研究所 | Multicomputer synchronous operation and time alignment method suitable for Mars detection |
| CN111538369B (en) * | 2020-04-17 | 2021-09-24 | 北京中科宇航技术有限公司 | Triple-modular redundancy computer clock synchronization method and system |
| CN113132045A (en) * | 2021-03-25 | 2021-07-16 | 井芯微电子技术(天津)有限公司 | Clock synchronization method of redundancy system, redundancy system and network system |
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