CN107678532A - A kind of low-power dissipation SOC wake module and low-power dissipation SOC - Google Patents
A kind of low-power dissipation SOC wake module and low-power dissipation SOC Download PDFInfo
- Publication number
- CN107678532A CN107678532A CN201710986284.XA CN201710986284A CN107678532A CN 107678532 A CN107678532 A CN 107678532A CN 201710986284 A CN201710986284 A CN 201710986284A CN 107678532 A CN107678532 A CN 107678532A
- Authority
- CN
- China
- Prior art keywords
- wake
- module
- signal
- soc
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
This application discloses a kind of low-power dissipation SOC wake module and low-power dissipation SOC, the wake module includes wake source acquisition module, register configuration module, asks generation module；Wherein, wake source acquisition module is connected with register configuration module, and the wake-up for acquisition chip PIN or chip internal real-time clock encourages, and output makes the first in running order signals of SOC；Register configuration module is used to receive the first signal, and being sent after processing and to request generation module makes the in running order corresponding state configuration information of off working state module in SOC；Off working state module is connected with wake module；Request generation module is corresponding with state configuration information for receiving, generating, and makes interruption/wake request that off working state module is in running order, and is respectively sent to corresponding off working state module, SOC is entered normal operating conditions.For the application by the way that the circuit power for not needing work is closed, it is necessary to open circuit power when working, realization reduces SOC power consumption.
Description
Technical field
The present invention relates to electronic circuit field, more particularly to a kind of low-power dissipation SOC wake module and low-power dissipation SOC.
Background technology
With the rapid development of electronic technology, the electronic product such as application of mobile phone, computer electronic product in life is got over
Come more universal.And these electronic products require the power-on time of battery more and more higher, when high power consumption turns into restriction battery use
Between key constraints.Electronic product chip manufacture generally use SOC technologies (SOC, System on Chip, it is system-level
Chip), SOC technologies can be such that all processing components are integrated on one single chip.Due to containing more part in SOC,
Its power consumption can be completely converted into heat energy, raise chip operating temperature, and the rise of temperature can make silicon materials fail, and cause chip
Reliability decrease, it is seen then that high power consumption can influence SOC reliability, and people can not be met to the longer power-on time of electronic product
Requirement, and then restrict electronic product development.
Therefore how to realize that the power consumption for reducing SOC is those skilled in the art's urgent problem to be solved.
The content of the invention
In view of this, it is an object of the invention to provide a kind of low-power dissipation SOC wake module and above-mentioned wake module is included
Low-power dissipation SOC, realize reduce SOC power consumptions effect.Its concrete scheme is as follows：
A kind of low-power dissipation SOC wake module, including wake source acquisition module, register configuration module, ask generation module；
Wherein, the wake source acquisition module is connected with the register configuration module, for acquisition chip PIN or core
The wake-up excitation of piece internal real time clock, and export corresponding with wake-up excitation, making that the SOC is in running order the
One signal；
The register configuration module is used to receive first signal, is sent after processing and to the request generation module
Make the in running order corresponding state configuration information of off working state module in the SOC；Wherein, the off working state mould
Block is connected with the wake module；
The request generation module is used to receive the state configuration information, generation and the state configuration information after processing
Corresponding, make the in running order interruption/wake request of the off working state module, and be respectively sent to corresponding institute
Off working state module is stated, the SOC is entered normal operating conditions.
Optionally, the chip PIN pull-up.
Optionally, the circuit of the wake module includes rising edge Acquisition Circuit, trailing edge Acquisition Circuit, the first logic electricity
Road；
Wherein, the rising edge Acquisition Circuit selects device and the first deposit for selecting device to be connected with the first via including the first via
Device；Wherein, the first via select device be used for produce the first pulse signal；
First register includes the first signal clock signal input part, the first signal input part and the first signal output
End；Wherein, first clock signal input terminal is used to receive by the chip PIN or the chip internal real-time clock
Wake up secondary signal caused by excitation；
First signal input part is used to receive first pulse signal；First signal output part is used to deposit
And the first pulse signal when the secondary signal is rising edge signal is exported, obtain first object pulse signal；
The trailing edge Acquisition Circuit selects device and the second register for selecting device to be connected with second tunnel including the second tunnel；
Second tunnel select device be used for produce the second pulse signal；
Second register includes secondary signal clock signal input terminal, secondary signal input and secondary signal output
End；Wherein, the second clock signal input part is used to receive by the chip PIN or the chip internal real-time clock
Wake up excitation to produce, the 3rd signal converted by phase inverter；
The secondary signal input is used to receive second pulse signal；
The secondary signal output end is used to depositing and exporting the letter of the second pulse when the secondary signal is trailing edge
Number, obtain the second target impulse signal；
First logic circuit is used to obtain and passed through by the first object pulse signal and second target impulse signal
Or first signal obtained after computing.
Optionally, the low-power dissipation SOC wake module also includes：
Filter circuit, for being filtered to signal caused by the wake-up excitation as the chip PIN, after obtaining filtering
Secondary signal or to as the chip PIN wake-up excitation caused by signal filter, and through the phase inverter change
The 3rd signal after being filtered.
Optionally, the wake source acquisition module includes the first wake source acquisition module and the second wake source acquisition module；
Wherein, the first wake source acquisition module is used for the wake-up excitation for receiving the chip PIN, and described second calls out
Source acquisition module of waking up is used for the wake-up excitation for receiving the chip PIN or the chip internal real-time clock.
Optionally, the off working state module includes CPU and/or interrupt control unit and/or power consumption/schema management mould
Block.
Optionally, when the off working state module includes the CPU, the interrupt control unit and the power consumption/pattern
During management module, the request generation module includes not maskable interrupts/wake request generation module and interruption/wake request production
Raw module；
Wherein, the not maskable interrupts/wake request generation module is used to send destination request to the CPU, makes institute
State CPU and enter working condition；Wherein, the destination request includes：Critical interrupt and/or hardware check and/or it is not maskable in
It is disconnected；
The interruption/wake request generation module is used to send interrupt requests to the interrupt control unit, makes the interruption
Controller enters working condition；
Wherein, the power consumption/schema management module is used to receive by the not maskable interrupts/wake request generation module
Request caused by the wake request process sent with the interruption/wake request generation module or computing.
Accordingly, the invention also discloses a kind of low-power dissipation SOC, including above-mentioned wake module.
A kind of low-power dissipation SOC wake module provided by the invention, SOC systems are made to be removed before low-power consumption mode is entered
The power supply and clock Close All for the other modules gone outside wake module and power management module；When wake module reception chip
After the wake-up excitation of PIN or chip internal, work request is sent in off working state module, SOC is entered normal work
Operation mode, so as to realize the effect for reducing SOC power consumptions, and then meet needs of the people to the longer power-on time of electronic product, promote
Enter the extensive use of electronic product.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
Fig. 1 is a kind of structural representation of low-power dissipation SOC wake module provided in an embodiment of the present invention；
Fig. 2 is a kind of structural representation of low-power dissipation SOC wake module circuit provided in an embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
It is shown in Figure 1 the embodiment of the invention discloses a kind of low-power dissipation SOC wake module, including wake source collection mould
Block, register configuration module 301, ask generation module；
Wherein, wake source acquisition module is connected with register configuration module, real for acquisition chip PIN or chip internal
Shi Shizhong wake-up excitation, and output is corresponding with wake-up excitation, makes the first signal that SOC is in running order；
Above-mentioned register configuration module 301 is used to receive the first signal, and sending after processing and to request generation module makes SOC
State configuration information corresponding to interior off working state module is in running order；Wherein, off working state module and wake module
It is connected；
Request generation module is used for reception state configuration information, and generation is corresponding with state configuration information after processing, makes
In running order interruption/the wake request of off working state module, and corresponding off working state module is respectively sent to, make
SOC enters normal operating conditions.
It should be noted that when SOC systems enter low-power consumption mode, wake module and power management module power supply are to beat
Open, remaining modular power source is closed, also, wake module clock is closed, so the requirement of wake source acquisition module is in no clock
In the case of acquisition chip PIN or real-time clock wake-up excitation.Above-mentioned off working state module includes CPU and/or interrupts control
Device and/or power consumption/schema management module.
In the embodiment of the present invention, the PIN of SOC uses upper pull-mode, it is to be understood that does not have when waking up PIN
When having encapsulation, the power consumption for further reducing chip can be configured by pulling up.
Need to describe in detail, the circuit of above-mentioned wake module is as shown in Fig. 2 including rising edge Acquisition Circuit, decline
Along Acquisition Circuit, the first logic circuit；
Wherein, rising edge Acquisition Circuit selects device and the first register for selecting device to be connected with the first via including the first via；Wherein,
The first via select device be used for produce the first pulse signal；
First register includes the first signal clock signal input part, the first signal input part and the first signal output part；
Wherein, the first clock signal input terminal is used to receive as caused by the wake-up excitation of chip PIN or chip internal real-time clock
Secondary signal；
First signal input part is used to receive the first pulse signal；First signal output part is used to deposit and export when second
The first pulse signal when signal is rising edge signal, obtains first object pulse signal；
Trailing edge Acquisition Circuit selects device and the second register for selecting device to be connected with the second tunnel including the second tunnel；
Second tunnel select device be used for produce the second pulse signal；
Second register includes secondary signal clock signal input terminal, secondary signal input and secondary signal output end；
Wherein, second clock signal input part is used to receive to be encouraged by the wake-up of chip PIN or chip internal real-time clock and produced, warp
Cross the 3rd signal of phase inverter conversion；
Secondary signal input is used to receive the second pulse signal；
Secondary signal output end is used to deposit and export the second pulse signal when secondary signal is trailing edge, obtains the
Two target impulse signals；
First logic circuit be used to obtaining by first object pulse signal and the second target impulse signal by or computing after
The first obtained signal.
Also include to reduce noise to waking up the influence encouraged, the wake module provided in the embodiment of the present invention：
Filter circuit, for being filtered to signal caused by the wake-up excitation as chip PIN, the after being filtered
After binary signal filters to signal caused by the wake-up excitation as chip PIN, and inverted device is converted to filtering
3rd signal.
In the embodiment of the present invention, above-mentioned wake source acquisition module includes the first wake source acquisition module 101 and second and waken up
Source acquisition module 102；
Wherein, the first wake source acquisition module 101 is used for the wake-up excitation of reception chip PIN, the collection of the second wake source
Module 102 is used for the wake-up excitation of reception chip PIN or chip internal real-time clock.
, please when off working state module includes CPU, interrupt control unit and power consumption/schema management module in the present embodiment
Generation module is asked to include not maskable interrupts/wake request generation module 201 and interruption/wake request generation module 202；
Wherein, maskable interrupts/wake request generation module 201 is not used to send destination request to CPU, enters CPU
Working condition；Wherein, destination request includes：Critical interrupt and/or hardware check and/or non-maskable interrupts；
Interruption/wake request generation module 202 is used to send interrupt requests to interrupt control unit, enters interrupt control unit
Working condition；
Wherein, power consumption/schema management module is used to receive by not maskable interrupts/wake request generation module 201 with
The wake request that disconnected/wake request generation module 202 is sent, which is passed through, or computing is caused asks.
Next, it should be further stated that the specific work process of above-mentioned wake module, including：
When SOC switches to working condition by off working state, first, wake module receive from chip PIN or
Chip internal sends the wake-up excitation of real-time clock, i.e. wake-up pulse；It should be noted that when the wake-up pulse received is chip
, it is necessary to first pass through filter circuit when PIN is sent, wherein the pulse width of filter circuit can pass through nonvolatile storage in SOC
Middle register configuration, the upper automatic loading of electricity.The wake-up excitation that chip internal sends real-time clock need not then pass through filter circuit.
For rising edge Acquisition Circuit part, the filtered signal 101 of device is used as first to the excitation of chip PIN after filtering
The clock end of register, once there is the value deposit that high level pulse will hold the first register " d " to " q " end.Wherein, first
The value at register " d " end selects device from alternative road, and if up along enabling, " 1 " will be input to " d " of the first register
End, accordingly even when wake module does not have the first register of clock output end 102 to export virtual value after detecting rising edge yet.Together
Reason, the signal for only needing to add behind the filter circuit after phase inverter is changed for trailing edge collecting part is as second
The clock end of register, once there is the value deposit that low level pulse will hold the second register " d " to " q " end.Wherein, second
The value at register " d " end selects device from alternative road, if trailing edge enables, " 0 " will be input to " d " end of register,
Accordingly even when wake module does not have the second register of clock output end 103 to export virtual value after detecting rising edge yet.
Chip PIN excitations rising edge status signal 102 and trailing edge status signal 103 do logic or computing obtain it is asynchronous in
Disconnected/wake-up states signal 107, while interrupt/wake up driving source acquisition module output sync break/wake-up states setting signal
106, sync break/wake-up states are recorded in register configuration module 301.
Then, register configuration module 301 receives the first signal, is sent after processing and to request generation module described in making
The in running order corresponding state configuration information 407,408 of off working state module, reaches control data generation module in SOC
Effect.It should be noted that register configuration module 301 is connected with registered bus.
For interruption/wake request generation module 202, on the premise of wake-up is enabled, any one PIN or internal real
Shi Shizhong asynchronous interrupt/wake-up states or sync break/wake-up states can all make wake module to power consumption/schema management module
Send wake request；On the premise of interruption is enabled, interrupt requests 406 are sent to interrupt control unit, interrupt terminal control unit
Off working state before.And for not maskable interrupts/wake request generation module 201, interrupt it is not maskable, can by with
Put, critical interrupt 401, hardware check 402 or not maskable interrupts 403 sent to CPU, make CPU interrupt before inoperative shape
State.Power managed module can open the power supply of all modules in system and clock, and now, SOC enters working condition.
When SOC enters working condition, then, the clock of wake module is turned on, to the same of asynchronous interrupt/wake-up states
Step 104 and 105 signals of sampling will be effective, for the signal of synchronized sampling 104 and 105 of asynchronous interrupt/wake-up states is passed through
The interruption that logic or computing obtain/wake-up states setting signal 106 will be effective, and then interruption/wake-up states 108 are effective, this
When this synchronous status signal can by asynchronous status register by reset terminal remove 102,103 signal removals be 0, from
Interruption/wake-up asynchronous mode is transformed into synchronous regime.Now power supply and clock have been switched on, and CPU can be by inquiring about or interrupting
Mode synchronous regime is removed, then start wake up after work.
It can be seen that a kind of low-power dissipation SOC wake module provided in an embodiment of the present invention, makes SOC systems enter low-power consumption mould
Before formula, by the power supply and clock Close All of other modules outside removing wake module and power management module；Work as wake-up
After the wake-up excitation of module reception chip PIN or chip internal, work request is sent in off working state module, is made
SOC enters normal mode of operation, so as to realize the effect for reducing SOC power consumptions, and then meets people to the longer power supply of electronic product
The needs of time, promote the extensive use of electronic product.
The embodiment of the invention also discloses a kind of SOC for including above wake module, the specific configuration on wake module
Referring to the specific descriptions of above example, will not be repeated here.
Finally, it is to be noted that, herein, such as first and second or the like relational terms be used merely to by
One entity or operation make a distinction with another entity or operation, and not necessarily require or imply these entities or operation
Between any this actual relation or order be present.Moreover, term " comprising ", "comprising" or its any other variant meaning
Covering including for nonexcludability, so that process, method, article or equipment including a series of elements not only include that
A little key elements, but also the other element including being not expressly set out, or also include for this process, method, article or
The intrinsic key element of equipment.In the absence of more restrictions, the key element limited by sentence "including a ...", is not arranged
Except other identical element in the process including the key element, method, article or equipment being also present.
A kind of low-power dissipation SOC wake module provided by the present invention and SOC are described in detail above, herein should
The principle and embodiment of the present invention are set forth with specific case, the explanation of above example is only intended to help and managed
Solve the method and its core concept of the present invention；Meanwhile for those of ordinary skill in the art, according to the thought of the present invention,
There will be changes in embodiment and application, in summary, this specification content should not be construed as to this hair
Bright limitation.
Claims (8)
1. a kind of low-power dissipation SOC wake module, it is characterised in that including wake source acquisition module, register configuration module, request
Generation module；
Wherein, the wake source acquisition module is connected with the register configuration module, in acquisition chip PIN or chip
The wake-up excitation of portion's real-time clock, and output is corresponding with wake-up excitation, makes the first letter that the SOC is in running order
Number；
The register configuration module is used to receive first signal, and sending after processing and to the request generation module makes institute
State the in running order corresponding state configuration information of off working state module in SOC；Wherein, the off working state module with
The wake module is connected；
The request generation module is used to receive the state configuration information, is generated after processing relative with the state configuration information
Answer, make the in running order interruption/wake request of the off working state module, and be respectively sent to corresponding described non-
Operation state module, the SOC is set to enter normal operating conditions.
2. low-power dissipation SOC wake module according to claim 1, it is characterised in that the chip PIN pull-up.
3. low-power dissipation SOC wake module according to claim 1, it is characterised in that the circuit of the wake module includes
Rising edge Acquisition Circuit, trailing edge Acquisition Circuit, the first logic circuit；
Wherein, the rising edge Acquisition Circuit selects device and the first register for selecting device to be connected with the first via including the first via；
Wherein, the first via select device be used for produce the first pulse signal；
First register includes the first signal clock signal input part, the first signal input part and the first signal output part；
Wherein, first clock signal input terminal is used to receive calling out by the chip PIN or the chip internal real-time clock
Secondary signal caused by awake excitation；
First signal input part is used to receive first pulse signal；First signal output part be used for deposit and it is defeated
Go out the first pulse signal when the secondary signal is rising edge signal, obtain first object pulse signal；
The trailing edge Acquisition Circuit selects device and the second register for selecting device to be connected with second tunnel including the second tunnel；
Second tunnel select device be used for produce the second pulse signal；
Second register includes secondary signal clock signal input terminal, secondary signal input and secondary signal output end；
Wherein, the second clock signal input part is used to receive calling out by the chip PIN or the chip internal real-time clock
Excitation of waking up produces, the 3rd signal converted by phase inverter；
The secondary signal input is used to receive second pulse signal；
The secondary signal output end is used to deposit and export the second pulse signal when the secondary signal is trailing edge, obtains
To the second target impulse signal；
First logic circuit is used to obtain and is passed through or transported by the first object pulse signal and second target impulse signal
First signal obtained after calculation.
4. low-power dissipation SOC wake module according to claim 3, it is characterised in that also include：
Filter circuit, for being filtered to signal caused by the wake-up excitation as the chip PIN, the after being filtered
Binary signal filters to signal caused by the wake-up excitation as the chip PIN, and is converted to through the phase inverter
The 3rd signal after filtering.
5. low-power dissipation SOC wake module according to claim 1, it is characterised in that the wake source acquisition module includes
First wake source acquisition module and the second wake source acquisition module；
Wherein, the first wake source acquisition module is used for the wake-up excitation for receiving the chip PIN, second wake source
Acquisition module is used for the wake-up excitation for receiving the chip PIN or the chip internal real-time clock.
6. the low-power dissipation SOC wake module according to any one of claim 1 to 5, it is characterised in that the off working state
Module includes CPU and/or interrupt control unit and/or power consumption/schema management module.
7. low-power dissipation SOC wake module according to claim 6, it is characterised in that when the off working state module bag
When including the CPU, the interrupt control unit and the power consumption/schema management module, the request generation module includes shielding
Cover interruption/wake request generation module and interruption/wake request generation module；
Wherein, the not maskable interrupts/wake request generation module is used to send destination request to the CPU, makes the CPU
Into working condition；Wherein, the destination request includes：Critical interrupt and/or hardware check and/or non-maskable interrupts；
The interruption/wake request generation module is used to send interrupt requests to the interrupt control unit, controls described interrupt
Device enters working condition；
Wherein, the power consumption/schema management module is used to receive by the not maskable interrupts/wake request generation module and institute
State wake request process or the caused request of computing that interruption/wake request generation module is sent.
8. a kind of low-power dissipation SOC, it is characterised in that including the wake module described in any one of claim 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710986284.XA CN107678532A (en) | 2017-10-20 | 2017-10-20 | A kind of low-power dissipation SOC wake module and low-power dissipation SOC |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710986284.XA CN107678532A (en) | 2017-10-20 | 2017-10-20 | A kind of low-power dissipation SOC wake module and low-power dissipation SOC |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107678532A true CN107678532A (en) | 2018-02-09 |
Family
ID=61141787
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710986284.XA Pending CN107678532A (en) | 2017-10-20 | 2017-10-20 | A kind of low-power dissipation SOC wake module and low-power dissipation SOC |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107678532A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109582371A (en) * | 2018-11-06 | 2019-04-05 | 珠海格力电器股份有限公司 | A kind of low-power consumption awakening method and device |
| CN109753313A (en) * | 2019-01-04 | 2019-05-14 | 华大半导体有限公司 | A kind of device and method for wake-up processor |
| CN110018791A (en) * | 2019-03-28 | 2019-07-16 | 深圳忆联信息系统有限公司 | Power managed control method and system based on SSD SOC |
| CN112148662A (en) * | 2020-08-17 | 2020-12-29 | 上海赛昉科技有限公司 | Low-power-consumption chip architecture awakened by I2C address matching and awakening method |
| CN112204923A (en) * | 2018-09-27 | 2021-01-08 | 纳米电力有限责任公司 | Power management device and method of operation |
| CN113608605A (en) * | 2021-07-16 | 2021-11-05 | 芯来智融半导体科技(上海)有限公司 | Wake-up circuit, chip system and electronic equipment |
| CN113824623A (en) * | 2021-09-17 | 2021-12-21 | 辰海微电(苏州)半导体有限公司 | Low-power-consumption asynchronous communication mechanism |
| CN114384996A (en) * | 2022-01-14 | 2022-04-22 | 长鑫存储技术有限公司 | Power supply control circuit and control method |
| CN114448403A (en) * | 2020-11-05 | 2022-05-06 | 中移物联网有限公司 | Asynchronous wake-up circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101387896A (en) * | 2008-10-22 | 2009-03-18 | 炬力集成电路设计有限公司 | Method and device for implementing system-on-chip wake and sleep function in SOC |
| CN202916787U (en) * | 2012-11-13 | 2013-05-01 | 江苏东大集成电路系统工程技术有限公司 | Chip with extra-low stand-by power consumption |
| CN103412634A (en) * | 2013-07-30 | 2013-11-27 | 深圳市汇顶科技股份有限公司 | Device and method for awakening MCU (micro control unit) of SOC (system on chip) chip |
| CN103645794A (en) * | 2013-11-15 | 2014-03-19 | 北京兆易创新科技股份有限公司 | Chip and method for achieving sleep mode wake-up through edge detection circuit |
| CN204423297U (en) * | 2015-01-26 | 2015-06-24 | 北京神州龙芯集成电路设计有限公司 | A kind of SOC (system on a chip) in order to realize Systematical control and power management |
| CN106055026A (en) * | 2016-07-20 | 2016-10-26 | 深圳市博巨兴实业发展有限公司 | Real time clock unit in microcontroller SOC (System On Chip) |
-
2017
- 2017-10-20 CN CN201710986284.XA patent/CN107678532A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101387896A (en) * | 2008-10-22 | 2009-03-18 | 炬力集成电路设计有限公司 | Method and device for implementing system-on-chip wake and sleep function in SOC |
| CN202916787U (en) * | 2012-11-13 | 2013-05-01 | 江苏东大集成电路系统工程技术有限公司 | Chip with extra-low stand-by power consumption |
| CN103412634A (en) * | 2013-07-30 | 2013-11-27 | 深圳市汇顶科技股份有限公司 | Device and method for awakening MCU (micro control unit) of SOC (system on chip) chip |
| CN103645794A (en) * | 2013-11-15 | 2014-03-19 | 北京兆易创新科技股份有限公司 | Chip and method for achieving sleep mode wake-up through edge detection circuit |
| CN204423297U (en) * | 2015-01-26 | 2015-06-24 | 北京神州龙芯集成电路设计有限公司 | A kind of SOC (system on a chip) in order to realize Systematical control and power management |
| CN106055026A (en) * | 2016-07-20 | 2016-10-26 | 深圳市博巨兴实业发展有限公司 | Real time clock unit in microcontroller SOC (System On Chip) |
Non-Patent Citations (1)
| Title |
|---|
| 薛智文: "《操作系统》", 31 July 2003, 中国铁道出版社 * |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112204923A (en) * | 2018-09-27 | 2021-01-08 | 纳米电力有限责任公司 | Power management device and method of operation |
| CN109582371A (en) * | 2018-11-06 | 2019-04-05 | 珠海格力电器股份有限公司 | A kind of low-power consumption awakening method and device |
| CN109753313A (en) * | 2019-01-04 | 2019-05-14 | 华大半导体有限公司 | A kind of device and method for wake-up processor |
| CN109753313B (en) * | 2019-01-04 | 2021-09-07 | 华大半导体有限公司 | Device and method for waking up processor |
| CN110018791A (en) * | 2019-03-28 | 2019-07-16 | 深圳忆联信息系统有限公司 | Power managed control method and system based on SSD SOC |
| CN112148662A (en) * | 2020-08-17 | 2020-12-29 | 上海赛昉科技有限公司 | Low-power-consumption chip architecture awakened by I2C address matching and awakening method |
| CN112148662B (en) * | 2020-08-17 | 2024-02-09 | 上海赛昉科技有限公司 | Low-power-consumption chip architecture and wake-up method by using I2C address matching wake-up |
| CN114448403A (en) * | 2020-11-05 | 2022-05-06 | 中移物联网有限公司 | Asynchronous wake-up circuit |
| CN113608605A (en) * | 2021-07-16 | 2021-11-05 | 芯来智融半导体科技(上海)有限公司 | Wake-up circuit, chip system and electronic equipment |
| CN113608605B (en) * | 2021-07-16 | 2024-05-14 | 芯来智融半导体科技(上海)有限公司 | Wake-up circuit, chip system and electronic equipment |
| CN113824623A (en) * | 2021-09-17 | 2021-12-21 | 辰海微电(苏州)半导体有限公司 | Low-power-consumption asynchronous communication mechanism |
| CN114384996A (en) * | 2022-01-14 | 2022-04-22 | 长鑫存储技术有限公司 | Power supply control circuit and control method |
| CN114384996B (en) * | 2022-01-14 | 2023-10-24 | 长鑫存储技术有限公司 | Power supply control circuit and control method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107678532A (en) | A kind of low-power dissipation SOC wake module and low-power dissipation SOC | |
| CN103645794B (en) | Chip and method for achieving sleep mode wake-up through edge detection circuit | |
| CN103856192B (en) | Embedded pulse sequential circuit system | |
| CN103412990B (en) | A kind of multi-level collaborative low-power design method | |
| CN100442204C (en) | System-on-chip chip and its power consumption control method | |
| CN103631360A (en) | Chip allowing sleep mode and method | |
| CN102801174B (en) | Main control module for low-voltage dynamic reactive harmonic comprehensive compensation device | |
| CN104281465B (en) | Computer and awakening method thereof | |
| CN107515662A (en) | Low-power consumption management method in a kind of MCU chip towards the application of keying class | |
| CN101350612B (en) | Circuit for preventing gating clock bur | |
| US9780644B1 (en) | Methods and apparatus for always on domain finite state machine shutdown using a clock source from a power managed domain | |
| CN107463236A (en) | A kind of reset detection circuit and reset detection method | |
| CN109799898A (en) | A kind of power control of chip, chip and its power control method | |
| CN106843436A (en) | A kind of reset control module and repositioning method | |
| CN104750226A (en) | USB (universal serial bus) OTG (on-the-go) pattern recognition system and USB OTG pattern recognition method | |
| CN104793723A (en) | Low-power-consumption control circuit based on level detection | |
| CN109861343A (en) | A kind of fitful power management circuit | |
| CN103376877B (en) | A kind of multi-core processor clock control device and control method | |
| CN106066684B (en) | Master-slave mode SOC chip low power consumpting controling circuit | |
| CN102361216A (en) | Solid laser control system | |
| CN205594571U (en) | Power controlling means and computer | |
| CN100452005C (en) | System and method for controlling interrput | |
| CN202749829U (en) | Main control module used for low voltage dynamic wattless harmonic wave comprehensive compensation device | |
| CN206884766U (en) | A kind of cell management system of electric automobile based on ARM9 | |
| CN101452337A (en) | Control method and device for peripheral equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 215011 23rd Floor, Building 3, Suzhou Pioneer Park, 209 Zhuyuan Road, Suzhou High-tech Zone, Jiangsu Province Applicant after: Suzhou Guoxin Technology Co., Ltd. Address before: 215011 23rd Floor, Building 3, Suzhou Pioneer Park, 209 Zhuyuan Road, Suzhou High-tech Zone, Jiangsu Province Applicant before: C*Core Technology (Suzhou) Co., Ltd. |
|
| CB02 | Change of applicant information | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180209 |
|
| RJ01 | Rejection of invention patent application after publication |