CN114448403A - Asynchronous wake-up circuit - Google Patents
Asynchronous wake-up circuit Download PDFInfo
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- CN114448403A CN114448403A CN202011222513.9A CN202011222513A CN114448403A CN 114448403 A CN114448403 A CN 114448403A CN 202011222513 A CN202011222513 A CN 202011222513A CN 114448403 A CN114448403 A CN 114448403A
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Abstract
The application provides an asynchronous wake-up circuit, which comprises a reset control circuit, an effective edge detection circuit, a wake-up locking circuit, an asynchronous frequency division circuit, a filter circuit and a wake-up generation circuit; the effective edge detection circuit is connected with the clock source through the wake-up locking circuit; the asynchronous frequency division circuit is connected with the clock source and is used for carrying out asynchronous frequency division on a clock signal output by the clock source; the filter circuit is connected with the asynchronous frequency division circuit and is used for filtering the asynchronous wake-up signal through the asynchronous frequency division clock signal; the wake-up generating circuit is respectively connected with the filter circuit, the wake-up locking circuit and the reset control circuit, and is used for judging whether the filter signal output by the filter circuit meets a preset wake-up condition or not, enabling the clock source to continuously output a clock signal through the wake-up locking circuit if the preset wake-up condition is met, and controlling the filter circuit and the effective edge detection circuit to reset through the reset control circuit. The power consumption can be reduced.
Description
Technical Field
The present application relates to the field of circuitry, and more particularly, to an asynchronous wake-up circuit.
Background
In application scenes of mobile, wearable, internet of things and the like powered by batteries, a circuit system is required to support various low power consumption modes to save power consumption, all clocks can be completely closed by the system in the lowest power consumption mode, an asynchronous wake-up circuit needs to support the wake-up system through an external signal, the external signal is generally filtered firstly to reduce the number of times of mistakenly waking up the system due to signal interference, and effective signals after filtering act on the asynchronous wake-up circuit to wake up the whole system. In order to support filtering in a larger range, a current source-based filter circuit is adopted in the existing scheme, however, the current source is added by adopting the current source-based filter circuit, which results in larger power consumption.
Disclosure of Invention
The embodiment of the application provides an asynchronous wake-up circuit to solve the problem of large power consumption.
The embodiment of the application provides an asynchronous wake-up circuit which is characterized by comprising a reset control circuit, an effective edge detection circuit, a wake-up locking circuit, an asynchronous frequency division circuit, a filter circuit and a wake-up generation circuit;
the effective edge detection circuit is connected with a clock source through the wake-up locking circuit and used for enabling the clock source to output a clock signal after detecting an asynchronous wake-up signal;
the asynchronous frequency division circuit is connected with the clock source and is used for carrying out asynchronous frequency division on a clock signal output by the clock source;
the filter circuit is connected with the asynchronous frequency division circuit and is used for filtering the asynchronous wake-up signal through the asynchronous frequency division clock signal;
the wake-up generating circuit is respectively connected with the filter circuit, the wake-up locking circuit and the reset control circuit, and is used for judging whether the filter signal output by the filter circuit meets a preset wake-up condition or not, if the preset wake-up condition is met, the clock source is enabled to continuously output clock signals through the wake-up locking circuit, and the reset control circuit controls the filter circuit and the effective edge detection circuit to reset.
Thus, in this embodiment, when the asynchronous wake-up circuit is completely stationary, after the effective edge detection circuit detects the effective wake-up edge of the asynchronous wake-up signal, the clock source is immediately enabled through the wake-up lock circuit, then the clock signal of the clock source is subjected to asynchronous frequency division through the asynchronous frequency division circuit, the asynchronous wake-up signal is filtered through the asynchronous frequency division clock signal, the filter signal output by the filter circuit is judged through the wake-up generation circuit, if the preset wake-up condition is met, the clock source is enabled to continuously output the clock signal through the wake-up lock circuit, and the filter circuit and the effective edge detection circuit are controlled to reset through the reset control circuit, so that the filtering of the asynchronous signal in a larger range can be realized without the cooperation of external circuits, and the false wake-up probability of the system is reduced, therefore, the technical effect of reducing the power consumption of the asynchronous wake-up circuit can be achieved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of an asynchronous wake-up circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of another asynchronous wake-up circuit provided in an embodiment of the present application;
fig. 3 is an operation timing diagram of an asynchronous wake-up circuit according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a diagram of an asynchronous wake-up circuit according to an embodiment of the present disclosure, and as shown in fig. 1, the asynchronous wake-up circuit 100 includes a reset control circuit 101, an active edge detection circuit 102, a wake-up locking circuit 103, an asynchronous frequency division circuit 104, a filter circuit 105, and a wake-up generation circuit 106;
the active edge detection circuit 102 is connected to the clock source 200 through the wake-up lock circuit 103, and is configured to enable the clock source 200 to output a clock signal after detecting the asynchronous wake-up signal;
the asynchronous frequency division circuit 104 is connected to the clock source 200, and is configured to perform asynchronous frequency division on a clock signal output by the clock source 200;
the filter circuit 105 is connected to the asynchronous frequency dividing circuit 104, and is configured to filter the asynchronous wake-up signal through the asynchronous frequency divided clock signal;
the wake-up generating circuit 106 is connected to the filter circuit 105, the wake-up locking circuit 103, and the reset control circuit 101, where the wake-up generating circuit 106 is configured to determine whether the filter signal output by the filter circuit 105 meets a preset wake-up condition, and if the preset wake-up condition is met, the wake-up locking circuit 103 enables the clock source 200 to continuously output a clock signal, and the reset control circuit 101 controls the filter circuit 105 and the effective edge detecting circuit 102 to reset.
The controlling the reset of the filter circuit 105 may include controlling the reset of the filter circuit 105 or controlling the clock of the filter circuit 105 to be turned off, for example: in addition, the reset control circuit 101 may control the active edge detection circuit 102 to reset when the filtering signal output by the filtering circuit 105 satisfies a preset wake-up condition, so as to control the clock of the filtering circuit 105 to be turned off, and may reset the filtering circuit 105 and the active edge detection circuit 102 when an active asynchronous reset signal is input by the reset control circuit 101.
The preset wake-up condition may be a preset wake-up condition, for example: the filter width is configured in advance, when the filter signal output by the filter circuit 105 satisfies the filter width, the wake-up generating circuit 106 may generate an effective wake-up reset signal and a wake-up signal, and if the filter width is not satisfied, the wake-up generating circuit 106 may only generate an effective wake-up reset signal. The effective wake-up reset signal generated by the wake-up generation circuit 106 can reset the effective edge detection circuit 102 through the reset control circuit 101, and further close the working clock of the filter circuit 105, and the effective wake-up signal generated by the wake-up generation circuit 106 can continuously enable the clock source through the wake-up lock circuit 103.
In this embodiment, when the asynchronous wake-up circuit is completely stationary, after the effective edge detection circuit 102 detects the effective wake-up edge of the asynchronous wake-up signal, the clock source 200 is immediately enabled by the wake-up lock circuit 103, then the clock signal of the clock source 200 is subjected to asynchronous frequency division by the asynchronous frequency division circuit 104, the asynchronous wake-up signal is filtered by the asynchronous frequency division clock signal, the filter signal output by the filter circuit 105 is determined by the wake-up generation circuit 106, if the preset wake-up condition is met, the clock source 200 is enabled to continuously output the clock signal by the wake-up lock circuit 103, the reset control circuit 101 controls the filter circuit 105 and the effective edge detection circuit 102 to reset, and the asynchronous wake-up signal filtering in a larger range can be realized without the cooperation of an external circuit, the false wake-up probability of the system is reduced, so that the technical effect of reducing the power consumption of the asynchronous wake-up circuit can be realized.
Optionally, as shown in fig. 2, if the preset wake-up condition is not satisfied, the wake-up generating circuit 106 controls the filter circuit 105 and the active edge detecting circuit 102 to reset through the reset control circuit 101.
In this embodiment, when the filtering signal output by the filtering circuit 105 does not satisfy the preset wake-up condition, the reset control circuit 101 only resets the filtering circuit 105 and the effective edge detection circuit 102, the enable signal of the clock source 200 fails, and the circuit system returns to the state of detecting the effective edge of the asynchronous wake-up signal again, so as to filter the asynchronous wake-up signal and reduce the number of times that the system is mistakenly woken up due to signal interference.
Optionally, as shown in fig. 2, a first output end of the effective edge detection circuit 102 is connected to a first input end of the wakening-locking circuit 103, a first output end of the wakening-locking circuit 103 is connected to an input end of the clock source 200, a first output end of the clock source 200 is connected to an input end of the asynchronous frequency dividing circuit 104, a second output end of the clock source 200 is connected to a second input end of the wakening-locking circuit 103, an output end of the asynchronous frequency dividing circuit 104 is connected to a first input end of the filter circuit 105, a first output end of the filter circuit 105 is connected to a first input end of the wakening-generating circuit 106, a first output end of the wakening-generating circuit 106 is connected to a third input end of the wakening-locking circuit 103, a second output end of the wakening-generating circuit 106 is connected to a first input end of the reset control circuit 101, a first output end of the reset control circuit 101 is connected to a second input end of the filter circuit 105, a second output end of the reset control circuit 101 is connected to a first input end of the effective edge detection circuit 102, a third output end of the reset control circuit 101 is connected to a second input end of the wake-up generation circuit 106, and a second output end of the effective edge detection circuit 102 is connected to a third input end of the filter circuit 105;
the second input end of the reset control circuit 101 is configured to receive the asynchronous reset signal, the third input end of the reset control circuit 101 is configured to receive the asynchronous wake-up signal, the second input end of the effective edge detection circuit 102 is configured to receive the asynchronous wake-up signal, the third input end of the filter circuit 105 is configured to receive the asynchronous wake-up signal, and the fourth input end of the wake-up lock circuit 103 is configured to receive the asynchronous reset signal.
In this embodiment, when the asynchronous wake-up circuit is completely stationary, after the effective edge detection circuit 102 detects the effective wake-up edge of the asynchronous wake-up signal, the clock source 200 is immediately enabled by the wake-up lock circuit 103, then the clock signal of the clock source 200 is subjected to asynchronous frequency division by the asynchronous frequency division circuit 104, the asynchronous wake-up signal is filtered by the asynchronous frequency divided clock signal, the filter signal output by the filter circuit 105 is determined by the wake-up generation circuit 106, if the preset wake-up condition is met, the clock source 200 is enabled to continuously output the clock signal by the wake-up lock circuit 103, the reset control circuit 101 controls the filter circuit 105 and the effective edge detection circuit 102 to reset, and the asynchronous wake-up signal filtering in a larger range can be realized without the cooperation of an external circuit, the false wake-up probability of the system is reduced, so that the technical effect of reducing the power consumption of the asynchronous wake-up circuit can be realized.
In addition, the filtering of the asynchronous signal is realized through the digital circuit, the filtering precision can be improved, the configuration is easy, and the process portability of the asynchronous wake-up circuit can be improved.
Optionally, as shown in fig. 2, the asynchronous frequency divider circuit 104 includes an N-stage asynchronous frequency divider 1041 and a data selector 1042, where:
the output end of the N-stage asynchronous frequency divider 1041 is connected to the input end of the data selector 1042, the output end of the data selector 1042 is connected to the first input end of the filter circuit 105, and the input end of the N-stage asynchronous frequency divider 1041 is connected to the first output end of the clock source 200.
The N-stage asynchronous frequency divider 1041 and the data selector 1042 in the asynchronous frequency divider circuit 104 may be configured in a matching manner, and the N-stage asynchronous frequency divider 1041 may output 2NAsynchronous frequency division signals, for example: the two-stage asynchronous frequency divider is matched with the one-out-of-four data selector to perform asynchronous frequency division, or the three-stage asynchronous frequency divider is matched with the one-out-of-eight data selector to perform asynchronous frequency division, and the like.
In this embodiment, the N-stage asynchronous frequency divider 1041 and the data selector 1042 generate a frequency-divided clock signal according to the clock signal output by the clock source 200, the asynchronous wake-up signal may be filtered according to the frequency-divided clock signal, and the clock signal output by the clock source 200 is subjected to asynchronous frequency division by the N-stage asynchronous frequency divider and the data selector, so that a frequency-divided counter with a large scale may be avoided, thereby reducing the power consumption overhead of the asynchronous frequency-divided circuit 104.
Optionally, as shown in fig. 2, the N-stage asynchronous frequency divider 1041 is a two-stage asynchronous frequency divider, and the data selector 1042 is a one-out-of-four data selector, where:
the first output end of the second-level asynchronous frequency divider is connected with the first input end of the four-select-one data selector, the second output end of the second-level asynchronous frequency divider is connected with the second input end of the four-select-one data selector, the third output end of the second-level asynchronous frequency divider is connected with the third input end of the four-select-one data selector, the fourth output end of the second-level asynchronous frequency divider is connected with the fourth input end of the four-select-one data selector, the output end of the four-select-one data selector is connected with the first input end of the filter circuit 105, and the input end of the second-level asynchronous frequency divider is connected with the first output end of the clock source 200.
In this embodiment, the clock signal output by the clock source 200 is subjected to asynchronous frequency division through the two-stage asynchronous frequency divider and the one-out-of-four data selector, so as to output an asynchronous frequency division signal, and the power consumption of the asynchronous classification circuit 104 is limited within the load of the asynchronous frequency divider, thereby saving the power consumption of the asynchronous frequency division circuit 104.
Optionally, as shown in fig. 2, the filter circuit 105 includes a first and gate G1, a first register S1, a second register S2, a third register S3, and a fourth register S4, where:
a first input end of the first and gate G1 is connected to an output end of the data selector, an output end of the first and gate G1 is connected to a clock end of the first register S1, an output end of the first and gate G1 is connected to a clock end of the second register S2, an output end of the first and gate G1 is connected to a clock end of the third register S3, an output end of the first and gate G1 is connected to a clock end of the fourth register S4, an output end of the first register S1 is connected to an input end of the second register S2, an output end of the second register S2 is connected to an input end of the third register S3, and an output end of the third register S3 is connected to an input end of the fourth register S4;
a second input end of the first and gate G1 is connected to a second output end of the active edge detection circuit 102, an output end of the first and gate G1 is connected to a first input end of the wake-up generating circuit 106, an output end of the fourth register S4 is connected to a first input end of the wake-up generating circuit 106, a reset end of the first register S1 is connected to a first output end of the reset control circuit 101, a reset end of the second register S2 is connected to a first output end of the reset control circuit 101, a reset end of the third register S3 is connected to a first output end of the reset control circuit 101, and a reset end of the fourth register S4 is connected to a first output end of the reset control circuit 101;
the input end of the first register S1 is used for inputting the asynchronous wake-up signal.
In this embodiment, the first register S1, the second register S2, the third register S3, and the fourth register S4 filter the asynchronous wake-up signal in a cascade manner, and the first and gate G1 controls the clock terminals of the first register S1, the second register S2, the third register S3, and the fourth register S4, so that it is possible to turn on the filter clock during the filtering of the asynchronous wake-up signal and turn off the filter clock during the non-operation time of the filter circuit 105, that is, it is possible to turn off the clock of the filter circuit 105 by the first and gate when the wake-up reset signal is generated by the wake-up generation circuit 106 regardless of whether the wake-up signal is generated by the wake-up generation circuit 106, thereby reducing the power consumption of the filter circuit 105.
In addition, by connecting the clock terminals of the first register S1, the second register S2, the third register S3 and the fourth register S4 to the first output terminal of the reset control circuit 101, the first register S1, the second register S2, the third register S3 and the fourth register S4 can be reset by the reset control circuit 101 when receiving an asynchronous reset signal or an asynchronous wake-up signal, which is valid, and is invalid, so that the power consumption of the filter circuit 105 is reduced.
Optionally, as shown in fig. 2, the wake-up generating circuit 106 includes a fifth register S5, a second and gate G2, a third and gate G3, and a fourth and gate G4, where:
the output end of the fifth register S5 is connected to the first input end of the third and gate G3, the first input end of the fourth and gate G4 is connected to the output end of the second and gate G2, and the second input end of the fourth and gate G4 is connected to the output end of the third and gate G3;
an input end of the fifth register S5 is connected to an output end of the fourth register S4, a clock end of the fifth register S5 is connected to an output end of the first and gate G1, a first input end of the second and gate G2 is connected to an output end of the second register S2, a second input end of the second and gate G2 is connected to an output end of the third register S3, a third input end of the second and gate G2 is connected to an output end of the fourth register S4, a second input end of the third and gate G3 is connected to an output end of the fourth register S4, and an output end of the fourth and gate G4 is connected to a third input end of the wake-up lock circuit 103.
The wake-up reset signal output from the fifth register S5 may act on the reset control circuit 101, the active edge detection circuit 102 is reset by the reset control circuit 101, and the working clock of the filter circuit 105 is turned off, and the wake-up signal output from the fourth and gate G4 may act on the wake-up lock circuit 103, so that the wake-up lock circuit 103 continuously enables the clock source 200.
In this embodiment, the fifth register S5 outputs the wake-up reset signal, and the fourth and gate outputs the wake-up signal, so that the wake-up reset signal and the wake-up signal can be generated and reset when the preset wake-up condition is satisfied, the filter circuit 105 and the effective edge detection circuit 102 are reset, the clock source 200 is continuously enabled, and when the preset wake-up condition is satisfied, only the wake-up reset signal is generated and reset, the filter circuit 105 and the effective edge detection circuit 102 are reset, the circuit enters the static state again, waits for the detection of the effective edge of the next wake-up signal, and the interference to the asynchronous wake-up circuit can be reduced.
Optionally, as shown in fig. 2, the wakelock circuit 103 includes an or gate G7, a sixth register F2, and a synchronization/judgment logic circuit 1031, where:
an input end of the synchronization/judgment logic circuit 1031 is connected to an output end of the fourth and gate G4, an output end of the synchronization/judgment logic circuit 1031 is connected to an input end of the sixth register F2, a clock end of the sixth register F2 is connected to the second output end of the clock source 200, an output end of the sixth register F2 is connected to the first input end of the or gate G7, a second input end of the or gate G7 is connected to the first output end of the effective edge detection circuit 102, and an output end of the or gate G7 is connected to an input end of the clock source 200;
the reset terminal of the sixth register F2 is configured to receive the asynchronous reset signal.
The second input terminal of the or gate G7 is connected to the first output terminal of the active edge detection circuit 102, and the clock source 200 is enabled immediately when the active edge detection circuit 102 detects the active edge of the wake-up signal.
The input terminal of the synchronization/determination logic circuit 1031 is connected to the output terminal of the fourth and gate G4, that is, receives the valid wake-up signal output by the wake-up generating circuit 106, and the output terminal of the synchronization/determination logic circuit 1031 is connected to the input terminal of the sixth register F2, so that when the valid wake-up signal is received, the sixth register F2 may be set to make the output terminal of the sixth register F2 be at a high level, thereby continuously enabling the clock source 200.
In this embodiment, by determining whether the wake-up signal output by the wake-up generating circuit 106 is valid, if the valid edge of the wake-up signal output by the wake-up generating circuit 106 is detected, a clock enable signal is generated to continuously enable the clock source 200, and if the wake-up signal output by the wake-up generating circuit 106 is invalid, the valid edge detecting circuit is reset by the wake-up reset signal output by the wake-up generating circuit 106, so that the clock source 200 is turned off due to the enable failure, the asynchronous wake-up circuit enters a static state again, and the number of times that the asynchronous wake-up circuit is mistakenly awakened is reduced.
In addition, taking the asynchronous wake-up signal wkp _ src is active high, the asynchronous frequency divider 104 is configured to divide by 4 of losc _ clk, and using 4-stage digital filtering as an example, fig. 3 is a timing diagram of operation of the asynchronous wake-up circuit, when the asynchronous wake-up signal wkp _ src is low during first wake-up, the whole circuit system is in a static state, when the rising edge of the asynchronous wake-up signal wkp _ src comes, the output F1.q of the register F1 is active therewith, the clock source enable signal losc _ en is active therewith, when the output of the clock signal losc _ clk starts, the asynchronous 4-divided clocks losc _ div _ clk and its gated clock losc _ div _ gclk start to be output, the cascade registers S1, S2, S3, S4 and S5, the outputs S1.q, S2.q, S3.q, S4.q, and S5.q are sequentially active, when the asynchronous wake-up signal wkp. sq, and the synchronous wake-up signal sxnc, the synchronous wake-clk generate synchronous wake-up signal sxq, when the synchronous wake-up signal sx2. isb 3.q, s4. isb, s9. 3. q. 3. q. 3. clk are all high, and s9. clk are active, and the synchronous wake-clk, i.e. set losc _ set, then reset register f1.q with s5.q as wake-up reset signal and simultaneously turn off gated clock losc _ div _ gclk, so that the circuit re-enters the detection state of the next valid edge of the asynchronous wake-up signal.
When the low level of the subsequent asynchronous wake-up signal wkp _ src comes on, F1, S1, S2, S3, S4, and S5 are reset again. When the rising edge of the asynchronous wake-up signal wkp _ src is still on, the wake-up circuit operates according to the first wake-up if losc _ clk is turned off. When the rising edge of the asynchronous wake-up signal wkp _ src is still on, if losc _ clk is not turned off at this time, f1.q is immediately enabled and los _ div _ gclk is enabled, and depending on the context of the rising edges of losc _ div _ gclk and the wake-up signal, s1.q may start sampling at the first or second rising edge of losc _ div _ gclk, with subsequent timing consistent with the first wake-up.
Optionally, as shown in fig. 2, the reset control circuit 101 includes a fifth and gate G5 and a sixth and gate G6, where:
an output end of the fifth and gate G5 is connected to a first input end of the sixth and gate G6, a second input end of the sixth and gate G6 is connected to an output end of the fifth register S5, and an output end of the sixth and gate G6 is connected to a first input end of the active edge detection circuit 102;
the output end of the fifth and gate G5 is connected to the reset end of the first register S1, the output end of the fifth and gate G5 is connected to the reset end of the second register S2, the output end of the fifth and gate G5 is connected to the reset end of the third register S3, the output end of the fifth and gate G5 is connected to the reset end of the fourth register S4, and the output end of the fifth and gate G5 is connected to the reset end of the fifth register S5; a first input end of the fifth and gate G5 is configured to receive the asynchronous reset signal, and a second input end of the fifth and gate G5 is configured to receive the asynchronous wake-up signal.
The reset control circuit 101 may reset the active edge detection circuit 102 and the filter circuit 105 when receiving an asynchronous active reset signal or an asynchronous active wake-up signal input from the outside, and the reset control circuit 101 resets the active edge detection circuit 102 when receiving an active wake-up signal of the wake-up generation circuit.
In this embodiment, the reset control circuit 101 may control the filter circuit 105 to reset according to an input asynchronous reset signal, an input asynchronous wake-up signal, and an input reset wake-up signal, and may also control the effective edge detection circuit 102 to reset, so as to control the operating clock of the filter circuit 105 to be turned off, thereby reducing the power consumption of the filter circuit 105 and recovering the detection state of the effective edge detection circuit 102.
Optionally, as shown in fig. 2, the effective edge detection circuit 102 includes a Buffer and a seventh register F1, where:
an output end of the Buffer is connected to a clock end of the seventh register F1, an input end of the seventh register F1 is grounded, a reset end of the seventh register F1 is connected to an output end of the sixth and gate G6, an output end of the seventh register F1 is connected to a second input end of the or gate G7, and an output end of the seventh register F1 is connected to a second input end of the first and gate G1;
and the input end of the Buffer is used for receiving the asynchronous wake-up signal.
In this embodiment, the output of the seventh register F1 may control the wakelock circuit 103 to enable the clock source 200 and the filter clock of the filter circuit 105 to be turned off, and the Buffer may output the input asynchronous wake-up signal after a proper delay, so as to avoid the timing problem that the clock terminal and the reset terminal of the seventh register F1 simultaneously input the asynchronous wake-up signal.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Further, it should be noted that the scope of the methods and apparatus of the embodiments of the present application is not limited to performing the functions in the order illustrated or discussed, but may include performing the functions in a substantially simultaneous manner or in a reverse order based on the functions involved, e.g., the methods described may be performed in an order different than that described, and various steps may be added, omitted, or combined. In addition, features described with reference to certain examples may be combined in other examples.
While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. An asynchronous wake-up circuit is characterized by comprising a reset control circuit, an effective edge detection circuit, a wake-up locking circuit, an asynchronous frequency division circuit, a filter circuit and a wake-up generation circuit;
the effective edge detection circuit is connected with a clock source through the wake-up locking circuit and used for enabling the clock source to output a clock signal after detecting an asynchronous wake-up signal;
the asynchronous frequency division circuit is connected with the clock source and is used for carrying out asynchronous frequency division on a clock signal output by the clock source;
the filter circuit is connected with the asynchronous frequency division circuit and is used for filtering the asynchronous wake-up signal through the asynchronous frequency division clock signal;
the wake-up generating circuit is respectively connected with the filter circuit, the wake-up locking circuit and the reset control circuit, and is used for judging whether the filter signal output by the filter circuit meets a preset wake-up condition or not, if the preset wake-up condition is met, the clock source is enabled to continuously output clock signals through the wake-up locking circuit, and the reset control circuit controls the filter circuit and the effective edge detection circuit to reset.
2. The asynchronous wake-up circuit of claim 1, wherein the wake-up generation circuit controls the filter circuit and the active edge detection circuit to reset via the reset control circuit if the preset wake-up condition is not satisfied.
3. The asynchronous wake-up circuit of claim 1, wherein a first output of the active edge detection circuit is connected to a first input of the wake-up lock circuit, a first output of the wake-up lock circuit is connected to an input of the clock source, a first output of the clock source is connected to an input of the asynchronous frequency divider circuit, a second output of the clock source is connected to a second input of the wake-up lock circuit, an output of the asynchronous frequency divider circuit is connected to a first input of the filter circuit, a first output of the filter circuit is connected to a first input of the wake-up generator circuit, a first output of the wake-up generator circuit is connected to a third input of the wake-up lock circuit, a second output of the wake-up generator circuit is connected to a first input of the reset control circuit, the first output end of the reset control circuit is connected with the second input end of the filter circuit, the second output end of the reset control circuit is connected with the first input end of the effective edge detection circuit, the third output end of the reset control circuit is connected with the second input end of the wake-up generation circuit, and the second output end of the effective edge detection circuit is connected with the third input end of the filter circuit;
the second input end of the reset control circuit is used for receiving the asynchronous reset signal, the third input end of the reset control circuit is used for receiving the asynchronous wake-up signal, the second input end of the effective edge detection circuit is used for receiving the asynchronous wake-up signal, the third input end of the filter circuit is used for receiving the asynchronous wake-up signal, and the fourth input end of the wake-up locking circuit is used for receiving the asynchronous reset signal.
4. The asynchronous wake-up circuit of claim 3, wherein the asynchronous frequency division circuit comprises an N-stage asynchronous frequency divider and a data selector, wherein:
the output end of the N-level asynchronous frequency divider is connected with the input end of the data selector, the output end of the data selector is connected with the first input end of the filter circuit, and the input end of the N-level asynchronous frequency divider is connected with the first output end of the clock source.
5. The asynchronous wake-up circuit of claim 4, wherein the N-stage asynchronous frequency divider is a two-stage asynchronous frequency divider and the data selector is a one-out-of-four data selector, wherein:
the first output end of the second-level asynchronous frequency divider is connected with the first input end of the four-selected-one data selector, the second output end of the second-level asynchronous frequency divider is connected with the second input end of the four-selected-one data selector, the third output end of the second-level asynchronous frequency divider is connected with the third input end of the four-selected-one data selector, the fourth output end of the second-level asynchronous frequency divider is connected with the fourth input end of the four-selected-one data selector, the output end of the four-selected-one data selector is connected with the first input end of the filter circuit, and the input end of the second-level asynchronous frequency divider is connected with the first output end of the clock source.
6. The asynchronous wake-up circuit of claim 4, wherein the filter circuit comprises a first AND gate, a first register, a second register, a third register, and a fourth register, wherein:
the first input end of the first AND gate is connected with the output end of the data selector, the output end of the first AND gate is connected with the clock end of the first register, the output end of the first AND gate is connected with the clock end of the second register, the output end of the first AND gate is connected with the clock end of the third register, the output end of the first AND gate is connected with the clock end of the fourth register, the output end of the first register is connected with the input end of the second register, the output end of the second register is connected with the input end of the third register, and the output end of the third register is connected with the input end of the fourth register;
the second input end of the first and gate is connected with the second output end of the effective edge detection circuit, the output end of the first and gate is connected with the first input end of the awakening generation circuit, the output end of the fourth register is connected with the first input end of the awakening generation circuit, the reset end of the first register is connected with the first output end of the reset control circuit, the reset end of the second register is connected with the first output end of the reset control circuit, the reset end of the third register is connected with the first output end of the reset control circuit, and the reset end of the fourth register is connected with the first output end of the reset control circuit;
the input end of the first register is used for inputting the asynchronous wake-up signal.
7. The asynchronous wake-up circuit of claim 6, wherein the wake-up generation circuit comprises a fifth register, a second and gate, a third and gate, and a fourth and gate, wherein:
the output end of the fifth register is connected with the first input end of the third AND gate, the first input end of the fourth AND gate is connected with the output end of the second AND gate, and the second input end of the fourth AND gate is connected with the output end of the third AND gate;
the input end of the fifth register is connected with the output end of the fourth register, the clock end of the fifth register is connected with the output end of the first AND gate, the first input end of the second AND gate is connected with the output end of the second register, the second input end of the second AND gate is connected with the output end of the third register, the third input end of the second AND gate is connected with the output end of the fourth register, the second input end of the third AND gate is connected with the output end of the fourth register, and the output end of the fourth AND gate is connected with the third input end of the wake-up locking circuit.
8. The asynchronous wake-up circuit of claim 7, wherein the wake-lock circuit comprises an or gate, a sixth register and a synchronization/arbitration logic circuit, wherein:
the input end of the synchronization/judgment logic circuit is connected with the output end of the fourth and gate, the output end of the synchronization/judgment logic circuit is connected with the input end of the sixth register, the clock end of the sixth register is connected with the second output end of the clock source, the output end of the sixth register is connected with the first input end of the or gate, the second input end of the or gate is connected with the first output end of the effective edge detection circuit, and the output end of the or gate is connected with the input end of the clock source;
and the reset end of the sixth register is used for receiving the asynchronous reset signal.
9. The asynchronous wake-up circuit of claim 7, wherein the reset control circuit comprises a fifth and a sixth and gate, wherein:
the output end of the fifth AND gate is connected with the first input end of the sixth AND gate, the second input end of the sixth AND gate is connected with the output end of the fifth register, and the output end of the sixth AND gate is connected with the first input end of the effective edge detection circuit;
the output end of the fifth AND gate is connected with the reset end of the first register, the output end of the fifth AND gate is connected with the reset end of the second register, the output end of the fifth AND gate is connected with the reset end of the third register, the output end of the fifth AND gate is connected with the reset end of the fourth register, and the output end of the fifth AND gate is connected with the reset end of the fifth register; and a first input end of the fifth AND gate is used for receiving the asynchronous reset signal, and a second input end of the fifth AND gate is used for receiving the asynchronous wake-up signal.
10. The asynchronous wake-up circuit of claim 8 or 9, wherein the active edge detection circuit comprises a buffer and a seventh register, wherein:
the output end of the buffer is connected with the clock end of the seventh register, the input end of the seventh register is grounded, the reset end of the seventh register is connected with the output end of the sixth and gate, the output end of the seventh register is connected with the second input end of the or gate, and the output end of the seventh register is connected with the second input end of the first and gate;
the input end of the buffer is used for receiving the asynchronous wake-up signal.
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