CN204423297U - A kind of SOC (system on a chip) in order to realize Systematical control and power management - Google Patents

Abstract

The purpose of this utility model is to provide a kind of SOC (system on a chip) in order to realize Systematical control and power management, in order to realize the object of Systematical control and power management.Comprise: the system control module be connected with a bus bridge by a bus and some functional modules; The built-in configuration register in order to control the enable of described functional module and frequency of operation of described system module, the configuration register of described functional module built-in frequency control and module shuts down in order to realize the corresponding function module respectively.In SOC (system on a chip) of the present utility model, system control module as one from equipment connection to SOC (system on a chip) in ahb bus on, central processing unit is configured system control module by instruction, thus realizes various system control function.Compared with prior art, without the need to increasing design cost or cost of products can realize Systematical control and managing power consumption.

Description

A kind of SOC (system on a chip) in order to realize Systematical control and power management

Technical field

The utility model relates to a kind of SOC (system on a chip), particularly relates to the SOC (system on a chip) comprising system control module and power management module, belongs to integrated circuit (IC) design technical field.

Background technology

At present, along with increasing of various information Systematical control application apparatus, the application of SOC (system on a chip) (System on Chip) is also more and more extensive.This SOC (system on a chip), there is microcontroller and micro-processor kernel module, digital signal processor module, the memory module of embedding, external communication interface module, power supply provide and power managed module etc., form in one piece of integrated circuit, there is the data-handling capacity of 32 or 64, and work in certain temperature range, therefore, generally adopt in all kinds of control system such as Internet of Things and Industry Control terminal, Information Collecting & Processing and message transfer system.

SOC (system on a chip), because of the difference of its control mode and workflow, the work efficiency of its inner institute management object is also different.In addition, as the SOC (system on a chip) of general type, also have in SOC (system on a chip) control the power management function of parts, the mode of its power management, method, relevant to management object, also the method to taked is relevant, and these methods reduce the effect of power consumption by having influence on SOC (system on a chip) itself.

In the SOC (system on a chip) of prior art, on the operative orientation that power management is energy-saving and cost-reducing, be all the dormancy of employing module, close the methods such as useless clock, low-frequency operation.Therefore, in specific implementation, some SOC (system on a chip) take following way to be: one is in SOC (system on a chip), arrange a power source management controller specially, and this module in charge implements power management, to reduce energy consumption to other module in system; Another kind of way is then applying in the concrete equipment that this SOC (system on a chip) forms, namely outside SOC (system on a chip), then increasing other chips of the power management being used for this equipment.Although these two kinds of methods all can reach the effect of power management, but all there is the phenomenon increasing cost, the former adds design cost in design process, too increases the manufacturing cost of SOC (system on a chip), and the specific product applied in SOC (system on a chip) adds cost of products to the latter.

Utility model content

For above-mentioned prior art Problems existing, the utility model provides a kind of SOC (system on a chip), in order to realize the object of Systematical control and power management.

For achieving the above object, the technical scheme that the utility model is taked is:

In order to realize a SOC (system on a chip) for Systematical control and power management, comprising: the system control module be connected with a bus bridge by a bus and some functional modules; The built-in configuration register in order to control the enable of described functional module and frequency of operation of described system module, the configuration register of described functional module built-in frequency control and module shuts down in order to realize the corresponding function module respectively.

Further, described bus is an ahb bus.

Further, described system control module also comprises an ahb bus interface.

Further, described system control module is in order to clock signal, reset signal, IO multiplexed signals and block configuration signal.

Further, the central processing unit be connected with bus bridge by an AXI bus is also comprised.

Further, described central processing unit is in order to system control module transfer instruction.

Further, described central processing unit is a Loongson processor.

Further, described functional module comprises: the dma controller be connected with bus bridge by described ahb bus, NANDFlash controller, interruptable controller, SPI1 host interface, ethernet mac controller, USB2.0OTG controller and external static memory interface.

Further, described functional module also comprises: the I2S host interface be connected with bus bridge by an APB bus, I2C host interface, WatchDog Timer, timer × 4, UART × 8, GPIO, matrix keyboard, PWM and rotary encoder interface, 7816 interface × 2, GPIO (General Purpose Input Output), ADC interface and PS2 interface × 2.

Further, described functional module also comprises: PLL and clock reset circuit on the DDR2 controller be connected with bus bridge by an AXI bus, sheet.

The major function of described system control module is to manage the start-up mode management of whole SOC (system on a chip), Clock management, reset management and power managed.Certainly, the system control functions such as IO (Input/Output I/O) reuse management, bus error management, module configuration managing are also comprised.System control module is the control axis of whole SOC (system on a chip).Its control mode is: the mode 1, by carrying out instruction configuration to the configuration register of system control module can realize desired control function; 2, the controlling functions realizing expecting is set by on-chip system chip pin.

The major function that system control module possesses is: support 3 kinds of start-up mode; PLL (Phase Locked Loop, phase synchronous loop) output frequency is configurable; Each module clock can separate configurations; All modules all can carry out instruction reset; As required, the clock of each module can be opened or close by instruction; Support CPU (Central Processing Unit, central processing unit) park mode; Support that IO is multiplexing; Support to carry out system-level configuration to each module.

By taking technique scheme, system control module as one from equipment connection to SOC (system on a chip) in ahb bus on, central processing unit is configured system control module by instruction, thus realizes various system control function.Compared with prior art, without the need to increasing design cost or cost of products can realize Systematical control and managing power consumption.

Accompanying drawing explanation

Fig. 1 is the structured flowchart of SOC (system on a chip) of the present utility model;

Fig. 2 is the structured flowchart of system control module in SOC (system on a chip) of the present utility model;

Fig. 3 is the timing topology figure of system control module in SOC (system on a chip) of the present utility model;

Fig. 4 is the PLL structured flowchart of system control module in SOC (system on a chip) of the present utility model;

Fig. 5 is the schematic flow sheet of the reset schemes of system control module in SOC (system on a chip) of the present utility model;

Fig. 6 is the park mode transition diagram of system control module in SOC (system on a chip) of the present utility model.

Embodiment

Below in conjunction with accompanying drawing, the utility model is described further.

A kind of SOC (system on a chip) that the utility model provides as described in Figure 1.In described SOC (system on a chip), contain the system control module be connected with AXI bus with bus bridge by ahb bus, further comprises PLL, clock-reset circuit and AXI bus on Godson central processing unit, DDR2 (Double DataRate 2) controller, sheet.

Described SOC (system on a chip) is by bus bridge and ahb bus, be connected to DMA (Direct Memory Access, direct memory access) controller, NAND Flash controller, interruptable controller, SPI1 (Serial Peripheral Interface, Serial Peripheral Interface (SPI)) host interface, ethernet mac (Media Access Control, data link layer) controller, USB (UniversalSerial Bus, USB (universal serial bus)) 2.0OTG (On-The-Go) controller, external static memory interface.

Described SOC (system on a chip) is by bus bridge and APB (Advanced Peripheral Bus, peripheral bus) bus, be connected to I2S host interface, I2C host interface, WatchDog Timer, timer × 4, UART × 8, GPIO, matrix keyboard, PWM and rotary encoder interface, 7816 interface × 2, GPIO and ADC interface, PS2 interface × 2.

System control module as one from equipment connection to SOC (system on a chip) in ahb bus on, central processing unit adopts domestic Loongson processor, is configured system control module by instruction, thus realizes various system control function.System control module comprises: ahb bus interface, configuration register etc.The start-up mode management that this control module passes through exported clock signal, reset signal, IO multiplexed signals, block configuration signal achieve system, module resets management, power supply power consumption management.

The start-up mode management of described system control module comprises: NAND Flash starts; SPI Flash starts; NOR Flash starts.

Can the start-up mode of configuration module by nfcsn_bootmode0 and pwmout3_bootmode1_psclk0 two pins of control module, concrete configuration situation is as shown in table 1.These two start-up mode configuration pin are only in the reset state for configuring start-up mode, and after control module exits reset mode, these two pins will be used as common functional pin.

Control module start-up mode configures

Configuration pin

Start-up mode

{bootmode1,bootmode0}
		00	Retain
01	NOR Flash starts
		10	SPI Flash starts
11	NAND Flash starts

NAND Flash starts, and is the first-selected Starting mode of control module under normal circumstances; Start to realize NAND Flash, the NAND Flash controller of control module has the sheet internal buffer of 4KB, when being configured to NAND Flash start-up mode, after reset, NAND Flash controller is transported to the data of first piece of first page in NAND Flash particle in 4KB sheet internal buffer automatically, and CPU will perform start-up code from 4KB sheet internal buffer.

SPI Flash starts, and there is provided a kind of optional Starting mode, allows application system to deposit in the NOR Flash of SPI interface by the start-up code of control module, maximum support 4MB start-up code.Because SPI interface only needs 4 chip interface signals, therefore SPI Starting mode can reduce system cost, is applicable to other low-cost design scheme.

NOR Flash starts, to control module external static memory interface (EMI interface, External MemoryInterface) provide another kind of optional Starting mode, allow control module to start from 8 NOR Flash of conventional SRAM interface.The EMI interface of control module supports 3 chip selection signals, and each chip selection signal supports maximum 1MB address space.

The structured flowchart of system control module as shown in Figure 2.

The start-up mode management of described system control module comprises: NAND Flash (adopting a kind of non-volatile flash memory of non-linear macroelement pattern) starts; SPI Flash (serial peripheral interface, serial peripheral equipment flash memory) interface starts; NOR Flash (nonvolatile flash memory) starts.

Described Clock management, comprises timing topology, PLL configuration and clock division three ingredients.

According to different sources, the internal clocking of control module can be divided three classes:

First kind clock is directly inputted by chip exterior and is supplied to corresponding module, the reception of such as ethernet mac controller and tranmitting data register, EJTAG debug clock JTCK etc.;

Equations of The Second Kind clock is directly provided by the special PHY of module itself, the clock of such as USB;

3rd class clock, derives from the system PLL in sheet, and can configure divide ratio and whether enable by instruction, the difference according to application can be configured to meet different performances or power consumption demand flexibly.As previously mentioned, most clock all directly or secondary source in PLL.

The frequency division of clock: the inner most clock of system control module all carries out direct or indirect frequency division by pll clock and obtains.According to the different characteristics of module, some clock carries out integral frequency divisioil by source clock and obtains, and some clock carries out even frequency division by source clock and obtains.For given divide ratio value coefficient, the frequency values after system control module integral frequency divisioil and even frequency division adopts the computing formula determined, wherein integral frequency divisioil does not support the situation of a frequency division.

The reset management of described system control module comprises:

Reset source: system control module has six kinds of sources that reset: electrification reset; The system reset of chip pin input; Watchdog circuit time-out resets; Chipset level commands resets; Module level instruction resets; EJTAG (Enhanced Joint Test ActionGroup) debug reset.

The power supply power consumption management of described system:

In SOC (system on a chip), corresponding configuration register is provided with in each functional module comprising system control module, wherein most configuration register is included in functional module inside, but also has partial configuration function to be configured by the configuration register of system control module.In the environment that the SOC (system on a chip) of reality is applied, in the specific works process realizing information acquisition, process, transmission, in SOC (system on a chip), the determination of the enable and frequency of operation of each functional module corresponding realizes controlling by the configuration register in system control module, reduces the power consumption of overall modules with this; And concrete in running order under module, then realize the frequency control of this module and the shutoff of this module by the configuration register in this module, be in optimum Working to make these modules.In a word, realize the closedown of module, dormancy and fall low-frequency mode of operation, inner and reduce the energy-saving and cost-reducing object of SOC (system on a chip) outside institute control parts to realize reducing SOC (system on a chip), be realized with the configuration work in combination mode of the configuration register being dispersed in other each module by the configuration register of system control module.

Power supply power consumption management comprises following Three models:

Module is closed: in the control module, except AXI (Advanced eXtensible Interface, a kind of bus on chip agreement towards high-performance, high bandwidth, low delay) bus and AHB (Advanced High-performance Bus, Advanced High-Performance Bus) bus keeps the state that works all the time, and every other module can be enable with closedown separately by the configuration of register.

Low-frequency operation: in control module, most clock is all obtained by one-level or multistage frequency division by PLL output clock, all clocks can carry out frequency dividing control independently, PLL itself also can carry out meticulous frequency control by instruction simultaneously, therefore for different application scenarios, fine-grained control can be carried out to pll clock and each module clock, each clock is made to operate in the low-limit frequency meeting performance requirement, instead of simply extensive operate under a higher frequency, the power consumption of control module can be remained on a lower level like this.

Park mode: when control module CPU performs dormancy instruction WAIT, CPU will enter dormancy waiting status, and cpu clock is closed, and no longer perform any instruction, only can consume little electricity leakage power dissipation.

The timing topology of SOC (system on a chip) as shown in Figure 3.

All internal clocks except EJTAG debug clock and mutual relationship thereof is denoted in figure; Highest frequency clock is pll clock, is 500MHZ in typical case, and this clock is directly as the clock of DDR2PHY; As the work clock of AXI bus clock and CPU, DDR2 controller after pll clock 2 frequency division, as the work clock of ahb bus clock and some equipment after pll clock integral frequency divisioil, as APB bus clock after ahb bus clock integral frequency divisioil; Except MAC, in other sheets, the clock of equipment all obtains for source clock carries out frequency division with pll clock, ahb bus clock or APB bus clock etc.

Preferably, in order to reduce system cost, the reference clock of PLL both can come from external pin clock, the 12MHZ clock that also can provide from USB PHY sheet internal oscillator; Due to for selecting the signal pins clksel of reference clock with pull down resistor, therefore under default situations control module using use USB PHY to provide 12MHZ clock as PLL reference clock.

The structured flowchart of the PLL configuration of SOC (system on a chip) as shown in Figure 4.

SOC (system on a chip) have employed PLL in high-precision sheet, can provide reliable and stable clock source for whole chip.The reference frequency output of PLL is 62.5MHZ ~ 1500MHZ.

Configuration input signal M, N, OD are used for being configured PLL output frequency, and bypass, then for bypass PLL, makes PLL output clock equal the reference clock inputted.

SOC (system on a chip) has three clock configuration pin can be configured PLL output frequency value.

Preferably, when giving tacit consent to the 12MHZ reference clock adopting USB PHY to provide, according to different Configuration Values, PLL can export the different frequency of 600MHZ, 534MHZ, 500MHZ, 468MHZ, 400MHZ, 333MHZ, 267MHZ, 200MHZ etc. 8 kinds.These three clock configuration pin are nfcle_clkcfg0, nfale_clkcfg1 and nfren_clkcfg2_emioen.

Preferably, when adopting sheet External Reference clock, the M/N/OD value corresponding according to three clock configuration pin and reference clock frequency value, can calculate PLL output frequency now.Three clock configuration pin of PLL and functional pin carry out multiplexing, and their configuring condition can not affect the normal use of functional pin.

Preferably, for given reference clock frequency, except the PLL output frequency using three clock configuration pin configuration generations 8 kinds different, can also carry out more meticulous configuration by instruction programming pll clock configuration register SYSCTL_PLL_FREQ, and the mode priority of instruction programming configuration PLL is higher than the configuration of clock configuration pin.

Preferably, except pll clock configuration register can be used for configuration PLL output frequency, whether external command can also control to arrange bypass PLL with status register SYSCTL_PLL_CSR by PLL and be in the lock state with inquiry PLL.

The clock division structure of SOC (system on a chip) as shown in Figure 3, we it can also be seen that:

For adapting to each module different operating frequency needs, clock division takes integral frequency divisioil to obtain, or carries out even frequency division by source clock and obtain.

Preferably, in actual applications, demand and the factor such as performance, power consumption of disparate modules is considered, can the suitable PLL frequency of option and installment one; According to selected PLL frequency, select suitable divide ratio to produce the target frequency expected respectively for disparate modules.

Preferably, except initialization procedure, also can configuration change clock division coefficient as required in operational process, such as reduce when module is idle module clock frequency even closing module clock to reduce power consumption.

The reset management of described system control module comprises:

Control module one has six kinds of sources that reset: electrification reset; The system reset of chip pin input; Watchdog circuit time-out resets; Chip-scale external reset; Module level resets; EJTAG debug reset.

The overall plan of reset generation circuit as shown in Figure 5.

Preferably, in order to reduce system cost, control module is integrated with electrify restoration circuit in chip.PLL after power-up, inner VCO needs the regular hour just can lock output, therefore whole chip just must can start normal work after PLL stable output, and before this, internal circuit must be in reset mode and cause faulty operation to avoid clock instability.Be in the lock state in order to ensure PLL after electrification reset, control module have employed lock control circuit when electrification reset, can provide extra time-delay reset after electrification reset, ensure that reset terminate after PLL started normal work.

In the reset schemes diagram of Fig. 5, sys_rstn refers to the systematic reset signal from chip pin input, can be used for the hand-reset of plate level, also can external electrify restoration circuit; Owing to being integrated with electrify restoration circuit in control module, therefore sys_rstn reset signal can not be re-used in maturation application plate.Wdt_resetn refers to the reset signal that watchdog circuit time-out causes, if do not use watchdog circuit in certain application, then wdt_resetn can not work.EJTAG debug reset ejtag_resetn comes from EJTAG TAP controller, and debug host controls by ejtag_resetn the whole chip that resets.Chip-scale external reset and module level reset then for the reset of full chip with certain module.Except module level resets, any one reset signal in all the other five reset source can reset whole chip.

Preferably, control module provides chip-scale and module level two kinds resets, and can further facilitate the needs of applications.Control module provides two reseting register SYSCTL_MOD_SRST0 and SYSCTL_MOD_SRST1, and external command can produce the reset of expectation by these two registers of configuration.

When external command configuration produces chip-scale reset, whole module will all reset, and all software and hardwares start anew to run again.When instruction configure certain module reset time, then only have this module to be reset, other modules can not be affected.

System control module provides the measure reducing chip power-consumption, for embody rule, by the mode to configuration register configuration-direct content, provide and close useless module, reduce the running frequency of full chip or functional module, the measure of park mode, reduce the power consumption of whole chip, and reduce the power consumption of SOC (system on a chip) institute control assembly.

Such as, in system control module, GPIO-ENA register wherein, when its GPIO control bit is " 1 ", is enable GPIO clock, correspondingly, when this position is " 0 ", then closes GPIO clock.

Example again: in system control module, SYSCTL_CLKDIV_APB wherein, its function arranges APB bus clock divide ratio, at its clkdiv bit field, when its numerical value is " 001 ", for 2 frequency divisions of clock frequency, during for " 010 ", be 3 frequency divisions of clock frequency, until when being " 111 ", for 8 frequency divisions of clock frequency, in order to the clock frequency of control APB bus work.

Example again: arranging ahb bus clock division coefficient, take pll clock as source clock, carries out frequency division under the control of its register SYSCTL_CLKDIV_AHB, also by clkdiv bit field, obtains the clock signal of this bus.

Module is closed

In the control module, except AXI bus and ahb bus keep the state that works all the time, every other module can be enable with closedown separately; After closedown module, except electricity leakage power dissipation, this module will no longer consume any electric flux.

Preferably, for the application that certain is concrete, useless module can be closed on the one hand, in operational process, a lot of module always can't be in running status usually on the other hand, when certain module is in the stage not needing to run, can close these modules equally, such as a module just needs transceiving data once in a while, then closing this module in the inoperative stage significantly will reduce power consumption.

Low-frequency operation

The inner most clock of control module is all obtained by one-level or multistage frequency division by PLL output clock, nearly all clock can carry out frequency dividing control independently, PLL itself also can carry out meticulous frequency control by instruction simultaneously, therefore for different application scenarios, fine-grained control can be carried out to pll clock and each module clock of SOC (system on a chip), each clock is made to operate in the low-limit frequency meeting performance requirement, instead of simply extensive operate under a higher frequency, the power consumption of integral module can be remained on a lower level like this.

Preferably, some functional module may need to remain on duty to maintain normal function always, but often only just need full speed running when carrying out the valid functions such as such as data transmission, other most time will be in idle waiting state and not need full speed running, assignment by the configuration register of this module makes it can reduce the frequency of operation of module when idle waiting state, make it bottom line and maintain running status, then can reduce the power consumption of functional module to greatest extent.

Park mode

The sleep mode conversion of system control module as shown in Figure 6.

When the CPU of control module performs dormancy instruction WAIT, CPU will enter dormancy waiting status, and cpu clock is closed, and no longer perform any instruction, only can consume little electricity leakage power dissipation; When CPU enters dormancy waiting status, CPU can wake up by any interruption, and CPU exits dormancy waiting status and starts to carry out interrupt processing.Fig. 5 gives the diagram of the State Transferring between normal mode and park mode.

When performing WAIT instruction, before CPU enters park mode, all instructions before WAIT instruction all can be performed complete, and all instructions after WAIT instruction all can not be performed, and the instruction after these WAIT instructions will continue to perform after CPU exits dormant state.If just interrupted when performing WAIT instruction, then CPU no longer will enter park mode.

Preferably, can be triggered by suitable interrupt request upon entering a sleep mode to make CPU and exit park mode, each modules interrupts function and interruptable controller should be configured to a state expected by CPU before performing WAIT instruction.

Preferably, the interruptable controller of control module can receive and send interrupt request under the state not having clock, and therefore CPU can close the clock of interruptable controller to reduce power consumption further before entering park mode.If certain functional module can accept external event when module is closed and send interruption, such as matrix keyboard can receive key information when module is closed and send wake-up interrupts, then under limiting case, CPU can close before entering sleep mode all can pent clock, now the control module clock that only has pll clock, AXI bus clock and ahb bus clock etc. few is in running order, and whole chip will be in a kind of extremely low power dissipation state.When there is certain wake-up interrupts, such as external key triggers matrix keyboard wake-up interrupts, then CPU will exit park mode, and the clock according to circumstances recovering each module starts normal operation.

Claims (10)

1. in order to realize a SOC (system on a chip) for Systematical control and power management, it is characterized in that, comprising: the system control module be connected with a bus bridge by a bus and some functional modules; The built-in configuration register in order to control the enable of described functional module and frequency of operation of described system module, the configuration register of described functional module built-in frequency control and module shuts down in order to realize the corresponding function module respectively.

2. as claimed in claim 1 in order to realize the SOC (system on a chip) of Systematical control and power management, it is characterized in that, described bus is an ahb bus.

3. as claimed in claim 2 in order to realize the SOC (system on a chip) of Systematical control and power management, it is characterized in that, described system control module also comprises an ahb bus interface.

4. as claimed in claim 1 in order to realize the SOC (system on a chip) of Systematical control and power management, it is characterized in that, described system control module is in order to clock signal, reset signal, IO multiplexed signals and block configuration signal.

5. as claimed in claim 1 in order to realize the SOC (system on a chip) of Systematical control and power management, it is characterized in that, also comprise the central processing unit be connected with bus bridge by an AXI bus.

6. as claimed in claim 5 in order to realize the SOC (system on a chip) of Systematical control and power management, it is characterized in that, described central processing unit is in order to system control module transfer instruction.

7. the SOC (system on a chip) in order to realize Systematical control and power management as described in claim 5 or 6, is characterized in that, described central processing unit is a Loongson processor.

8. as claimed in claim 3 in order to realize the SOC (system on a chip) of Systematical control and power management, it is characterized in that, described functional module comprises: the dma controller be connected with bus bridge by described ahb bus, NAND Flash controller, interruptable controller, SPI1 host interface, ethernet mac controller, USB2.0OTG controller and external static memory interface.

9. as claimed in claim 8 in order to realize the SOC (system on a chip) of Systematical control and power management, it is characterized in that, described functional module also comprises: the I2S host interface be connected with bus bridge by an APB bus, I2C host interface, WatchDog Timer, timer × 4, UART × 8, GPIO, matrix keyboard, PWM and rotary encoder interface, 7816 interface × 2, GPIO, ADC interface and PS2 interface × 2.

10. as claimed in claim 9 in order to realize the SOC (system on a chip) of Systematical control and power management, it is characterized in that, described functional module also comprises: PLL and clock reset circuit on the DDR2 controller be connected with bus bridge by an AXI bus, sheet.