CN109753313B - Device and method for waking up processor - Google Patents
Device and method for waking up processor Download PDFInfo
- Publication number
- CN109753313B CN109753313B CN201910007122.6A CN201910007122A CN109753313B CN 109753313 B CN109753313 B CN 109753313B CN 201910007122 A CN201910007122 A CN 201910007122A CN 109753313 B CN109753313 B CN 109753313B
- Authority
- CN
- China
- Prior art keywords
- reference current
- processor
- oscillator
- system clock
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The invention relates to a device for waking up a processor, wherein the processor is capable of operating in the following modes: a standby mode in which the processor is in a standby state; and an operating mode in which the processor is capable of operating at a higher load than during an interrupt phase in which the processor is awakened from the standby mode and enters the operating mode; the device comprises: a first bias circuit configured to provide a first reference current to the oscillator during an interruption phase; a second bias circuit configured to provide a second reference current to the oscillator in the run mode, wherein the second reference current is less than the first reference current and the second reference current has a precision greater than the first current; and an oscillator configured to provide a system clock according to the provided reference current. Furthermore, the invention relates to a method for a ring processor. By the invention, high-speed awakening of the processor can be realized, and low power consumption and high system clock precision are kept.
Description
Technical Field
The present invention relates generally to the field of processors, and more particularly, to an apparatus for waking up a processor. The invention further relates to a method for waking up a processor.
Background
In general, a processor enters a sleep mode when idle, in which the processor operates at a very low power to reduce power consumption. To wake up a processor, a single internal RC oscillator (RCOSC) is currently employed to generate a system clock to wake up the processor as well as other peripheral circuits.
The ideal case for waking up a processor is to wake up the processor at high speed while maintaining low power consumption and high accuracy of the system clock. However, in practice, in order to wake up the processor at high speed, a large reference current must be used, which results in high power consumption, and thus cannot meet the requirements of many low power consumption application scenarios. Moreover, the system clock requires a certain time to achieve a high accuracy, which in turn prevents a high-speed start-up.
There is a need for a wake-up mechanism with low power consumption, high wake-up speed and high clock accuracy.
Disclosure of Invention
Proceeding from the prior art, the object of the present invention is to provide an apparatus and a method for waking up a processor, by means of which apparatus or method a high-speed wake-up of the processor can be achieved while maintaining a low power consumption and a high system clock accuracy.
In a first aspect of the invention, this task is solved by a device for waking up a processor, wherein said processor is capable of operating in the following mode:
a standby mode in which the processor is in a standby state; and
a run mode in which the processor is able to run at a higher load than during an interrupt phase in which the processor is woken up from a standby mode and enters a run mode;
the device comprises:
a first bias circuit configured to provide a first reference current to the oscillator during an interruption phase;
a second bias circuit configured to provide a second reference current to the oscillator in the run mode, wherein the second reference current is less than the first reference current and the second reference current has a precision greater than the first current; and
an oscillator configured to provide a system clock for waking up a processor according to a provided reference current, wherein accuracy of the system clock output by the oscillator has a positive correlation with accuracy of the provided reference current, and a start-up speed of the oscillator has a positive correlation with a magnitude of the provided reference current.
In one embodiment of the invention, it is provided that the processor is a microcontroller unit MCU, a general-purpose processor or a special-purpose processor, and the oscillator is an RC oscillator RCOSC. It should be noted here that the present invention may be applied to other processors, especially processors requiring low power consumption, high wake-up speed, and high clock accuracy, such as special purpose processors, general purpose processors, and the like.
In a preferred embodiment of the invention, it is provided that the length of the interruption phase is 1 to 10. mu.s. By this preferred solution a good compromise between high speed, low power consumption and high accuracy can be achieved, because the inventors have found that a processor or system needs a high accuracy and low power consumption system clock only after a few mus from the start of the wake-up, i.e. from the end stage. The above compromise can thus be better achieved by configuring the length of the interruption phase.
In a further preferred embodiment of the invention, it is provided that the oscillator comprises an oscillating circuit, which comprises:
the three inverters are connected in series and comprise a first inverter, a second inverter and a third inverter, wherein the input end of the first inverter is connected with the current source, and the output end of the third inverter outputs the system clock;
three capacitors corresponding to the three inverters, wherein one end of each capacitor is connected to a line between the two inverters and the second end is grounded;
the multiplexer receives a first reference current sent by the first bias circuit and a second reference current sent by the second bias circuit, selects the first reference current and the second reference current and outputs the selected reference current; and
a current source that receives the selected reference current and delivers the current output by the current source to the input of the oscillator.
With this preferred arrangement, a simple configuration of the dual oscillator can be realized, thereby simplifying the circuit and increasing the system clock generation speed.
In one embodiment of the invention, it is provided that the accuracy of the reference current includes the stability of the reference current. The accuracy of the reference current may be manifested, for example, as the stability, i.e., stationarity, of the amplitude of the current, the sensitivity of the current to temperature and voltage variations, and so forth.
In a second aspect of the invention, the aforementioned task is solved by a method for waking up a processor, wherein the processor is capable of operating in the following mode:
a standby mode in which the processor is in a standby state; and
a run mode in which the processor is able to run at a higher load than during an interrupt phase in which the processor is woken up from a standby mode and enters a run mode;
the method comprises the following steps:
providing a first reference current to the oscillator during an interruption phase;
providing a second reference current to the oscillator in the run mode, wherein the second reference current is less than the first reference current and the second reference current has a precision greater than the first current;
generating a corresponding system clock according to the provided reference current; and
waking up the processor using the system clock.
In a preferred aspect of the invention, it is provided that the generation of the respective system clock from the provided reference current comprises:
generating a first system clock at a first speed from a first reference current;
a second system clock is generated at a second speed based on the second reference current, wherein the second speed is less than the first speed and the accuracy of the second system clock is greater than the accuracy of the first system clock.
By the optimal scheme, high-speed starting, high system clock precision and low power consumption can be realized simultaneously.
The invention has at least the following beneficial effects: (1) by providing a large reference current with low accuracy in the interrupt phase and a small reference current with high accuracy in the run phase, fast wake-up in the interrupt phase and low power consumption and high system clock accuracy in the run phase can be achieved, because the inventors found that the system is insensitive to both power consumption and clock accuracy at the very beginning of wake-up (interrupt phase, lasting about a few μ s), at which time high-speed wake-up with high oscillator power consumption (i.e. large reference current) and low system clock accuracy can be achieved; in the run phase (immediately after the interrupt phase), the system requires a high-precision system clock and a low-power oscillator; (2) since the oscillator needs a certain time to generate the high-precision system clock, the oscillator can provide the high-precision system clock in the running mode after the interruption stage to meet the running requirement of the system.
Drawings
The invention is further elucidated with reference to specific embodiments in the following description, in conjunction with the appended drawings.
Fig. 1 shows the principle of a scheme for waking up a processor according to the invention.
FIG. 2 shows a schematic diagram of an apparatus for waking up a processor according to the invention; and
fig. 3 shows a system clock of an apparatus for waking up a processor according to the present invention.
Detailed Description
It should be noted that the components in the figures may be exaggerated and not necessarily to scale for illustrative purposes. In the figures, identical or functionally identical components are provided with the same reference symbols.
In the present invention, the embodiments are only intended to illustrate the aspects of the present invention, and should not be construed as limiting.
In the present invention, the terms "a" and "an" do not exclude the presence of a plurality of elements, unless otherwise specified.
It is further noted herein that in embodiments of the present invention, only a portion of the components or assemblies may be shown for clarity and simplicity, but those of ordinary skill in the art will appreciate that, given the teachings of the present invention, required components or assemblies may be added as needed in a particular scenario.
It is also noted herein that, within the scope of the present invention, the terms "same", "equal", and the like do not mean that the two values are absolutely equal, but allow some reasonable error, that is, the terms also encompass "substantially the same", "substantially equal".
The numbering of the steps of the methods of the present invention does not limit the order of execution of the steps of the methods. Unless specifically stated, the method steps may be performed in a different order.
Furthermore, although the present invention is explained by taking a micro control unit MCU as an example, this is only exemplary. Rather, the present invention may be used with other processors as well.
Fig. 1 shows the principle of a scheme for waking up a processor according to the invention.
The solution of the invention is based on the following insights of the inventors: the processor generally operates as follows, in the operation mode 1, the processor performs various operations with higher load and higher clock precision, and power consumption is needed; when the processor enters a standby mode 2 after receiving a standby instruction, the processor performs only the most basic operation with extremely low power consumption; when the processor is interrupted to execute corresponding operation, the processor is in an interruption phase, namely a awakened phase, after the interruption phase, the processor runs in a running mode with higher load and higher clock precision, and in the interruption phase, namely when the processor is just awakened, the processor is insensitive to power consumption and insensitive to precision, only high-speed awakening is needed, but in the running mode after a period of time, such as several us, the system only needs a high-precision system clock and low power consumption, so that in the invention, the requirements of high-speed awakening, low power consumption and high-precision system clock of the system can be met by adopting large low-precision reference current (also called bias current) in the interruption phase and small high-precision reference current in the running phase.
Fig. 2 shows a schematic diagram of an apparatus 100 for waking up a processor according to the invention.
As shown in fig. 1, the apparatus 100 for waking up a processor is, for example, used for providing a system clock for the processor (not shown) in a sleep mode, i.e., providing the system clock for waking up the processor. The processor includes various processors such as a micro control unit MCU, a general purpose processor, a special purpose processor, and the like. The processor is capable of operating in the following modes:
standby mode, in which the processor is in a standby state. For example, the standby mode may include various sleep modes such as a deep sleep mode and a sleep mode, and various ultra-low power modes in which the processor performs the most basic operation with extremely low power consumption or is in a sleep state.
A run mode in which the processor can run at a higher load than in an interrupt phase in which the processor is woken up from the standby mode and enters the run mode. The operation modes include, for example, a full load mode, a normal operation mode, and the like in which various operations can be normally performed. The interrupt phase refers to a phase in which the processor is woken up to perform some task. In the present invention, the interruption phase may last for a certain period of time, e.g. 1 to 10 μ s.
The apparatus 100 comprises:
a first bias circuit 101 configured to provide a first reference current to the oscillator 103 during the interruption phase. The first bias circuit 101 is, for example, a low-precision, large-current bias circuit.
A second bias circuit 102 configured to provide a second reference current to the oscillator 103 in the run mode, wherein the second reference current is smaller than the first reference current and the accuracy of the second reference current is greater than the accuracy of the first current. Since the second reference current is smaller than the first reference current, the power consumption of the oscillator in the run mode is smaller than the power consumption of the oscillator in the interrupt phase, and since the first reference current is larger, the oscillator can be started up faster. In addition, the precision of the second reference current is higher than that of the first current, so that the precision of the oscillator in the running mode is higher, the running requirement can be met, the precision of the first current is lower, and the cost can be saved. The second bias circuit 102 may be started substantially simultaneously with the first bias circuit 101 and a low precision reference current is first provided by the first bias circuit 101 and a high precision reference current is provided by the second bias circuit 102 after settling.
An oscillator 103 configured to provide a system clock for waking up the processor in dependence on the provided reference current. The oscillator is, for example, an RC oscillator. The oscillator 103 may include a single oscillation circuit that can generate a high-precision system clock from a high-precision reference current and a lower-precision system clock from a lower reference current, and can also be started quickly in the case of a large current. In other embodiments, however, oscillator 103 includes multiple oscillation circuits, such as a first oscillation circuit and a second oscillation circuit, where the first oscillation circuit receives a first reference current from first bias circuit 101 and the second oscillation circuit receives a second reference current from second bias circuit 102, such that the first oscillation circuit has a higher start-up speed (and higher power consumption) than the second oscillation circuit and the accuracy of the system clock generated by the second oscillation circuit is greater than the accuracy of the system clock generated by the first oscillation circuit. The output frequency of the oscillator 103 (i.e. the frequency of the system clock) is related to the reference current, which is high if the current is large, and low if the current is small. The accuracy, e.g. stability, of the reference current will determine the stability of the output frequency of the oscillator.
The oscillator 103 in the embodiment of fig. 2 is described in detail below.
The oscillator 103 includes an oscillation circuit including three inverters 1031, 1032, 1033 connected in series and capacitors 1034, 1035, 1036 corresponding to the three inverters. The multiplexer 105 receives a first reference current 1011 from the first bias circuit 101 and a second reference current 1021 from the second bias circuit 102, the multiplexer 105 selects the first reference current 1011 and the second reference current 1021 and outputs a selected reference current 1051, the current source 104 receives the selected reference current 1051, and the output current of the current source 104 is transmitted to the input terminal of the oscillator 103.
The input of oscillator 103 is controlled by controlling the selection of multiplexer 105. For example:
in the standby mode, the processor is in the standby state, and the multiplexer 105 is controlled not to select the first reference current 1011 and the second reference current 1021;
during the interrupt phase, where the processor requires a low precision current, the multiplexer 105 is controlled to select the first reference current 1011;
in the run mode, the processor requires a high precision current, controlling the multiplexer 105 to select the second reference current 1021.
Table 1 below shows a reference comparison of the first bias circuit 101 or the first RCOSC or the second bias circuit 102 or the second RCOSC.
TABLE 1 comparison of parameters of first and second bias circuits (RCOSC)
The invention has at least the following beneficial effects: (1) by providing a large reference current with low accuracy in the interrupt phase and a small reference current with high accuracy in the run phase, fast wake-up in the interrupt phase and low power consumption and high system clock accuracy in the run phase can be achieved, because the inventors found that the system is insensitive to both power consumption and clock accuracy at the very beginning of wake-up (interrupt phase, lasting about a few μ s), at which time high-speed wake-up with high oscillator power consumption (i.e. large reference current) and low system clock accuracy can be achieved; in the run phase (immediately after the interrupt phase), the system requires a high-precision system clock and a low-power oscillator; (2) since the oscillator needs a certain time to generate the high-precision system clock, the oscillator can provide the high-precision system clock in the running mode after the interruption stage to meet the running requirement of the system.
Fig. 3 shows a system clock of an apparatus for waking up a processor according to the present invention.
As shown in fig. 3, the present invention can combine the advantages of high speed low precision bias circuit 101 and high precision bias circuit 102 to meet the system's requirements for low power consumption, high wake-up speed, and high clock precision.
In fig. 3, the system clock is provided by oscillator I ROSC2 in the interrupt mode and oscillator ICOSC1 in the run mode. Therefore, the invention can meet the requirements of the system on low power consumption, high awakening speed and high clock precision.
Although some embodiments of the present invention have been described herein, those skilled in the art will appreciate that they have been presented by way of example only. Numerous variations, substitutions and modifications will occur to those skilled in the art in light of the teachings of the present invention without departing from the scope thereof. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.
Claims (6)
1. An apparatus for waking a processor, wherein the processor is capable of operating in:
a standby mode in which the processor is in a standby state; and
a run mode in which the processor is able to run at a higher load than during an interrupt phase in which the processor is woken up from a standby mode and enters a run mode;
the device comprises:
a first bias circuit configured to provide a first reference current to the oscillator during an interruption phase;
a second bias circuit configured to provide a second reference current to the oscillator in the run mode, wherein the second reference current is less than the first reference current and the second reference current has a precision greater than the first current; and
an oscillator configured to provide a system clock for waking up a processor according to a provided reference current, wherein accuracy of the system clock output by the oscillator has a positive correlation with accuracy of the provided reference current, and a start-up speed of the oscillator has a positive correlation with a magnitude of the provided reference current.
2. The apparatus of claim 1, wherein the processor is a Micro Control Unit (MCU), a general purpose processor, or a dedicated processor, and the oscillator is an RC oscillator (RCOSC).
3. The apparatus of claim 1, wherein the length of the interrupt phase is 1-10 μ s.
4. The apparatus of claim 1, wherein the oscillator comprises an oscillating circuit comprising:
the three inverters are connected in series and comprise a first inverter, a second inverter and a third inverter, wherein the input end of the first inverter is connected with the current source, and the output end of the third inverter outputs the system clock;
three capacitors corresponding to the three inverters, wherein one end of each capacitor is connected to a line between the two inverters and the second end is grounded;
the multiplexer receives a first reference current sent by the first bias circuit and a second reference current sent by the second bias circuit, selects the first reference current and the second reference current and outputs the selected reference current; and
a current source that receives the selected reference current and delivers the current output by the current source to the input of the oscillator.
5. The apparatus of claim 1, wherein the accuracy of the reference current comprises stability of the reference current.
6. A method for waking up a processor, wherein the processor is capable of operating in:
a standby mode in which the processor is in a standby state; and
a run mode in which the processor is able to run at a higher load than during an interrupt phase in which the processor is woken up from a standby mode and enters a run mode;
the method comprises the following steps:
providing a first reference current to the oscillator during an interruption phase;
providing a second reference current to the oscillator in the run mode, wherein the second reference current is less than the first reference current and the second reference current has a precision greater than the first current;
generating a respective system clock from the provided reference current, comprising:
generating a first system clock at a first speed from a first reference current; and
generating a second system clock at a second speed according to a second reference current, wherein the second speed is less than the first speed, and the precision of the second system clock is greater than the precision of the first system clock; and
waking up the processor using the system clock.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910007122.6A CN109753313B (en) | 2019-01-04 | 2019-01-04 | Device and method for waking up processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910007122.6A CN109753313B (en) | 2019-01-04 | 2019-01-04 | Device and method for waking up processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109753313A CN109753313A (en) | 2019-05-14 |
| CN109753313B true CN109753313B (en) | 2021-09-07 |
Family
ID=66405186
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910007122.6A Active CN109753313B (en) | 2019-01-04 | 2019-01-04 | Device and method for waking up processor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109753313B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997011428A1 (en) * | 1995-09-19 | 1997-03-27 | Microchip Technology Incorporated | Microcontroller wake-up function having digitally programmable threshold |
| US5842028A (en) * | 1995-10-16 | 1998-11-24 | Texas Instruments Incorporated | Method for waking up an integrated circuit from low power mode |
| US6256746B1 (en) * | 1998-07-31 | 2001-07-03 | Ubicom, Inc. | System and method for multi-input wake up in a microcontroller using a single clock |
| EP1447736A1 (en) * | 2003-02-06 | 2004-08-18 | STMicroelectronics | Microprocessor having low power consumption modes |
| CN1984169A (en) * | 2005-10-06 | 2007-06-20 | 美国博通公司 | Mobile communication device and method of running the mobile communication device in energy-saving manner |
| CN102394607A (en) * | 2011-08-30 | 2012-03-28 | 无锡中星微电子有限公司 | High-precision oscillator |
| CN107678532A (en) * | 2017-10-20 | 2018-02-09 | 苏州国芯科技有限公司 | A kind of low-power dissipation SOC wake module and low-power dissipation SOC |
-
2019
- 2019-01-04 CN CN201910007122.6A patent/CN109753313B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1997011428A1 (en) * | 1995-09-19 | 1997-03-27 | Microchip Technology Incorporated | Microcontroller wake-up function having digitally programmable threshold |
| US5842028A (en) * | 1995-10-16 | 1998-11-24 | Texas Instruments Incorporated | Method for waking up an integrated circuit from low power mode |
| US6256746B1 (en) * | 1998-07-31 | 2001-07-03 | Ubicom, Inc. | System and method for multi-input wake up in a microcontroller using a single clock |
| EP1447736A1 (en) * | 2003-02-06 | 2004-08-18 | STMicroelectronics | Microprocessor having low power consumption modes |
| CN1984169A (en) * | 2005-10-06 | 2007-06-20 | 美国博通公司 | Mobile communication device and method of running the mobile communication device in energy-saving manner |
| CN102394607A (en) * | 2011-08-30 | 2012-03-28 | 无锡中星微电子有限公司 | High-precision oscillator |
| CN107678532A (en) * | 2017-10-20 | 2018-02-09 | 苏州国芯科技有限公司 | A kind of low-power dissipation SOC wake module and low-power dissipation SOC |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109753313A (en) | 2019-05-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7194644B2 (en) | System and method for operating a microprocessor in a low power mode by providing a wakeup clock to the microprocessor | |
| US20100229011A1 (en) | Power Reduction in Microcontrollers | |
| US5623234A (en) | Clock system | |
| JP2006107127A (en) | Semiconductor integrated circuit device | |
| JPH03266108A (en) | Single-chip microcomputer | |
| JP3437174B2 (en) | Power saving integrated circuit and control method of power saving integrated circuit | |
| JP2012208804A (en) | Clock signal generation circuit | |
| US20140351615A1 (en) | Integrated circuit wake-up control system | |
| CN117075683A (en) | Clock gating component, multiplexer component and frequency dividing component | |
| JPH0854955A (en) | Clock signal generation circuit | |
| US8819401B2 (en) | Semiconductor device and reset control method in semiconductor device | |
| US7906996B1 (en) | System and method for controlling an integrated circuit in different operational modes | |
| JPH0450629B2 (en) | ||
| US9009513B2 (en) | Multiprocessor for providing timers associated with each of processor cores to determine the necessity to change operating frequency and voltage for per core upon the expiration of corresponding timer | |
| US9780644B1 (en) | Methods and apparatus for always on domain finite state machine shutdown using a clock source from a power managed domain | |
| CN109753313B (en) | Device and method for waking up processor | |
| US7293185B2 (en) | Clock control circuit and clock control method that switchingly supplies a high-speed clock and a low-speed clock | |
| CN109683975B (en) | Circuit and method for waking up processor | |
| CN115639897B (en) | Real-time voltage control module | |
| US6496078B1 (en) | Activating on-chip oscillator using ring oscillator | |
| CN112235850A (en) | Low-power-consumption system and method of Internet of things chip | |
| JP5977308B2 (en) | Electronic circuit having sleep mode | |
| JP6377659B2 (en) | Semiconductor device and control method thereof | |
| JPH076155A (en) | Single chip microcomputer | |
| JPH06259164A (en) | Clock signal generating/integrating circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221213 Address after: 201210 floor 10, block a, building 1, No. 1867, Zhongke Road, pilot Free Trade Zone, Pudong New Area, Shanghai Patentee after: Xiaohua Semiconductor Co.,Ltd. Address before: Room 305, block Y1, 112 liangxiu Road, Pudong New Area, Shanghai 201203 Patentee before: HUADA SEMICONDUCTOR Co.,Ltd. |