CN109753313A - A kind of device and method for wake-up processor - Google Patents
A kind of device and method for wake-up processor Download PDFInfo
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- CN109753313A CN109753313A CN201910007122.6A CN201910007122A CN109753313A CN 109753313 A CN109753313 A CN 109753313A CN 201910007122 A CN201910007122 A CN 201910007122A CN 109753313 A CN109753313 A CN 109753313A
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Abstract
The present invention relates to a kind of devices for wake-up processor, wherein the processor can work in following modes: standby mode, wherein processor is in standby；And operational mode, wherein processor can be with than load operation higher under interrupt phase, in interrupt phase, processor be waken up from standby mode and enters operational mode；Described device includes: the first biasing circuit, is configured as providing the first reference current to oscillator in interrupt phase；Second biasing circuit is configured as providing the second reference current to oscillator in the operating mode, wherein the second reference current is less than the first reference current, and the precision of the second reference current is greater than the precision of the first electric current；And oscillator, it is configured as providing system clock according to provided reference current.Moreover, it relates to a kind of method for ring processing unit.By the invention it is possible to realize that the high speed of processor wakes up, while keeping low-power consumption and high system clock accuracy.
Description
Technical field
Present invention relates in general to field of processors, in particular to a kind of device for wake-up processor.This
Outside, the invention further relates to a kind of methods for wake-up processor.
Background technique
Under normal circumstances, processor during idle time can enter suspend mode, under such suspend mode, processor with
Extremely low Power operation is to reduce power consumption.For wake-up processor, at present using single internal RC oscillator (RCOSC) Lai Shengcheng
System clock is with wake-up processor and other peripheral circuits.
Wake-up processor ideally, wake-up processor at high speed, while keeping the height of low-power consumption and system clock
Precision.However, actual conditions are, for high speed wake-up processor, it is necessary to larger reference current is used, this will cause high power consumption,
Thus it is not able to satisfy the requirement of many low-power consumption application scenarios.Moreover, system clock needs certain time to reach degree of precision,
This hampers high-speed starting again.
It needs at present a kind of with low-power consumption, the high wake-up mechanism for waking up speed and high clock accuracy.
Summary of the invention
From the prior art, a kind of device and a kind of method the task of the present invention is offer for wake-up processor,
By the device or this method, the high speed that processor may be implemented is waken up, while keeping low-power consumption and high system clock accuracy.
In the first aspect of the present invention, which is solved by a kind of device for wake-up processor, wherein described
Processor can work in following modes:
Standby mode, in stand-by mode, processor are in standby；And
Operational mode, in the operating mode, processor can be with than load operations higher under interrupt phase, wherein in
Faulted-stage section, the processor are waken up from standby mode and enter operational mode；
Described device includes:
First biasing circuit is configured as providing the first reference current to oscillator in interrupt phase；
Second biasing circuit is configured as providing the second reference current to oscillator in the operating mode, wherein second
Reference current is less than the first reference current, and the precision of the second reference current is greater than the precision of the first electric current；And
Oscillator is configured as providing the system clock for being used for wake-up processor according to provided reference current,
In the precision positive correlation of the precision of system clock and provided reference current that is exported by the oscillator, and institute
State the starting speed of oscillator and the size positive correlation of provided reference current.
It is provided in an expansion scheme of the invention, the processor is micro-control unit MCU, general processor or special
With processor, and the oscillator is RC oscillator RCOSC.It should be noted here that present invention could apply to other processing
Device especially requires low-power consumption, high wake-up speed and the processor of high clock accuracy, such as application specific processor, general processor
Deng.
It is provided in a preferred embodiment of the invention, the length of interrupt phase is 1-10 μ s.It, can by the preferred embodiment
To realize the preferable compromise between high speed, low-power consumption and high-precision, this is because the inventors discovered that, from starting to wake up (i.e.
When since the terminal stage) a few μ s have been crossed, processor or system just need the system clock of high-precision low-power consumption.From there through matching
The length of interrupt phase is set, can preferably realize above-mentioned compromise.
It provides in another preferred embodiment of the invention, the oscillator includes oscillating circuit, and the oscillating circuit includes:
Three concatenated phase inverters, including the first phase inverter, the second phase inverter and third phase inverter, wherein the first phase inverter
Input terminal connect with current source, and the output end output system clock of third phase inverter；
Three capacitors corresponding with three phase inverters, wherein one end of each capacitor is connected to the line between two phase inverters
Road and second end ground connection；
Multiplexer, what the first reference current and the second biasing circuit for receiving the sending of the first biasing circuit issued
Second reference current, multiplexer select the first reference current and the second reference current, and export the reference of selection
Electric current；And
Current source receives the reference current of selection, and the electric current exported by current source is passed to the input of oscillator
End.
By the preferred embodiment, the easy configuration of double oscillator may be implemented, thus simplify circuit and improve system clock
Formation speed.
It is provided in an expansion scheme of the invention, the precision of reference current includes the stability of reference current.With reference to
The precision of electric current can for example show as stability, the i.e. stationarity of the amplitude of electric current, current vs. temperature variation and voltage change
Susceptibility etc..
In the second aspect of the present invention, foregoing task is solved by a kind of method for wake-up processor, wherein institute
Stating processor can work in following modes:
Standby mode, in stand-by mode, processor are in standby；And
Operational mode, in the operating mode, processor can be with than load operations higher under interrupt phase, wherein in
Faulted-stage section, the processor are waken up from standby mode and enter operational mode；
This method includes the following steps:
The first reference current is provided to oscillator in interrupt phase；
The second reference current is provided to oscillator in the operating mode, wherein the second reference current is less than first with reference to electricity
Stream, and the precision of the second reference current is greater than the precision of the first electric current；
Corresponding system clock is generated according to provided reference current；And
The processor is waken up using the system clock.
It is provided in a preferred embodiment of the invention, corresponding system clock packet is generated according to provided reference current
It includes:
The first system clock is generated with First Speed according to the first reference current；
Second system clock is generated with second speed according to the second reference current, wherein second speed is less than First Speed,
And the precision of second system clock is greater than the precision of the first system clock.
By the preferred embodiment, high-speed starting, high system clock accuracy and low-power consumption can be realized simultaneously.
The present invention at least have it is following the utility model has the advantages that (1) by interrupt phase provide low precision restricted publication of international news and commentary entitled electric current and
High-precision small reference current is provided in the operation phase, the fast wake-up of interrupt phase and the low-power consumption of operation phase may be implemented
With high system clock accuracy, this is because the inventors discovered that, just start wake up (interrupt phase lasts about greatly several μ s) when,
System is insensitive to power consumption and clock accuracy, may be implemented have high oscillator power consumption (i.e. restricted publication of international news and commentary entitled electric current) and low system at this time
The high speed of system clock accuracy wakes up；And at operation phase (after interrupt phase), system just needs high-precision system
The oscillator of clock and low-power consumption；(2) since oscillator needs certain time that could generate high-precision system clock,
High-precision system clock can be provided under the later operational mode of interrupt phase by oscillator just to meet system operation need
It wants.
Detailed description of the invention
With reference to specific embodiment, the present invention is further explained with reference to the accompanying drawing.
Fig. 1 shows the principle of the scheme according to the present invention for wake-up processor.
Fig. 2 shows the schematic diagrames of the device according to the present invention for wake-up processor；And
Fig. 3 shows the system clock of the device according to the present invention for wake-up processor.
Specific embodiment
It should be pointed out that each component in each attached drawing may be shown in which be exaggerated in order to illustrate, and it is not necessarily ratio
Example is correctly.In the drawings, identical appended drawing reference is equipped with to the identical component of identical or function.
In the present invention, each embodiment is intended only to illustrate the solution of the present invention, and is understood not to restrictive.
In the present invention, unless otherwise indicated, quantifier "one", " one " and the scene for not excluding element.
It is also noted herein that in an embodiment of the present invention, for it is clear, for the sake of simplicity, might show only one
Sub-unit or component, but those skilled in the art are it is understood that under the teachings of the present invention, it can be according to concrete scene
Need to add required component or component.
It is also noted herein that within the scope of the invention, the wording such as " identical ", " equal ", " being equal to " are not meant to
The two numerical value is absolutely equal, but allows certain reasonable error, that is to say, that the wording also contemplated " substantially phase
Together ", " being essentially equal ", " being substantially equal to ".
In addition, the number of the step of each method of the invention limit the method step execute sequence.Unless special
It does not point out, various method steps can be executed with different order.
In addition, the present invention is despite illustrating by taking the micro-control unit MCU as an example, but this is only exemplary.Phase
Instead, it is contemplated that the present invention may be use with other processors.
Fig. 1 shows the principle of the scheme according to the present invention for wake-up processor.
The solution of the present invention based on inventor as follows see clearly: processor generally run it is as follows, in operational mode 1, locate
It manages device and operations is executed with higher load and higher clock accuracy, need power consumption at this time；When processor is receiving standby finger
When entering standby mode 2 after order, processor only executes most basic operation with extremely low power dissipation；When processor is interrupted to execute
When corresponding operating, in the stage that processor is in interrupt phase, is waken up, after interrupt phase, processor is again with higher negative
Lotus and higher clock accuracy operate in operational mode, and in interrupt phase, i.e., it is insensitive for power consumption when just waking up, to precision
Also insensitive, it is thus only necessary to high speed wakes up, but in having crossed the operational mode after a period of time, such as several us, system just needs
High-precision system clock and low power consumption are wanted, therefore in the present invention, by using big low precision in interrupt phase
Reference current (also referred to as bias current) and small high-precision reference current is used in the operation phase later, can satisfy and be
The requirement of high speed wake-up, the low-power consumption and High Definition Systems clock of system.
Fig. 2 shows the schematic diagrames of the device 100 according to the present invention for wake-up processor.
As shown in Figure 1, for wake-up processor device 100 for example for for processor (not shown) in the hibernation mode
System clock is provided, that is, the system clock for being used for wake-up processor is provided.Processor includes various processors, such as microcontroller list
First MCU, general processor, application specific processor etc..Processor can work in following modes:
Standby mode, in stand-by mode, processor are in standby.For example, standby mode may include various
Suspend mode, such as deep power down mode and sleep pattern and various super low-power consumption modes, wherein processor is with extremely low power consumption
Execute most basic operation or in sleep state.
Operational mode, under the mode, processor can with than load operation higher under interrupt phase, wherein
Interrupt phase, the processor are waken up from standby mode and enter operational mode.Operational mode for example including mode at full capacity,
Normal operation mode etc. can normally execute the mode of various operations.Interrupt phase is that finger processor is waken up to execute a certain task
Stage.In the present invention, interrupt phase can continue some period, such as 1 μ s to 10 μ s.
Device 100 includes:
First biasing circuit 101 is configured as providing the first reference current to oscillator 103 in interrupt phase.The
One biasing circuit 101 is, for example, the biasing circuit of low precision, high current.
Second biasing circuit 102 is configured as providing the second reference current to oscillator 103 in the operating mode,
Wherein the second reference current is less than the first reference current, and the precision of the second reference current is greater than the precision of the first electric current.By
In the second reference current less than the first reference current, therefore the power consumption of oscillator in the operating mode is less than oscillator in middle faulted-stage
The power consumption of section, and since the first reference current is larger, oscillator can be made quickly to start.Further, since the second reference electricity
The precision of stream is greater than the precision of the first electric current, therefore the precision of oscillator in the operating mode is higher, can meet operation needs, and
The precision of first electric current is lower, escapable cost.Second biasing circuit 102 can open simultaneously substantially with the first biasing circuit 101
It is dynamic, and provide precision low reference current by the first biasing circuit 101 first, and by the second biasing circuit 102 in stabilization
High-precision reference current is provided later.
Oscillator 103, when being configured as providing the system for being used for wake-up processor according to provided reference current
Clock.Oscillator is, for example, RC oscillator.Oscillator 103 may include single oscillating circuit, can be according to high-precision reference
Electric current generates high-precision system clock, and the system clock of lower accuracy is generated according to lower reference current, but also can
To start rapidly in the case where high current.But in other embodiments, oscillator 103 includes multiple oscillating circuits, such as the
One oscillating circuit and the second oscillating circuit, wherein the first oscillating circuit receives the first reference current from the first biasing circuit 101, and
And second oscillating circuit from the second biasing circuit 102 receive the second reference current so that the first oscillating circuit is more electric than the second oscillation
Road has higher starting speed (and more high power consumption), and the precision of the system clock generated by the second oscillating circuit is greater than
By the precision for the system clock that the first oscillating circuit generates.The output frequency (i.e. the frequency of system clock) and ginseng of oscillator 103
Examine current related, if electric current is big, frequency is high, if instead electric current is small, then frequency is low.It is the precision of reference current, such as stable
Property will determine the stability of the output frequency of oscillator.
Oscillator 103 in the embodiment of Fig. 2 is described below in detail.
Oscillator 103 includes an oscillating circuit, and oscillating circuit includes three concatenated phase inverters 1031,1032,1033,
And capacitor 1034,1035,1036 corresponding with three phase inverters.Multiplexer 105 receives the first biasing circuit 101 and issues
The first reference current 1011 and the second reference current 1021 for issuing of the second biasing circuit 102, multiplexer 105 is to the
One reference current 1011 and the second reference current 1021 are selected, and export the reference current 1051 of selection, a current source 104
Receive the reference current 1051 of selection, the output electric current of current source 104 passes to the input terminal of oscillator 103.
By controlling the selection of multiplexer 105, to control the input of oscillator 103.Such as:
In stand-by mode, processor is in standby, and control multiplexer 105 does not select the first reference current
1011 and second reference current 1021；
Under interrupt phase, processor needs low precision electric current, and control multiplexer 105 selects the first reference current
1011；
In the operating mode, processor needs high-precision current, and control multiplexer 105 selects the second reference current
1021。
Table 1 below illustrates the first biasing circuit 101 or the first RCOSC or the second biasing circuit 102 or the 2nd RCOSC
Reference pair ratio.
The parameter comparison table of 1 first and second biasing circuit (RCOSC) of table
The present invention at least have it is following the utility model has the advantages that (1) by interrupt phase provide low precision restricted publication of international news and commentary entitled electric current and
High-precision small reference current is provided in the operation phase, the fast wake-up of interrupt phase and the low-power consumption of operation phase may be implemented
With high system clock accuracy, this is because the inventors discovered that, just start wake up (interrupt phase lasts about greatly several μ s) when,
System is insensitive to power consumption and clock accuracy, may be implemented have high oscillator power consumption (i.e. restricted publication of international news and commentary entitled electric current) and low system at this time
The high speed of system clock accuracy wakes up；And at operation phase (after interrupt phase), system just needs high-precision system
The oscillator of clock and low-power consumption；(2) since oscillator needs certain time that could generate high-precision system clock,
High-precision system clock can be provided under the later operational mode of interrupt phase by oscillator just to meet system operation need
It wants.
Fig. 3 shows the system clock of the device according to the present invention for wake-up processor.
As shown in figure 3, the advantages of present invention can be by the low precision biasing circuitry 101 of high speed and high-precision biasing circuit 102
It is combined, to meet system to low-power consumption, the high needs for waking up speed and high clock accuracy.
In Fig. 3, system clock is provided by oscillator I ROSC2 in the interrupt mode, and in the operating mode by shaking
Device ICOSC1 is swung to provide.It can be seen that the present invention can meet system to low-power consumption, the high need for waking up speed and high clock accuracy
It wants.
Although some embodiments of the present invention are described in present specification, those skilled in the art
Member is it is understood that these embodiments are merely possible to shown in example.Those skilled in the art under the teachings of the present invention may be used
To expect numerous variant schemes, alternative solution and improvement project without beyond the scope of this invention.The appended claims purport
It is limiting the scope of the invention, and is covering the method in the range of these claims itself and its equivalents and knot whereby
Structure.
Claims (7)
1. a kind of device for wake-up processor, wherein the processor can work in following modes:
Standby mode, in stand-by mode, processor are in standby；And
Operational mode, in the operating mode, processor can be with than load operations higher under interrupt phase, wherein in middle faulted-stage
Section, the processor are waken up from standby mode and enter operational mode；
Described device includes:
First biasing circuit is configured as providing the first reference current to oscillator in interrupt phase；
Second biasing circuit is configured as providing the second reference current to oscillator in the operating mode, wherein the second reference
Electric current is less than the first reference current, and the precision of the second reference current is greater than the precision of the first electric current；And
Oscillator is configured as providing the system clock for being used for wake-up processor according to provided reference current, wherein by
The precision of the system clock of the oscillator output and the precision positive correlation of provided reference current, and the vibration
Swing the starting speed of device and the size positive correlation of provided reference current.
2. the apparatus according to claim 1, wherein the processor is micro-control unit MCU, general processor or dedicated
Processor, the oscillator are RC oscillator RCOSC.
3. the apparatus according to claim 1, wherein the length of interrupt phase is 1-10 μ s.
4. the apparatus according to claim 1, wherein the oscillator includes oscillating circuit, the oscillating circuit includes:
Three concatenated phase inverters, including the first phase inverter, the second phase inverter and third phase inverter, wherein the first phase inverter is defeated
Enter end to connect with current source, and the output end output system clock of third phase inverter；
Three capacitors corresponding with three phase inverters, wherein one end of each capacitor is connected on the route between two phase inverters
And second end is grounded；
Multiplexer receives the first reference current that the first biasing circuit issues and the second biasing circuit issues second
Reference current, multiplexer select the first reference current and the second reference current, and export the reference current of selection；
And
Current source receives the reference current of selection, and the electric current exported by current source is passed to the input terminal of oscillator.
5. the apparatus according to claim 1, wherein the precision of reference current includes the stability of reference current.
6. a kind of method for wake-up processor, wherein the processor can work in following modes:
Standby mode, in stand-by mode, processor are in standby；And
Operational mode, in the operating mode, processor can be with than load operations higher under interrupt phase, wherein in middle faulted-stage
Section, the processor are waken up from standby mode and enter operational mode；
This method includes the following steps:
The first reference current is provided to oscillator in interrupt phase；
The second reference current is provided to oscillator in the operating mode, wherein the second reference current is less than the first reference current, and
And second reference current precision be greater than the first electric current precision；
Corresponding system clock is generated according to provided reference current；And
The processor is waken up using the system clock.
7. according to the method described in claim 6, wherein including: according to provided reference current generation corresponding system clock
The first system clock is generated with First Speed according to the first reference current；
Second system clock is generated with second speed according to the second reference current, wherein second speed is less than First Speed, and
The precision of second system clock is greater than the precision of the first system clock.
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| WO1997011428A1 (en) * | 1995-09-19 | 1997-03-27 | Microchip Technology Incorporated | Microcontroller wake-up function having digitally programmable threshold |
| US5842028A (en) * | 1995-10-16 | 1998-11-24 | Texas Instruments Incorporated | Method for waking up an integrated circuit from low power mode |
| US6256746B1 (en) * | 1998-07-31 | 2001-07-03 | Ubicom, Inc. | System and method for multi-input wake up in a microcontroller using a single clock |
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Effective date of registration: 20221213 Address after: 201210 floor 10, block a, building 1, No. 1867, Zhongke Road, pilot Free Trade Zone, Pudong New Area, Shanghai Patentee after: Xiaohua Semiconductor Co.,Ltd. Address before: Room 305, block Y1, 112 liangxiu Road, Pudong New Area, Shanghai 201203 Patentee before: HUADA SEMICONDUCTOR Co.,Ltd. |