JPH076155A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To prevent a CPU from being stopped due to the failure or the like of an oscillator. CONSTITUTION:This single chip microcomputer is provided with a system clock selecting circuit 9 for selecting a clock signal through a clock switching signal 108 and supplying a system clock signal 109 to a CPU, a timer 4 to be reset by a timer reset signal 105, a timer reset flag 8 for outputting the signal 105, an OR circuit 5 for outputting an OR result between a system reset signal 103 and a time carry signal 106 as a flag reset signal 107, an oscillation control flag 7 capable of outputting an oscillation control signal 104 to a main clock oscillation circuit 3 and allowed to be reset by the signal 107, and a clock switching flag 6 capable of outputting the signal 108 and allowed to be reset by the signal 107. At the time of stopping the operation of the circuit 3, the circuit 3 is switched to a subclock oscillation circuit 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single chip microcomputer.

[0002]

2. Description of the Related Art One of the performances required of recent single-chip microcomputers is reduction of power consumption. As one example of means for realizing this low power consumption, there is a method using two oscillation circuits that generate a main system clock signal for high speed operation and a sub system clock signal for low speed operation. In this method, the main clock oscillation circuit is activated only when high speed operation is required, and the central processing unit (hereinafter referred to as CPU) is operated by the high speed clock signal.
On the other hand, when it is possible to operate even with a low-speed clock signal, the main clock oscillation circuit with high power consumption is stopped, the sub clock oscillation circuit with low power consumption is started, and the CPU is driven by the low-speed clock signal. I am trying to make it work.

FIG. 2 is a block diagram showing an example of a conventional single-chip microcomputer. As shown in FIG. 2, the single-chip microcomputer 10 has a clock oscillator circuit 11, a CPU 12, a reset control circuit 13, and a clock signal corresponding to an internal bus 201.
The memory 14 and the peripheral circuit 15 are provided.

In FIG. 2, in the clock generation circuit 11, by connecting a predetermined oscillator to the external terminals 31, 32, 33 and 34, the system clock 108 corresponding to the natural frequency of the oscillator is generated. , The system clock signal 108 is sent to the CPU 1 respectively.
2, supplied to the memory 14 and the peripheral circuit 15. In the CPU 12, the instruction by the program read from the memory 14 is executed, and the processed data is output and stored in the memory 14. In addition, the system reset signal 10 from the reset control circuit 13
3 is output, the clock oscillation circuit 11, the CPU 12,
The clock 14 is supplied to the memory 14 and the peripheral circuit 15, whereby the initial state of the system in the clock oscillation circuit 11, the CPU 12, the memory 14 and the peripheral circuit 15 is set. This system reset signal 103 is
When the system of the single-chip microcomputer is activated, the level temporarily becomes "1", whereby the clock oscillation circuit 11, the CPU 12, the memory 14, and the peripheral circuit 15 are reset to the initial state.

FIG. 3 shows the clock oscillator circuit 1 shown in FIG.
2 is a block diagram showing the internal configuration of No. 1. As shown in FIG. 3, the clock oscillator circuit 11 includes an internal bus 201.
Corresponding to, the sub clock oscillation circuit 2, the main clock oscillation circuit 3, the clock switching flag 6, the oscillation control flag 7, and the system clock switching circuit 9 are configured.

In FIG. 3, in the oscillation control flag 7, the data input via the internal bus 201 is stored by the instruction executed by the CPU 12 in FIG. 2, and the oscillation control signal 104 is output. It is supplied to the main clock oscillator circuit 3. In addition, the system reset signal 103 output from the reset control circuit
Is reset when the signal goes to "1" level and oscillation control signal 1
04 is reset to "0" level. In the main clock oscillator circuit 3, by connecting the main clock oscillator to the external terminals 33 and 34, a main clock oscillator circuit corresponding to the natural frequency of the main clock oscillator is formed, and the oscillation control flag is set. Oscillation is started at the time when the oscillation control signal 104 supplied from 7 goes to "1" level. The main clock signal 102 output from the main clock generating circuit 3 is supplied to the system clock switching circuit 9.

In the clock switching flag 6, the CPU
The data input via the internal bus 201 is stored by the instruction executed in 12 and the clock switching signal 104 is output and supplied to the system clock switching circuit 9. Also, the clock switching flag 6
Is the system sent from the reset control circuit 13.
When the reset signal 103 becomes "1" level, it is reset, and thereby the output clock switching signal 107 is also reset to "0" level.

In the system clock switching circuit 9, one of the sub clock signal 101 and the main clock signal 102 is inputted via the clock switching signal 107 inputted from the clock switching flag 6 in response to the input. One of the clock signals is selected and output as the system clock signal 108.
It is supplied to the U 12, the reset control circuit 13, the memory 14, and the peripheral circuit 15. In this case, clock switching signal 1
When 07 is at "0" level, the sub clock signal 101
Is selected and the clock switching signal 107 is at "1" level, the main clock signal 102 is selected.
Normally, the system clock switching circuit 9 has a built-in synchronizing circuit so that a hazard does not occur when the system clock signal is switched.

Next, the operation at system startup and system clock switching will be described.

At system startup, the system reset signal 103 is temporarily set to "1" level. As a result, the oscillation control flag 7 and the clock switching flag 6 are reset, and the oscillation control signal 104 and the clock switching signal 107 are set to the "0" level, respectively. Therefore, the oscillation operation of the main clock oscillation circuit 3 is stopped, and in the system clock switching circuit 9,
The sub clock signal 101 output from the sub clock oscillator circuit 2 is selected, and the system clock signal 1 is selected.
It is output as 08 and is supplied to the CPU 12, the reset control circuit 13, the memory 14, and the peripheral circuit 15, respectively. That is, immediately after the system is started, the operation of the main clock oscillation circuit 3 is stopped and the system
As the clock signal 108, the sub clock signal 10
1 is selected, and the low-speed operation state with low power consumption is restricted.

In this operating state, when switching from the sub clock signal 101 to the main clock signal 102 as the system clock signal 108, first, C
The instruction is executed in the PU 12, the oscillation control flag 7 is set to the “1” level, and the oscillation control signal 104 becomes the “1” level, whereby the oscillation of the main clock oscillation circuit 3 is started and the main clock oscillation circuit 3 starts. Clock signal 1
02 is generated. Next, an instruction executed by the CPU 12 sets the clock switching flag 7 to the "1" level, whereby the clock switching signal 107 is set to "1".
The level becomes high, and the system clock switching circuit 9 selects the main clock signal 102 and outputs it as the system clock signal 108. System clock signal 1 based on this main clock signal 108
08 is the CPU 12, the reset control circuit 13, the memory 1
4 and the peripheral circuit 15, the single chip microcomputer is brought into a high speed operation state.

Next, the system clock signal 108 is changed from the main clock signal 102 to the sub clock signal 10.
When switching to 1, the CPU 12 first executes an instruction to set the clock switching flag 6 to "0" level, whereby the clock switching signal 107 becomes "0" level, and in the system clock switching circuit 9, , The sub clock signal 101 is selected and output as the system clock signal 108. The system clock signal 108 based on this sub clock signal 101
Are supplied to the CPU 12, the reset control circuit 13, the memory 14, and the peripheral circuit 15, so that the single-chip microcomputer is brought into a low speed operation state. Further, when an instruction is executed in the CPU 12 and the oscillation control flag 7 is set to the "0" level, the oscillation control signal 104 becomes the "0" level, the oscillation operation of the main clock oscillation circuit 3 is stopped, and the consumption is stopped. Power is reduced.

[0013]

In the conventional single-chip microcomputer described above, when the system clock signal is switched from the sub clock signal to the main clock signal, the main clock oscillation circuit is If the main clock signal is not generated due to a failure of the clock oscillator, the system clock signal will not be supplied to the CPU, and the system of the single-chip microcomputer will be unable to recover. There is a drawback that it ends up.

[0014]

A single-chip microcomputer according to the present invention provides at least two clock signal supply sources having different oscillation frequencies and clock signals output from the clock signal supply sources. It is included in the plurality of clock signal supply sources and a system clock selection circuit which receives and selects one of the clock signals via a predetermined clock switching signal and supplies it to the CPU as a system clock signal. Of the clock signal supply sources, a clock signal output from a specific clock signal supply source that operates at system startup is counted, a time carry signal is output, and the clock signal is reset via a predetermined timer reset signal. And a timer reset signal in response to the execution of an instruction in the CPU. A timer reset flag to force a logic circuit which receives a predetermined system reset signal and the time-carry signal, and outputs the logical sum of these two signals as a flag reset signal, CPU
Output an oscillation control signal to a clock signal supply source other than the specific clock signal supply source in response to the execution of the instruction in 1), and an oscillation control flag reset by the flag reset signal, Upon execution, a clock generation circuit configured to output at least the clock switching signal and at least a clock switching flag reset by the flag / reset signal is built-in, and a clock generator other than the specific clock supply source is provided. When the clock source stops operating, the system
The clock signal supply source is switched to the specific clock signal supply source through the operation of the clock selection circuit and the oscillation control flag.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a clock generation circuit according to an embodiment of the present invention. As shown in FIG. 1, the clock generation circuit 1 in the present embodiment corresponds to the internal bus 201, a sub clock oscillation circuit 2, a main clock oscillation circuit 3, a timer 4, and an OR circuit 5.
A clock switching flag 6, an oscillation control flag 7, a timer reset flag 8, and a system clock switching circuit 9. Note that FIG. 2 is referred to as a block diagram of the entire single-chip microcomputer of the present invention.

As is clear from the comparison between FIG. 1 and FIG. 3, the difference between the clock generating circuit in the present embodiment and the clock generating circuit in the conventional example is that a timer 4, The OR circuit 5 and the timer reset flag 8 are added, and the system reset signal 103 input to the oscillation control flag 7 and the clock switching flag 6 is the flag reset signal 1.
It is a point that has been changed to 07. Further, as shown in FIG. 1, as a clock signal input to the timer 4,
The sub clock signal 101 output from the sub clock oscillation circuit 2 is input, and the inputs to the OR circuit 5 are the timer carry signal 106 output from the timer 4 and the reset control circuit 13. The system reset signal 103 is input. The flag / reset signal 107 is the logical sum output of the timer carry signal 106 and the system reset signal 103 in the OR circuit 5.

In FIG. 1, the operations of the sub clock oscillation circuit 2, the main clock oscillation circuit 3, the clock switching flag 6, the oscillation control flag 7, the system clock switching circuit 9, etc. are the same as those of the above-mentioned conventional example. The same is true, and their specific operations are omitted because they overlap with the above description. The newly added timer 4 is formed by a binary counter that counts the number of clocks of the sub clock signal 101.
When the instruction is executed in the PU 12 and the timer reset flag 8 is set to the “1” level, the timer reset 105 is set to the “1” level and the count value of the timer 4 is reset to 0. When the count value of the clock number of the sub clock signal 101 overflows, the timer carry signal 106
Is output and input to the OR circuit 5. Timer reset signal 10 output from timer reset flag 8
5 is temporarily set to the "1" level and output only when the "1" level is set by the CPU 12, but is reset to the "0" level in the normal time zone. The timer carry signal 106 output from the timer 4 temporarily becomes "1" level only when the timer 4 overflows, but normally it is "0".
Remains leveled.

In the OR circuit 5, the system reset signal 103 output from the reset control circuit 13 becomes "1" level or the timer carry signal 1
When 06 becomes "1" level, flag reset signal 1
The “1” level is output as 07 and is input to the clock switching flag 6 and the oscillation control flag 7. When the flag / reset signal 107 is output at "1" level, both the oscillation control flag 7 and the clock switching flag 6 are reset, and the oscillation control signal 104 output from the oscillation control flag 7 and the clock switching flag 6 respectively.
And the clock switching signal 108 is reset to "0" level.

In the following, the system clock signal 1
The operation in the case where 09 is normally supplied to the CPU 12 will be described. The timer 4 is C before the timer carry signal 106 is output from the timer 4.
It is reset by the PU 12 via the timer reset signal 105 output from the timer reset flag 8 which is periodically set to "1" level. Therefore, which of the sub-clock signal 101 and the main clock signal 102 is selected as the system clock signal 109 can be set by the control operation of the clock switching flag 6 and the oscillation control flag 7 of the CPU 12. To be executed.

Next, when the main clock signal 102 is selected as the system clock signal 109,
The operation in the state where the main clock signal 102 is not supplied from the main clock oscillation circuit 3 will be described. When the main clock signal 102 is selected as the system clock signal 109, the system clock signal 109 is not supplied to the CPU 12 when the main clock signal oscillation circuit 3 does not generate the main clock signal 102. Then, the operation of the CPU 12 is stopped. When the operation of the CPU 12 is stopped,
The timer reset signal 105 is not input to the timer 5 from the timer reset flag 8, and thus the timer 4 is not reset. Therefore, the timer carry signal 10 is output from the timer circuit 4.
6 is output at any time and is input to the OR circuit 5. As a result, the flag / reset signal 1 output from the OR circuit 5
07 is always output as “1” level and is input to the clock switching flag 6 and the oscillation control flag 7. By this "1" level flag / reset signal 107,
Both the clock switch flag 6 and the oscillation control flag 7 are reset, and the clock switch signal 108 and the oscillation control signal 104 output from these flags are also reset to "0" level. Therefore, the oscillation operation of the main clock oscillation circuit 3 is stopped, and in the system clock switching circuit 9, the sub clock signal 101
Is selected, is output as the system clock signal 109, and is supplied to the CPU 12 and the like. This makes CP
The operation in U12 or the like is restarted and the instruction processing is continuously executed.

[0022]

As described above, according to the present invention, in response to an operation stop failure of the main clock oscillation circuit during system operation in which the main clock signal is used as the system clock signal, the main clock oscillation circuit is reset by the instruction of the CPU. Is
A timer that counts the number of clocks of the sub clock signal is provided, and a clock switch flag that specifies selection of the system clock signal supplied to the CPU by the timer carry signal output from the timer, and a main clock signal oscillation By resetting the oscillation control flag that controls the operation of the circuit, there is an effect that the system clock signal can be automatically switched to the sub clock signal and the unrecoverable state of the CPU can be avoided.

[Brief description of drawings]

FIG. 1 is a block diagram showing a clock generation circuit in an embodiment of the present invention.

FIG. 2 is a block diagram showing a single-chip microcomputer.

FIG. 3 is a block diagram showing a clock generation circuit in a conventional example.

[Explanation of symbols]

 1, 11 Clock generation circuit 2 Sub clock oscillation circuit 3 Main clock oscillation circuit 4 Timer 5 OR circuit 6 Clock switching flag 7 Oscillation control flag 8 Timer reset flag 9 System clock switching circuit 12 CPU 13 Reset control circuit 14 Memory 15 peripheral circuit

Claims (1)

[Claims] 1. A plurality of clock signal supply sources having different oscillation frequencies, and a clock signal output from the plurality of clock signal supply sources, and receiving a clock signal from the plurality of clock signal supply sources via a predetermined clock switching signal. A system clock selection circuit that selects one clock signal and supplies it to the CPU as a system clock signal; and a clock signal supply source included in the plurality of clock signal supply sources, which operates at system startup. A clock signal output from a specific clock signal supply source is counted, a time carry signal is output, and a timer reset via a predetermined timer reset signal and an instruction in a CPU are executed, Timer reset flag that outputs a timer reset signal and predetermined system reset Signal and the time carry signal, and a logical circuit that outputs a logical sum of these two signals as a flag reset signal, and a clock signal other than the specific clock signal supply source in response to execution of an instruction in the CPU An oscillation control signal is output to a supply source, and an oscillation control flag reset by the flag reset signal and an instruction in the CPU are executed to output the clock switching signal and the flag reset signal. And a clock switching flag which is reset by the system clock selection circuit and the oscillation control flag when the operation of a clock supply source other than the specific clock supply source is stopped. Through the operation of the clock signal source to the specific clock A single-chip microcomputer characterized by switching to a signal supply source.