JPH11242529A - Clock controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To directly switch two system clocks and to shorten this switching time by holding the output of a selector of the preceding stage and also delaying switching of selectors when a clock switching signal is inputted. SOLUTION: The switching signal which is inputted to a clock selection terminal 3 and varied from 1 to 0 is inputted to a 1st delay circuit 6, a signal holding circuit 7 and a 2nd delay circuit 10 respectively. As the value of the signal of a selector 4 is 1 with a clock 0 under such conditions, the circuit 7 holds 1. Meanwhile, a selector 8 outputs 1 of the clock 0. Then a clock switching signal is inputted to a 2nd selector control circuit 9 via the circuit 10, and the input of the selector 8 is switched to the output of the circuit 7. Under such conditions, the output of the selector 4 is 1 and the output of the circuit 7 is also 1. As a result, the clocks which are outputted from the selector 8 via a noise elimination circuit 12 can be switched with no occurrence of any hazard.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control device incorporated in a semiconductor integrated circuit such as a microcomputer (hereinafter referred to as "microcomputer") to control supply of a system clock of the semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIG. 2 is a block diagram of a conventional clock control device. The clock control device includes input terminals 21 and 22 for inputting two independent clocks, a clock selection terminal 23 for inputting a clock switching signal for selecting the two input clocks, a selector 24 for switching between the two input clocks, A first selector control circuit 25 for controlling the selector 24 by a switching signal; a selector 26 for switching between a clock output from the output side of the selector 24 and a fixed signal of the power supply voltage level;
4. A counter 27 that measures the oscillation stabilization time of the clock output from the counter 4 and generates a signal synchronized with the clock, and controls the selector 26 according to the signal of the counter 27 and the clock switching signal input from the clock selection terminal 23. The selector control circuit 28 includes an output terminal 29 connected to the output side of the selector 26.

FIG. 3 shows an example of the operation of the above-mentioned conventional clock control device in which the microcomputer system clock is changed from clock 0 (for example, 32 KHz) to clock 1 (for example, 20 MHz).
FIG. 6 shows a timing chart when switching to the mode. The device of FIG.
It is assumed that the operation is performed under the following five conditions.

[0004] 1. It is assumed that when the clock switching signal input from the clock selection terminal 23 changes from 1 to 0, the clock changes from clock 0 to clock 1.

[0005] 2. The clock switching signal is synchronized with clock 0.

[0006] 3. The selector 24 is assumed to change from clock 0 to clock 1 when the signal from the first selector control circuit 25 changes from 0 to 1.

[0007] 4. When the signal from the second selector control circuit 28 changes from 0 to 1, the selector 26 switches from the clock output from the selector 24 to a fixed signal of the power supply voltage level, and outputs the signal from the second selector control circuit 28. When the signal changes from 1 to 0, the signal is switched from the fixed signal of the power supply voltage level to the clock output from the selector 24.

[0008] 5. It is assumed that the initial outputs of the first selector control circuit 25 and the second selector control circuit 28 are 0.

As shown in FIG. 3, when a clock switching signal that changes from 1 to 0 is input, the output signal of the first selector control circuit 25 changes from 0 to 1 and the output signal of the second selector control circuit 28 changes. Changes from 0 to 1. Therefore, 3. 4. The output of the selector 24 is switched from clock 0 to clock 1 according to the condition (1).

The output of the selector 26 is
Is switched to the fixed signal of the power supply voltage level. Since the output of the selector 24 is not synchronized with the clock 0 and the clock 1, a waveform having an indefinite width such as B which is neither the clock 0 nor the clock 1 (hereinafter referred to as a hazard) is output.

However, no hazard is generated at the output of the selector 26. Because the second selector control circuit 28
Output signal is synchronized with the rising edge of clock 0,
The input of the selector 26 is for a signal change from 1 to 1. Therefore, at the time of switching at A, the hazard of the output terminal 29 does not occur.

Next, a signal synchronized with the clock 1 is generated by the counter 27, and the signal is sent to the second selector control circuit 28. The signal generated by the counter 27 is synchronized with the rising edge of the clock 1 and is output after counting two or three clocks so as not to be synchronized with a hazard such as B. C
Receiving the signal of the counter 27 output at the timing of
The second selector control circuit 28 supplies the selector 26 with 1 to 0
To change the signal.

[0013] Therefore, the above 4. The selector 26 switches from the power supply voltage fixed signal to the clock 1 that is the output clock of the selector 24 according to the condition (1). The timing of C is synchronized with the rise of clock 1 and the selector 26
Is a signal change from 1 to 1, no hazard is generated at the output of the selector 26.

Therefore, no hazard is generated at the output terminal 29 even when C is switched. However, in the conventional clock control device, if the clock switching signal is not synchronized with the clock before the switching, a hazard is expected to be generated at the time of the switching.

FIG. 4 shows a timing chart when the system clock is switched from clock 0 to clock 1 asynchronously with clock 0. When a clock switching signal that changes from 1 to 0 is input at the timing A, the output signal of the first selector control circuit 25 changes from 0 to 1 and the output signal of the second selector control circuit 28 changes from 0 to 1 Changes to

Therefore, the above-mentioned 3. 4. According to the conditions of
The output of the selector 24 is switched from clock 0 to clock 1, and the output of the selector 26 is switched from the clock of the output of the selector 24 to a fixed signal of the power supply voltage level. in this case,
The output of the selector 26 generates a hazard such as B.

This is because the output signal of the second selector control circuit 28 is not synchronized with the rising edge of the clock 0, the signal of the clock 0 is output, and the signal changes from 0 to 1 at the timing of A. It is.

As described above, in the conventional clock control apparatus, if the clock switching signal is not synchronized with the clock before switching (clock 0 in FIG. 4), a hazard is generated at the time of switching. Therefore, in the conventional clock control device, the system clock cannot be switched by the asynchronous clock switching signal.

That is, in the conventional clock control device,
The clock switching signal had to be synchronized with the system clock. For example, a CPU or the like operating in synchronization with a system clock executes a clock switching instruction to generate a clock switching signal and switch the system clock.

Therefore, when it is desired to switch the system clock with an asynchronous signal such as an interrupt, the conventional clock control device has realized this by causing an interrupt to the CPU once and performing the process of switching the system clock by the CPU. In the case of switching the system clock by the CPU as described above, when switching from the low-speed clock to the high-speed clock, the operation of the CPU intervenes, and the execution of the CPU is performed at the low-speed clock. Having.

The conventional circuit has the following problems. Consider a case where a microcomputer incorporating a conventional clock control device is used in a communication device such as a mobile phone. In a communication device application such as a mobile phone, a microcomputer is operated with a low-speed clock during standby to reduce power consumption, and high-speed operation is required during a call, so processing is performed with a high-speed clock. When switching from the low-speed clock during standby to the high-speed clock during communication in such an application, the following execution sequence is performed by the microcomputer using the conventional clock control device.

1. During execution of the waiting program by the low-speed clock, an asynchronous signal indicating that communication has started is input to the microcomputer.

2. According to the input, a clock switching program is executed with a low-speed clock.

3. High-speed clock is 2-3 for synchronization.
Stop the cycle.

4. After the switching, the program for the call processing is executed by the high-speed clock.

In the above sequence, the above 2. The sequence of (1) executes a program using a low-speed clock, so that processing takes time. During the execution of this sequence.

That is, in the microcomputer using the conventional clock control device, when switching from the standby low-speed clock to the high-speed clock, the first part of the received data may be lost. In order to prevent such a malfunction, if an application such as a mobile phone is realized by a microcomputer having a conventional clock control device, it is necessary to have an external circuit for switching from a low-speed clock to a high-speed clock, which complicates the application circuit. I was

[0028]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a clock control device in which two system clocks supplied to a microcomputer are directly switched by an asynchronous signal, and the switching time is short.

[0029]

In order to achieve the above object, according to the present invention, a clock switching selector is connected in series, a clock is switched by a preceding-stage selector, and a fixed signal and an output of the preceding-stage selector are switched by a following-stage selector. In the clock control device that switches between and, a signal holding circuit that holds the output of the previous-stage selector when a clock switching signal is input for generating a fixed signal,
It is configured to have a delay circuit for sequentially switching the subsequent-stage selector and the preceding-stage selector.

[0030]

FIG. 1 is a diagram showing a basic configuration diagram of a clock control device according to a first embodiment of the present invention. The clock control device includes terminals 1 and 2 for inputting two independent clocks, a clock selection terminal 3 for inputting a clock switching signal for selecting the two input clocks, a selector 4 for switching the two input clocks, and a selector 4 The first selector control circuit 5 for controlling the clock switching signal input from the clock selection terminal 3
A first delay circuit 6 for sending a signal to the selector control circuit 5, a signal holding circuit 7 for holding a clock output from the selector 4 by a clock switching signal input from a clock selection terminal 3, a signal holding circuit 7, and a selector 4
A selector 8 for switching the signal output from the second selector, a second selector control circuit 9 for controlling the selector 8, a clock switching signal input from the clock selection terminal 3 to delay the signal, and send a signal to the second selector control circuit 9, Second delay circuit 1 having a smaller delay value than the delay circuit 6 of FIG.
0, a synchronizing circuit 11 that generates a signal synchronized with the clock output from the selector 4 and sends the signal to the second selector control circuit 9, and a noise removing circuit 12 for removing noise on the output signal of the selector 8 And an output terminal 13 of the clock control device connected to the output of the noise elimination circuit 12.

FIGS. 5, 6, and 7 show timing diagrams when the clock control device switches the system clock of the microcomputer from clock 0 to clock 1 as an embodiment of the present invention. FIG. 6 is an enlarged view of an aa 'portion of FIG. 5, and FIG. 7 is an enlarged view of a portion corresponding to the aa' portion of FIG. 5 when the clock switching signal enters at a timing different from that of FIGS. It is an enlarged view. It is assumed that the apparatus of FIG. 1 operates under the following four conditions.

1. It is assumed that when the clock switching signal input from the clock selection terminal 3 changes from 1 to 0, the clock changes from clock 0 to clock 1.

2. When the signal from the first selector control circuit 5 changes from 0 to 1, the selector 4 outputs the clock 0
From clock 1 to clock 1.

3. When the signal from the second selector control circuit 9 changes from 0 to 1, the selector 8
Is switched to the output signal of the signal holding circuit 7 and the signal from the second selector control circuit 9 becomes 1
Is changed from 0 to 0, the output signal of the signal holding circuit 7 is switched to the clock output from the selector 4.

4. It is assumed that the initial outputs of the first selector control circuit 5 and the second selector control circuit 9 are 0.

The signal in which the switching signal input to the clock selection terminal 3 changes from 1 to 0 is input to the first delay circuit 6, the signal holding circuit 7, and the second delay circuit 10. The signal holding circuit 7 holds the output signal of the selector 4 (FIG. 5 a-a ′, FIG. 6, point A and FIG. 7, point A).

5 and 6, the signal of the selector 4 is clock 0 and the value is 1, so that the signal holding circuit 7
Hold. At this time, the selector 8 is not switched, and the output of the selector 8 outputs 1 of the clock 0.

Thereafter, the clock switching signal is input to the second selector control circuit 9 through the first delay circuit 10. The second selector control circuit 9 switches the input of the selector 8 from the clock 0 which is the output of the selector 4 to the output of the signal holding circuit 7 according to the signal received from the second delay circuit 10.

At this time, since the output of the selector 4 is 1 and the output of the signal holding circuit 7 is 1, no hazard is generated by switching the selector 8. Therefore, no hazard occurs in the clock output from the output of the selector 8 to the output of the clock control device through the noise removal circuit 12 (points B in FIG. 5A-a ′ and FIG. 6).

When the clock switching signal comes in at the timing shown at point A in FIG. 7, the output of the selector 4 changes to 0 at the moment of switching of the selector 8, and the hazard of about the delay width by the first delay circuit 6 is generated. (Point B in FIG. 7). However, this hazard is less than several ns, and can be removed by the noise removal circuit 12 connected to the selector output 8. Therefore, even in the case of the example of FIG. 7, no hazard occurs in the clock output to the output of the clock control device.

Thereafter, the selector switching signal is input to the first selector control circuit 4 through the first delay circuit 6. Here, the output of the selector 4 switches from the clock 0 to the clock 1 (FIG. 5a-a ', points C and C in FIG. 6). At this time, the selector 8 is connected to the signal holding circuit 7.
Remains at 1 because the output has been selected.

When the output of the selector 4 switches from the clock 0 to the clock 1, the counter 11 generates a signal synchronized with the clock 1 several clocks later. The time at this time is to prevent a hazard generated at the time of switching by the selector 4 from being output to the output of the selector 8. Therefore, two to three clocks of the output clock of the selector 4 are sufficient.

Upon receiving the synchronization signal output from the counter 11,
The second selector control signal 9 switches the input of the selector 8 from the output of the signal holding circuit 7 to the clock 1 which is the output of the selector 4. At this time, since the selector switching signal input to the selector 8 is synchronized with the clock 1, no hazard occurs at the time of switching (point b in FIG. 5).

By the above operation, the system clock can be switched by two to three clocks by the counter 11 without generating a hazard at the output terminal 13.

Next, FIG. 8 shows a second embodiment of the present invention.
In FIG. 8, the same parts as those in the first embodiment shown in FIG. An interrupt input terminal 14 for receiving the interrupt signal shown in FIG.
An interrupt control circuit 15 for outputting an interrupt vector and an interrupt request to the CPU is provided.

In this case, when an interrupt is input, the system clock is switched as described in the first embodiment. Interrupt processing is performed at the same time as switching.

If the second embodiment is used for a communication device such as a mobile phone, the following sequence is obtained.

1. During execution of the waiting program at the low-speed clock, an asynchronous signal indicating that communication has started is input to the microcomputer as an interrupt.

2. The input switches the low-speed clock to the high-speed clock. The high-speed clock is stopped for a few cycles for synchronization.

3. The call processing program is executed with the switched high-speed clock.

Unlike the conventional clock control device, there is no program execution by the low-speed clock accompanying the clock switching. By stopping the clock for two or three cycles for synchronization and performing vector processing by interrupt processing, it is possible to immediately execute a communication program.

Moreover, since the synchronization and the vector processing are performed by the high-speed clock, the processing can be performed in a short time. By using the second embodiment, it is possible to realize an application, such as a mobile phone, that needs to quickly switch from operation using a low-speed clock to operation using a high-speed clock without providing a complicated external circuit.

[0053]

According to the present invention, it is possible to provide a clock control device in which two system clocks supplied to a microcomputer are directly switched by an asynchronous signal and the switching time is short. If a microcomputer incorporating the present invention is used in an application such as a mobile phone which needs to quickly switch from operation using a low-speed clock to operation using a high-speed clock, the application can be realized without providing a complicated external circuit.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a clock control device according to a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a conventional clock control device.

FIG. 3 is a first timing chart showing the operation of the conventional clock control device.

FIG. 4 is a second timing chart showing the operation of the conventional clock control device.

FIG. 5 is a first timing chart showing the operation of one embodiment of the present invention.

FIG. 6 is a second timing chart showing the operation of one embodiment of the present invention.

FIG. 7 is a third timing chart showing the operation of one embodiment of the present invention.

FIG. 8 is a circuit configuration diagram of a clock control device according to a second embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Clock input terminal, 2 ... Clock input terminal, 3 ... Clock selection terminal, 4 ... Selector, 5 ... First selector control circuit, 6 ... First delay circuit, 7 ... Signal holding circuit,
8 selector, 9 second selector control circuit, 10 second delay circuit, 11 counter, 12 noise removal circuit, 13 clock control device output terminal.

Claims (4)

[Claims] 1. A terminal for inputting two independent clocks, a clock selection terminal for inputting a clock switching signal for selecting one of the two clocks, and switching between the two clocks according to the clock switching signal. A first selector, a first selector control device for controlling the first selector, a second selector for switching between a fixed signal and a clock output from the first selector, and controlling the second selector A second selector control circuit that generates a signal synchronized with a clock output from the first selector and sends a signal to the second selector control device. The clock switching signal input to the terminal is delayed by a predetermined delay value and transmitted to the first selector control device. A first delay device for transmitting a clock signal, a second delay circuit for delaying the clock switching signal by a predetermined delay value and transmitting the clock switching signal to the second selector control device, and a clock output from the first selector. A signal holding device that holds the clock switching signal input from the clock selection terminal, wherein a delay value of the first delay device is set to be larger than a delay value of the second delay device; A clock control device, wherein a selector selects a fixed signal, which is an output of the signal holding device, and an output of the first selector according to an output signal of the second selector control device. 2. The clock control device according to claim 1, wherein said clock selection terminal is connected to an interrupt terminal. 3. The clock control device according to claim 1, wherein a noise removal device is provided on an output side of said second selector, and a noise on an output signal of said second selector is removed. 4. A terminal for inputting two independent clocks, a clock selection terminal for inputting a clock switching signal for selecting one of the two clocks, and switching between the two clocks according to the clock switching signal. A first selector, a first selector control device for controlling the first selector, a second selector for switching between a fixed signal and a clock output from the first selector, and controlling the second selector A second selector control circuit for generating a signal synchronized with a clock output from the first selector and a counter for sending a signal to the second selector control device. The clock switching signal input to the terminal is delayed by a predetermined delay value and transmitted to the first selector control device. A first delay device for transmitting a clock signal, a second delay circuit for delaying the clock switching signal by a predetermined delay value, and transmitting the clock signal to the second selector control device, and a clock output from the first selector. A signal holding device that holds a clock switching signal input from the clock selection terminal, an interrupt terminal connected to the clock selection terminal, and a noise removal device provided on an output side of the second selector, The delay value of the first delay device is set to be larger than the delay value of the second delay device, and the second selector receives the output of the signal holding device according to the output signal of the second selector control device. A clock control device for selecting a certain fixed signal and an output of the first selector.