JP2000066708A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a programmable controller capable of eliminating the time deviation of the internal clock of a clock supply origin LSI and the internal clock of another LSI for receiving the clock and supplying the clock of the same H width and L width to the own and other LSIs. SOLUTION: In this programmable controller for performing the transmission of a synchronous type between plural LSIs, when an LSI 200 of a clock supply origin uses a clock, a clock supplied to an other LSI 3 is fetched from a clock connection line 6 through an input buffer 21 to the LSI 200. Also, the LSI 200 of the clock supply origin frequency-divides the clock from an oscillator 100 into two and works it so as to make the H width and L width of the clock the same by a JK flip-flop 22 and supplies it to the own and other LSIs 200 and 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller that performs synchronous transmission between a plurality of LSIs.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional circuit configuration example of a programmable controller which performs synchronous transmission between a plurality of LSIs.

As shown in FIG. 5, a plurality of LSIs (large-scale integrated circuits) are a first LSI 2 and a second LSI 3, a clock supply source is a first LSI 2, and a clock connection line 6 is provided.
The clock is supplied to the second LSI 3 through the second LSI 3. The first LSI 2 receives the original clock from the oscillator 1 from the input buffer 4, uses this clock as an internal clock, and supplies this clock to another LSI 3 via the output buffer 5. The second LSI 3 receives the clock from the input buffer 13 through the clock connection line 6 and uses it as an internal clock. Note that 9,
10, 15 and 16 are D flip-flops, 11 and 14 are input buffers, and 12 and 17 are output buffers.

As an example of synchronous transmission in the above circuit, first data 7 and second data 8 are shown. First
The data 7 is data set in accordance with the rise of the internal clock of the first LSI 2, and is transmission data for one clock which is taken into the second LSI 3 by the rise of the internal clock of the second LSI 3. On the other hand, the second data 8 is data set in accordance with the rise of the internal clock of the second LSI 3, and is transmission data between the half clocks which is taken into the first LSI 2 by the fall of the internal clock of the first LSI 2.

The timing relationship between these clocks and data is shown in the timing chart of FIG. As shown in FIG. 6, the clock of the oscillator 1 (hereinafter, the oscillator clock)
Is delayed before the internal clock of the first LSI 2 (hereinafter, the first LSI internal clock), and further delayed by the internal clock of the second LSI 3 (hereinafter, the second LSI internal clock). Generally, the output buffer 5 and the input buffer 13
The second LSI internal clock input through the above will cause a large delay.

Therefore, the first data 7 changes with a delay from the rise of the first LSI internal clock, and the next second L
At the rising edge of the SI internal clock, it is taken into the second LSI 3. The second data 8 changes with a delay from the rise of the second LSI internal clock, and is taken into the first LSI 2 at the next fall of the first LSI internal clock.

[0007] Here, the first data 7 corresponds to a first LS with respect to a change delay from the rise of the first LSI internal clock.
If the delay from the rise of the I internal clock to the rise of the second LSI internal clock is large, the first LS
The rise of the internal clock of the second LSI, which is the same as the rise of the internal clock of I, is taken into the second LSI 3. That is, if the delay from the rise of the first LSI internal clock to the rise of the second LSI internal clock is large, synchronous transmission cannot be performed.

In addition, the second data 8 is generated by the second LSI with respect to a change delay from the rise of the second LSI internal clock.
If the time from the rise of the internal clock to the fall of the next first LSI internal clock is short, the first L
It is necessary to wait until the next falling edge of the first LSI internal clock without being captured by the falling edge of the SI internal clock. That is, if the delay from the rise of the first LSI internal clock to the rise of the second LSI internal clock is large, or if the H width of the clock is short, synchronous transmission cannot be performed. Generally, the output of the oscillator 1 has an H width (width of a high level portion of one pulse) and an L width (width of a low level portion of one pulse).

[0009]

As described in detail above,
In the prior art, when the clock source LSI uses the clock, the clock before supplying the clock to the other LSI is used. Therefore, the clock of the source LSI and the other LSI are used.
If the time difference with the clock is large and the difference is longer than the data transmission time, synchronous transmission using the same clock cannot be performed.

Therefore, a first object of the present invention is to solve the first problem by substantially eliminating a time lag between an internal clock of a clock source LSI and an internal clock of another LSI receiving the clock. An object of the present invention is to provide a programmable controller which has been eliminated.

Further, as described above, in the prior art, when the clock source LSI supplies a clock to another LSI, the original signal of the clock supplied from the oscillator is supplied to the other LSI as it is. If the H width and the L width of the clock are different and the difference between the H width and the L width is large, it is impossible to perform transmission between half clocks of the same clock in synchronous transmission.

Accordingly, a second object of the present invention is to provide a programmable controller capable of supplying clocks having the same H width and L width to a plurality of LSIs in order to solve the second problem. Is to do.

[0013]

According to a first aspect of the present invention, there is provided a programmable controller for performing synchronous transmission between a plurality of LSIs, wherein the clock source LSI uses a clock. When other LS
A means for using the clock supplied to I.

According to another aspect of the present invention, in a programmable controller for performing synchronous transmission between a plurality of LSIs, the clock source LSI divides the input clock by two. Means 2
A clock which is frequency-divided and processed so that the H width and the L width become the same is supplied to the clock supply source LSI and another LSI.

A third aspect of the present invention is a combination of the first and second aspects.

Here, preferably, the means for using the clock supplied to another LSI when the clock supply source LSI uses the clock according to claim 1 or 3 is provided for the other LSI. An input buffer for taking in the supplied clock into the LSI which supplies the clock is included.

The first aspect of the present invention focuses on the fact that clocks of the same condition should be used in a plurality of LSIs. For this reason, in the invention of claim 1, a plurality of L
In a programmable controller performing synchronous transmission between SIs, when a clock source LSI uses a clock, the clock supplied to another LSI is used, and the delay of the clock with respect to the original signal is the same. Therefore, clocks of the same condition can be used in a plurality of LSIs.

The invention of claim 2 focuses on the fact that the original clock signal should be processed into a clock signal having the same H width and L width. For this reason, according to the second aspect of the present invention, in the programmable controller which performs synchronous transmission between a plurality of LSIs, the clock supply source LS
When I supplies a clock to its own or another LSI, the input clock is divided by two and processed so that the H width and the L width of the clock become the same and supplied to the own or other LSI. Therefore, in a plurality of LSIs, a clock having the same H width and L width can be used.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a circuit configuration of a programmable controller according to a first embodiment of the present invention.
Is shown in the block diagram of FIG.

The difference between the configuration of the first embodiment shown in FIG. 1 and the configuration of the prior art shown in FIG. 5 is that the input buffer 21 of the input / output buffers 5 and 21 is used as the internal clock of the first LSI 20. The point is that the clock on the clock connection line 6 is input to the first LSI 20 through the first LSI 20. The other configuration is the same as that of the conventional example of FIG. 5, and the description thereof is omitted.

Although the input / output buffer connected to the clock connection line 6 is configured by combining the individual output buffer 5 and the input buffer 21 as described above, a single input / output buffer may be used.

As can be seen from FIG. 1, the original clock from the oscillator 1 passes through an input buffer 4, an output buffer 5, a clock connection line 6, and an input buffer 21 to a first L.
Used as the internal clock of SI20 and the oscillator 1
The original clock from the input buffer 4, output buffer 5,
The number of buffers that are used as internal clocks of the second LS 3 through the clock connection line 6 and the input buffer 13 and that cause time lags before reaching the respective internal clocks are also equal.

As a result, the internal clock of the first LSI 20 and the internal clock of the second LSI 3 are supplied from the clock connection line 6 under the same conditions, and as shown in the timing chart of FIG. Is eliminated.

(Second Embodiment) Next, a second embodiment of the present invention will be described.
FIG. 3 is a block diagram showing a circuit configuration of the programmable controller according to the embodiment.

The difference between the configuration of the second embodiment shown in FIG. 3 and FIG. 1 of the first embodiment of the present invention is that the oscillator 1
When the clock input from the first LSI 200 is output from the first LSI 200 to the clock connection line 6, the first LSI 200
Is that the frequency is divided by two. The other configuration is the same as that of the first embodiment of the present invention shown in FIG.

In this example, a JK flip-flop 22 is connected between the input buffer 4 and the output buffer 5 in the first LSI 200.
A configuration is adopted in which the output of the JK flip-flop 22 is inverted at the rising edge of the clock by fixing the K terminal to a predetermined H level. By this inversion, FIG.
As shown in the waveform of the oscillator clock and the waveform of the internal clock of the LSI 200 in the timing chart of FIG.
A clock obtained by dividing the clock from the oscillator 100 by two is obtained from the flip-flop 22, and the H width and the L width of the divided clock are equal.

Here, in order to obtain the same frequency on the clock connection line 6 even if the frequency is divided by 2, the oscillator 100 needs
Double frequency is required.

Thus, even if the output clock of the oscillator 100 has a difference between the H width and the L width, a clock having the same H width and L width can be supplied to a plurality of LSIs.

(Other Embodiments) In the above-described first and second embodiments of the present invention, for simplicity of description, the plurality of LSIs are two, a first LSI and a second LSI. However, by applying the same configuration, the present invention can be applied to three or more LSIs, and similar effects can be expected.

[0031]

As described above, according to the first embodiment of the present invention, when a clock supply source LSI uses a clock in a programmable controller performing synchronous transmission between a plurality of LSIs. Uses a clock supplied to another LSI and uses an input buffer so that the delay of the clock with respect to the original signal is the same, so that a plurality of LSIs can use clocks of the same condition. Therefore, according to the first aspect of the present invention, it is possible to substantially eliminate the time lag between the internal clock of the clock supply source LSI and the internal clock of another LSI receiving the clock, and thereby the same clock can be obtained. Can greatly improve the reliability of synchronous transmission using.

According to the second embodiment of the present invention, in a programmable controller performing synchronous transmission between a plurality of LSIs, when a clock source LSI supplies a clock to its own or another LSI, Since the clock is divided by two and processed so that the H width and the L width of the clock become the same and supplied to the other LSI, a plurality of LSs are provided.
In I, a clock whose H width and L width are the same can be used. Therefore, according to the second aspect of the present invention, reliability of transmission between half clocks of the same clock in synchronous transmission can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a programmable controller according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing clock timings in the first embodiment of the present invention shown in FIG. 1;

FIG. 3 is a block diagram showing a circuit configuration of a programmable controller according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing clock timings according to the second embodiment of the present invention shown in FIG. 3;

FIG. 5 is a block diagram illustrating a conventional circuit configuration example of a programmable controller that performs synchronous transmission between a plurality of LSIs.

FIG. 6 is a timing chart showing clock timings in the conventional example of FIG.

[Explanation of symbols]

 1 100 Oscillation circuit 2, 20, 200 First LSI 3 Second LSI 4, 11, 13, 14, 21 Input buffer 5, 12, 17 Output buffer 6 Clock connection line 7 First data 8 Second data 9, 15, 16 D Flip-flop 22 JK flip-flop

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2F002 AA00 CA00 CB11 5B079 CC02 CC14 DD02 DD06 DD08 DD13 DD17 5H219 CC11 EE05 HH09 HH21 5H220 BB09 CC03 CX01 EE03 EE06 JJ08 JJ35 5J043 AA11 BB04 DD05

Claims (4)

[Claims] 1. A programmable controller that performs synchronous transmission between a plurality of LSIs, characterized in that the programmable controller includes means for using a clock supplied to another LSI when the clock source LSI uses the clock. Programmable controller. 2. A programmable controller that performs synchronous transmission between a plurality of LSIs, wherein the clock source LSI has means for dividing the input clock by two, and the H width and L width are divided by two. A programmable controller, characterized in that a clock processed so as to be identical is supplied to the clock supply source LSI and another LSI. 3. A programmable controller for performing synchronous transmission between a plurality of LSIs, comprising: means for using a clock supplied to another LSI when the clock source LSI uses a clock; The LSI has means for dividing the input clock by two, and the clock processed so that the H width and the L width are equal to each other by dividing the clock by two is combined with the clock source LSI and the other LS.
A programmable controller, which supplies the programmable controller with the control signal. 4. The means for using a clock supplied to another LSI when the clock source LSI uses a clock is to fetch the clock supplied to the other LSI into the clock source LSI. 4. The programmable controller according to claim 1, further comprising: