JPH095397A - Logical simulation method - Google Patents

Abstract

PURPOSE: To achieve a higher testing accuracy by giving a specified delay value to an internal clock signal to be supplied to a clock distribution section to enable a comprehensive test containing a phase synchronization loop (PLL). CONSTITUTION: A clock signal (ExtCLK) from outside is applied to a reference input R of a PLL10 and an internal clock (IntCLK) is taken out of an output O thereof. The IntCLK is distributed to a plurality of logical circuits 121 -12n through a clock distribution section 11. At the same time, a clock signal (FeedbackCLK) fetched from the final stage of the distribution section 11 is applied to a feedback input F of the PLL10. A buffer 10a (tpdPLL) is provided to apply a specified delay value to the IntCLK. The delay circuit obtained corresponds to an internal delay of the PLL10. This enables matching of the phase of the FeedbackCLK in simulation accurately with that of the actual ExtCLK.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation method for a semiconductor integrated circuit incorporating a PLL clock skew suppressing circuit. As shown in FIG. 7, a PLL clock skew suppressing circuit mainly incorporated in various high-speed operation type semiconductor integrated circuits includes a PLL (Phase Lock Loop: Phase Lock Loop) provided in a clock input section of the semiconductor integrated circuit 1.
ed Loop) 2 is provided, and an external clock signal (hereinafter referred to as “ExtCL
Given K "), through a clock distribution unit signal 3 takes out the internal clock signal (hereinafter" IntCLK ") from its output O, a number of logic circuits (typically flip-flops 4 ₁
4 _n ) and a clock signal (hereinafter referred to as “Fe
edbackCLK ") is applied to the feedback input F of the PLL2. Note that 5, 6, 7 _i and 8 _i are buffers (subscript i is 1, 2, 3, ...).

Here, the PLL 2 is a phase comparator (PC) which generates a control voltage according to the phase difference between two input signals.
And a voltage controlled oscillator (VCO) whose oscillation frequency is controlled by its control voltage. A loop filter that removes high-frequency components from the control voltage and determines the PLL synchronization characteristic, response characteristic, and the like is also included in the configuration, but the description is omitted because it is not related to the gist of the invention.

In FIG. 7, the two inputs of the PC correspond to ExtCLK and FeedbackCLK, and the PLL 2 adjusts the phase of IntCLK so that the phase difference between these two inputs becomes zero. FIG. 8 is a timing chart of two inputs. According to this, the phases of FeedbackCLK and ExtCLK are exactly matched, and the duty of FeedbackCLK is adjusted to 50% (A = B) regardless of the duty of ExtCLK (a <b for convenience). The phase matching () is effective for high-speed data transmission between IC chips, and the duty adjustment () is effective for avoiding an error of the clock signal pulse width in the chip.

[0004]

2. Description of the Related Art FIG. 9 is a conceptual diagram of a conventional logic simulator method applied to a semiconductor integrated circuit incorporating such a PLL clock skew suppressing circuit. Reference numeral 9 denotes a multiplexer. Normally, the multiplexer 9 selects (a) the IntCLK taken out from the PLL 2, but when the selection signal (hereinafter, “Select”) is set to a predetermined logic,
Instead of tCLK, an external test clock signal (hereinafter "TstCLK") is selected (b). According to this, at the time of test (when Select is set to a predetermined logic), a logic simulation of each part in the chip using ExtCLK can be performed.

[0005]

However, in such a conventional logic simulation method, since the test is performed in a state where the PLL is completely cut off, a comprehensive test result including the PLL cannot be obtained, and the test cannot be performed. It was insufficient in terms of accuracy.

[0006]

[Purpose] Therefore, an object of the present invention is to obtain a comprehensive test result including a PLL, thereby sufficiently improving the test accuracy.

[0007]

According to the first aspect of the present invention,
Logic simulation method for a semiconductor integrated circuit including a PLL for adjusting the phase of the internal clock signal given to the clock distribution unit so that the phase difference between the internal clock signal extracted from the final stage of the clock distribution unit and the external clock signal becomes zero. A delay unit for giving a predetermined delay amount to the internal clock signal supplied to the clock distribution unit, and the internal clock signal supplied to the clock distribution unit and the final stage of the clock distribution unit at the predetermined delay amount. The delay amount with the internal clock signal extracted from is added, a virtual clock signal whose phase is shifted earlier than the external clock signal by the added value is generated, and a simulation is performed using the virtual clock signal, At the time of the test, the test is performed by using an actual external clock signal.

Alternatively, in the invention of claim 2, the phase of the internal clock signal given to the clock distribution unit so that the phase difference between the internal clock signal extracted from the final stage of the clock distribution unit and the external clock signal becomes zero. To adjust P
In a method for simulating a semiconductor integrated circuit having LL, a delay unit is provided for giving a predetermined delay amount to an internal clock signal given to the clock distribution unit, and the predetermined time is given from a time corresponding to one cycle length of the external clock. The simulation is performed by delaying the external clock signal by the time obtained by subtracting the delay amount of, and the test is performed using the actual external clock signal during the test.

[0009]

According to the present invention, a test external clock signal (or a virtual clock signal) is created in consideration of the internal delay of the PLL and the on-chip transmission delay of the clock signal. Therefore,
A comprehensive test including the PLL becomes possible, and the test accuracy is sufficiently improved.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are diagrams showing an embodiment of a logic simulation method according to the present invention. In FIG. 1, reference numeral 10 denotes a PLL, and this PLL 10 mainly forms a main part of a PLL clock skew suppressing circuit incorporated in various high-speed operation type semiconductor integrated circuits together with a feedback loop described later.

An external clock signal (hereinafter referred to as "ExtCLK") is applied to the reference input R of the PLL 10,
An internal clock signal (hereinafter “IntCLK”) is output from the output O.
Has been taken out. IntCLK is clock distribution unit signal 1
1 is distributed to a large number of logic circuits (typically shown by flip-flops 12 _{1 to} 12 _n ) and a clock signal (hereinafter referred to as “FeedbackCLK”) extracted from the final stage of the clock distribution unit signal 11 is supplied to the PLL 10. Is fed to the feedback input F.

FeedbackCLK is a clock distribution unit signal 11
Among a large number of IntCLKs distributed to each part through, the one having the largest number of via gate stages and being sent to the end of the clock signal transmission line (in other words, the one having the maximum delay amount). Therefore, this PLL 10 has a delay amount (for convenience, “tpd
IntCL so that the phase difference corresponding to " _CD ") is always zero.
Adjust the K phase. Note that 13, 14, 15 _i and 16 _i are buffers (subscript i is 1, 2, 3, ...
......)

The "logic simulation method (1)" in this embodiment has the following points. First, a predetermined amount of delay for IntCLK (for convenience, "tp
d _PLL )) to provide a delay means. This delay means is conceptually shown by a buffer 10a provided in the PLL 10. The buffer 10a is placed near the source of IntCLK (PLL logic unit 10b), and the tpd _PLL set by the buffer 10a is a delay amount corresponding to the internal delay of the _PLL 10.

Next, a predetermined virtual clock signal (hereinafter referred to as "Im
ageCLK "), and the generation timing of this ImageCLK is defined as the total value of the above-mentioned tpd _PLL and tpd _CD (hereinafter" tpd
)) Only set before ExtCLK. FIG.
FIG. 4 is a time relationship diagram of each clock signal including ImageCLK. ImageCLK is defined by this simulation method, and is shifted in phase by tpd from ExtCLK.

Here, as described above, tpd is a tpd _PLL .
This is the total value of tpd _CD . That is, the internal delay amount of the _{PLL 10} (tpd _PLL ) and the delay amount of the feedback loop (tpd _PLL )
It is the value including the _CD ). Therefore, if you give the ImageCLK shown in the simulation, IntC after tpd _PLL
LK is obtained, further, since FeedbackCLK is obtained after tpd _CD, by appropriately setting the tpd _PLL and tpd _CD, and FeedbackCLK on simulation phase, it is made to coincide exactly with the actual ExtCLK phase It will be possible. As a result, a comprehensive test including the PLL 10 can be performed on the simulation, and the test accuracy can be sufficiently improved. In addition, regardless of the duty of ExtCLK (30% for convenience in the figure), In
The duty of tCLK can be accurately set to 50%, and the error of the clock signal pulse width in the chip can be avoided.

Next, the "logic simulation method (2)" in this embodiment has the following points. The definitions of tpd _PLL and tpd _CD are the same as in the above-described logic simulation method (1). This method (Part 2) uses IntCLK in the simulation as ExtCLK
A certain shorter time (tpd _CD ) than one cycle length (tcycle) of
The point is that it was delayed only. In other words, as shown in FIG. 3, IntCLK is more than tpd _PLL (= tc
The point is that it is delayed by ycle−tpd _CD ). As described above, there is a delay called tpd _CD between IntCLK and FeedbackCLK. Since IntCLK delayed by tpd _PLL from ExtCLK becomes FeedbackCLK further by this tpd _CD , the phase of FeedbackCLK and ExtCLK eventually match after tcycle.

As described above, according to this method (No. 2) as well, it is possible to perform a comprehensive test including the PLL in simulation, and it is possible to sufficiently improve the test accuracy (No. 1). It is possible to obtain the same action and effect as the above. The above method (1st and 2nd)
In, the tpd _PLL is adjusted assuming that the value of tpd _CD is known, but tpd _CD corresponds to the actual delay amount between IntCLK and FeedbackCLK (that is, the delay amount of the feedback loop). Look at the amount of delay
The setting value of tpd _PLL may be calculated.

FIG. 4 is a conceptual block diagram of the PLL logic unit 10b,
5 and 6 are waveform diagrams thereof. PLL logic unit 10b
Are first and second inverter gates 10c and 10d that invert ExtCLK input through the buffer 13, and
An output of the first inverter gate 10c (for convenience "signal b") and ExtCLK (for convenience "signal a") AND gate 10e and an output of the second inverter gate 10d The second AND gate 10f which takes the logical product of (the signal "b '" for convenience) and the signal a, and the output (the signal "c'" for convenience) of the second AND gate 10f are kept for a predetermined time (DL). ), And an OR gate 10hg that ORs the output of the delay circuit 10g (for convenience, "signal c"") and the output of the first AND gate 10e (for convenience," signal c "). It includes a flip-flop 10i that repeats a set state (output H level) and a reset state (output L level) at each rising edge of the output of the OR gate 10g (for convenience, "signal C ₁ ").

As shown in FIG. 5A, signal a and signal b
Have an antiphase relationship, and the signal b is delayed by the time T _{10c with} respect to the signal a. Time T _10c is the delay time of the first inverter gate 10c. The logical product signal (c) of these two signals (a, b) becomes H level only during the time T _10c , but in reality, the first AND gate 10
The signal is delayed by the delay time T _{10e of} e. On the other hand, as shown in FIG. 9B, the signal a and the signal b'are also in anti-phase relation, and the signal _b'is delayed with respect to the signal a by the time _T10d . The time T _10d is the second inverter gate 10d
Is the delay time. These two signals (a, b ') a logical product signal of (c') is an H level only during a time T _10d, in practice, delayed by a delay time T _10f of the second AND gates 10f, Further, the signal c ″ is delayed by the time DL.
become.

As shown in FIG. 6, the signal C ₁ is a signal in which a pair of positive pulses are repeated in each cycle of ExtCLK, and the first pulse is delayed by the time T _{10 e} from the rising edge of ExtCLK, and The second pulse is delayed by the time T _10f from the falling edge of ExtCLK. As described above, the flip-flop 10i generates IntCLK while repeating the set state and the reset state at each rising edge of the signal C ₁ , but the set state is the signal C 1.
_In response to the 1st pulse (rising edge) of 1,
The reset state responds to (the rising edge of) the second pulse of signal C ₁ . Therefore, the duty of IntCLK (the ratio of the time of H level and the time of L level) is determined only by the pulse interval of the signal C ₁ , and the interval is the delay circuit 1.
Since it can be freely controlled by the delay time (DL) of 0 g, the appropriate delay time (D
By selecting L), the duty of IntCLK can be accurately adjusted to 50% regardless of the duty of ExtCLK.

[0021]

According to the present invention, a test external clock signal (or virtual clock signal) is created in consideration of the internal delay of the PLL and the on-chip transmission delay of the clock signal. Therefore, comprehensive test including PLL becomes possible,
It is possible to sufficiently improve the test accuracy.

[Brief description of drawings]

FIG. 1 is a conceptual configuration diagram of an embodiment.

FIG. 2 is a waveform diagram of an example (method 1).

FIG. 3 is a waveform diagram of an example (method 2).

FIG. 4 is a conceptual configuration diagram of a PLL logic unit according to an embodiment.

5 is a waveform chart of each part of FIG.

FIG. 6 is a waveform diagram of IntCLK made by the PLL logic unit according to the embodiment.

FIG. 7 is a conceptual configuration diagram of a semiconductor integrated circuit incorporating a PLL.

FIG. 8 is a waveform diagram of FIG. 7.

FIG. 9 is a conceptual diagram of a conventional simulation.

[Explanation of symbols]

 10: PLL 10a: Buffer (delay means) 11: Clock distribution unit ExtCLK: External clock signal ImageCLK: Virtual clock signal IntCLK: Internal clock signal

Claims (2)

[Claims] 1. A semiconductor integrated circuit comprising a PLL for adjusting the phase of an internal clock signal supplied to the clock distribution unit so that the phase difference between the internal clock signal extracted from the final stage of the clock distribution unit and the external clock signal becomes zero. In a circuit logic simulation method, a delay unit is provided for giving a predetermined delay amount to the internal clock signal given to the clock distribution unit, and the internal clock signal given to the clock distribution unit and the clock are given to the predetermined delay amount. The delay amount with the internal clock signal extracted from the final stage of the distribution unit is added, a virtual clock signal whose phase is shifted earlier than the external clock signal by the added value is generated, and the virtual clock signal is used. Simulation
A logic simulation method characterized by performing a test using an actual external clock signal during the test. 2. A semiconductor integrated circuit comprising a PLL for adjusting the phase of an internal clock signal supplied to the clock distribution unit so that the phase difference between the internal clock signal extracted from the final stage of the clock distribution unit and the external clock signal becomes zero. A circuit logic simulation method, comprising: a delay unit for giving a predetermined delay amount to an internal clock signal given to the clock distribution unit, and subtracting the predetermined delay amount from a time corresponding to one cycle length of the external clock. The logic simulation method is characterized in that the external clock signal is delayed by a predetermined time to perform the simulation, and the test is performed using the actual external clock signal during the test.