JP3630870B2 - System clock generation circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a system clock generation circuit in a semiconductor device that is built in a semiconductor device and generates a two-phase clock in which high-level periods do not overlap.
[0002]
[Prior art]
A typical system clock used in a semiconductor device is a two-phase clock (hereinafter, simply referred to as a two-phase clock) in which the high-level periods do not overlap each other. A two-phase clock is easily generated using a phase locked loop (hereinafter referred to as PLL) having a signal delay function.
[0003]
FIG. 14 is a block diagram showing a system clock generation circuit in a conventional semiconductor device using a PLL. In the figure, reference numeral 400 denotes a PLL that outputs a two-phase clock. In the PLL 400, 1A is a delay circuit that delays an input signal, 3A is a signal that is introduced from several delay stages among a plurality of delay stages of the delay circuit 1A, and a one-phase clock P1 and others from the introduced signal A pulse generator for generating a phase clock P2 and 5 a clock input terminal X _in The phase comparator 6 compares the phase of the clock signal input from the buffer 8 with the phase of the one-phase clock P1 from the pulse generator 3A, and 6 corresponds to the phase difference output from the phase comparator 5. A charge pump 7 that outputs a voltage instruction signal and a low-pass filter 7 that smoothes the voltage instruction signal from the charge pump 6 and supplies a control voltage to the delay circuit 1A. The delay circuit 1A delays the input signal and constitutes a voltage controlled oscillator (VCO).
[0004]
Next, the operation will be described.
Clock input terminal X _in The clock signal input from is supplied as a reference clock signal to one input terminal of the phase comparator 5 via the buffer 8. In the circuit shown in FIG. 14, the clock signal is supplied to the clock output terminal X. _out Also supplied. A one-phase clock P1 from the pulse generator 3A is input to the other input terminal of the phase comparator 5 as a feedback clock signal. The phase comparator 5 detects a phase difference between signals input to both terminals and outputs a signal indicating the phase difference to the charge pump 6. The charge pump 6 outputs, for example, a signal instructing to increase the voltage when the phase of the clock P1 is delayed with respect to the phase of the reference clock signal according to the phase difference, and with respect to the phase of the reference clock signal. When the phase of the clock P1 is advanced, a signal instructing to lower the voltage is output.
[0005]
The voltage of the capacitor included in the low-pass filter 7 changes according to the signal from the charge pump 6. The voltage is supplied to the delay circuit 1A. The low-pass filter 7 also serves to determine characteristics such as the response speed of the PLL 400. The delay circuit 1A changes the frequency of the output signal according to the input control voltage. When the phase of the reference clock signal matches the phase of the clock P1, the output of the charge pump 6 does not change and the frequency of the output signal of the delay circuit 1A does not change.
[0006]
The delay circuit 1A is configured by a plurality of delay elements connected in cascade. The pulse generator 3A has a desired phase difference (skew) t out of the outputs of the delay elements. _d Several outputs are selected so that two-phase clocks P1 and P2 can be generated. FIG. 14 shows a case where three outputs are selected. The pulse generator 3A generates two-phase clocks P1 and P2 from the selected output signal. As described above, as shown in FIGS. 15A, 15B, and 15C, the clock input terminal X _in The same frequency as the frequency of the clock signal input from, and the desired phase difference t _d Two-phase clocks P1 and P2 having are generated.
[0007]
When testing a semiconductor device, a process of applying a predetermined signal from the outside to the semiconductor device at a certain point in time and testing an output signal based on the signal is required. For example, a predetermined signal for the test is given at the time of moving from the operation # 1 to the operation # 2 in FIG. However, if the signal is given unconditionally, the waveform of the signal becomes distorted based on the wiring capacitance and the like, causing a problem that a signal for testing is not set in the semiconductor device at a desired timing. Note that FIG. 15D illustrates a case where a signal instructing switching of the operation of a semiconductor device such as a microprocessor is input as a predetermined signal for testing.
Therefore, when a predetermined signal is given to the semiconductor device, the clock input terminal X _in It may be possible to stop the clock signal input from the clock or reduce the frequency of the clock signal and restart the clock signal input or restore the clock signal frequency when the setting of the predetermined signal is completed. It is done. However, according to this method, the PLL 400 is once out of synchronization. Accordingly, the semiconductor device does not operate normally during a period from when the input of the clock signal is restarted or after the frequency of the clock signal is returned to the original value until the synchronization of the PLL 400 is reestablished. In other words, even if a predetermined signal for testing is set in the semiconductor device, the semiconductor device cannot immediately start operating normally, and in effect the test cannot be performed.
[0008]
Therefore, when testing the semiconductor device, the two-phase clocks P1 and P2 are generated by the flip-flop without using the PLL 400, and the phase difference t by the delay element. _d It is conceivable to provide a method. FIG. 16 is a block diagram showing a configuration of a system clock generation circuit for realizing such a method. In the figure, 17 is a clock input terminal X. _in A switch for supplying the clock signal inputted from the PLL 400 to either the PLL 400 or the second pulse generator 16, 11 is either the clock P 1 by the PLL 400 or the clock P 1 by the second pulse generator 16. 13 is a switch for selecting either the clock P2 by the PLL 400 or the clock P2 by the second pulse generator 16.
[0009]
FIG. 17 is a circuit diagram showing an example of the configuration of the second pulse generator. As shown in FIG. 17, the second pulse generator 16 includes, for example, an inverting circuit (NOR circuit) 151 and 152 constituting a flip-flop, and an inverting circuit (on the input side of the NOR circuit 151) ( Inverter) 150, inverters 153 to 158 provided on the other input side of NOR circuit 151 and constituting delay elements, and inverters 159 to 164 constituting delay elements provided on one input side of NOR circuit 152.
[0010]
During actual operation of the semiconductor device, the switch 17 is connected to the clock input terminal X. _in Is set so that the clock signal input from the PLL 400 is input to the PLL 400, and the switches 11 and 13 are set to output the two-phase clocks P1 and P2 from the PLL 400 to each part of the semiconductor device. Therefore, the semiconductor device operates with a system clock generated by the PLL 400. Note that the actual operation time is an operation time that is not when testing a semiconductor device, that is, a time when the semiconductor device is incorporated in a predetermined system and operates to perform a function required in the system.
[0011]
When testing the semiconductor device, the switch 17 is connected to the clock input terminal X. _in The clock signal input from the second pulse generator 16 is set to be input to the second pulse generator 16, and the switches 11 and 13 are set to output the two-phase clocks P1 and P2 from the second pulse generator 16. Is done. Then, as shown in FIGS. 18A to 18D, when a predetermined signal for testing is set in the semiconductor device, the clock input terminal X _in The frequency of the clock signal input from is reduced. In this state, if a predetermined signal for testing is input to the semiconductor device, the signal is correctly set in the semiconductor device. However, according to such a circuit configuration, t in FIG. _d ', The skew between the two-phase clocks P1, P2 is the desired phase difference t _d It is not kept in. Therefore, the set signal may not be propagated normally in the semiconductor device.
[0012]
[Problems to be solved by the invention]
Since the system clock generation circuit in the conventional semiconductor device is configured as described above, there is a problem that when a test of the semiconductor device is performed, a signal for the test cannot be set in the semiconductor device at a desired timing.
[0013]
The present invention has been made in order to solve the above-described problems, and the phase difference between the two-phase clocks P1 and P2 is changed to a desired phase difference t during the test. _d An object of the present invention is to obtain a system clock generation circuit in a semiconductor device capable of generating two-phase clocks P1 and P2 having an arbitrary frequency while maintaining the above.
A technique similar to the present invention is described in Japanese Patent Laid-Open No. 2-89422.
[0014]
[Means for Solving the Problems]
According to the invention of claim 1 System clock generation circuit Is Phase-locked loop Having the same configuration as the first delay circuit in FIG. Phase-locked loop Introduce a control voltage at a frequency corresponding to the control voltage. Second signal As well as that Second signal A second delay circuit for delaying and outputting Second pulse generation that is connected to the second delay circuit and generates two-phase third and fourth clock signals that do not overlap the high-level period in response to the second signal delayed by the second delay circuit And a first state in which the first input clock signal is supplied to the phase locked loop and the second delay circuit is opened, and a second input clock signal is supplied to the phase locked loop and the third state. The first switching means for switching between the second state in which the input clock signal is supplied to the second delay circuit and the first and second two-phase generated by the first pulse generator in the phase-locked loop Second switching means for selecting at least one of the clock signal and the two-phase third and fourth clock signals generated by the second pulse generator and outputting the selected two-phase clock signal as a system clock signal It is equipped with.
[0016]
Claim 2 Related to the invention System clock generation circuit The first switching means is connected to the clock input terminal. Phase locked loop Provided between the reference clock signal input terminal First switch A clock input terminal and a second delay circuit When Established between Second switch It is the structure which contains.
[0017]
Claim 3 Related to the invention System clock generation circuit Is Phase synchronization including a first delay circuit that generates a first signal having a frequency corresponding to a control voltage based on a phase difference between a reference clock signal and a feedback clock signal, and delays and outputs the first signal A loop and the same configuration as the first delay circuit, wherein a control voltage is input to generate a second signal having a frequency corresponding to the control voltage, and the second signal is delayed and output. A pulse that is connected to the delay circuit and the second delay circuit and generates two-phase first and second clock signals that do not overlap the high-level period in accordance with the second signal delayed by the second delay circuit A first state in which the generator, the first input clock signal is supplied to the phase locked loop and the second delay circuit, and the second input clock signal is supplied to the phase locked loop and the first input clock The signal is second And switching means for switching a second state that is supplied to the delay circuit It is equipped with.
[0018]
Claim 4 Related to the invention System clock generation circuit The switching means is connected to the clock input terminal. Phase-locked loop The reference clock signal input terminal is provided with a switch.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below.
Embodiment 1 FIG.
1 is a block diagram showing a configuration of a system clock generating circuit in a semiconductor device according to a first embodiment of the present invention. In the figure, 200 is a PLL that outputs a two-phase clock, and 2 is a clock input terminal X. _in Is connected to the control voltage V from the low-pass filter 7 of the PLL 200. _cnt The second delay circuit 4 outputs a signal having a frequency corresponding to the signal and having a predetermined delay amount, and a signal 4 is introduced from a predetermined delay stage of the second delay circuit 2 to be a one-phase clock P1T. And a second pulse generator for generating the clock P2T of the other phase, 15 is a buffer 8 and a clock output terminal X _out It is a switch provided between and. In this case, the second pulse generator 4 corresponds to the pulse generator described in the claims. The switches 9 and 15 are an example of first switching means.
[0020]
In the PLL 200, 1 is a control voltage V from the low-pass filter 7. _cnt Signal f of frequency according to _vco And a first delay circuit 3 for outputting each signal having a predetermined delay amount, and 3 is introduced from several delay stages among the plurality of delay stages of the first delay circuit 1 It is a first pulse generator that generates a one-phase clock P1S and another-phase clock P2S during actual operation from a signal. A switch 10 selects one of the one-phase clock P1S from the first pulse generator 3 and the one-phase clock P1 selected by the switch 11 and supplies it to the phase comparator 5. The switch 11 selects one of the clock P1S generated by the PLL 200 and the clock P1T generated by the second pulse generator 4, and the switch 13 is selected from the clock P2S generated by the PLL 200 and the clock P2T generated by the second pulse generator 4. Select one of the following.
The other components are the same as those shown in FIG. 14, but the switches 11 and 13 are an example of the second switching means.
[0021]
FIG. 2 is a circuit diagram showing a configuration example of the first delay circuit and the second delay circuit. As shown in the figure, the first delay circuit 1 and the second delay circuit 2 have, for example, a drain connected to a power source V _CC And P-channel transistors 20, 22, 26, 30, 34, 38, 42, 46, 50, 54 whose gates are connected to the drain side of the N-channel transistor 21. The source of the P-channel transistor 20 is connected to the gate. The first delay circuit 1 and the second delay circuit 2 include the P-channel transistors 23, 27, 31, 35, 39, 43, 47, 51, 55 and the N-channel transistors 24, 28, 32, 36, respectively. , 40, 44, 48, 52, 56. The first stage inverter has a signal f _in Is applied, and the inverters are cascaded. N-channel transistors 24, 28, 32, 36, 40, 44, 48, 52, 56 of each inverter are connected to the drain side of N-channel transistors 25, 29, 33, 37, 41, 45, 49, 53, 57. Is done. The gates of the N-channel transistors 21, 25, 29, 33, 37, 41, 45, 49, 53, 57 are connected to the control voltage V _cnt Is applied.
[0022]
Outputs of the respective inverters are output as outputs R1 to R8 through inverters 61 to 68, respectively. When the circuit shown in FIG. 2 is applied to the first delay circuit 1, the output of the final stage inverter is the signal f. _vco It becomes. And the signal f _vco Is the signal f _in To the first stage inverter. When the circuit shown in FIG. 2 is applied to the second delay circuit 2, the output terminal of the final stage inverter is opened.
[0023]
In such a circuit, the nine inverters act as delay elements. The signal f _vco Is the signal f _in The circuit acts as a ring oscillator. The P-channel transistors 20, 22, 26, 30, 34, 38, 42, 46, 50, 54 and the N-channel transistors 21, 25, 29, 33, 37, 41, 45, 49, 53, 57 have a control voltage V _cnt Accordingly, the delay amount is controlled by controlling the current flowing through the inverter.
[0024]
When the circuit shown in FIG. 2 is applied to the first delay circuit 1, the outputs R1 to R8 correspond to the outputs R11, R21, R31, R41, R51, R61, R71, and R81. When the circuit shown in FIG. 2 is applied to the second delay circuit 2, the outputs R1 to R8 correspond to the outputs R12, R22, R32, R42, R52, R62, R72, and R82.
The circuit shown in FIG. 2 is an example of a delay circuit, and the first delay circuit 1 and the second delay circuit 2 can be configured by other circuit configurations. In addition, although an example in which there are nine delay elements is shown here, any number of delay elements may be used as long as the number of stages is an odd number. The number of stages of delay elements is determined according to the required level of oscillation frequency and the accuracy required for skew.
[0025]
FIG. 3 is a circuit diagram showing a configuration example of the first pulse generator. Here, the case where the first pulse generator 3 introduces the outputs R11, R31, R41 of the first delay circuit 1 is taken as an example. As shown in the figure, the first pulse generator 3 includes a logical product circuit (AND circuit) 85 that takes a logical product of the output R11 and the output R41. In addition, it has a transmission gate 87 and a P-channel transistor 88 that allow the output of the AND circuit 85 to pass under a predetermined condition, and an inverter 91 that inverts the passing output into a one-phase clock signal P1S. Furthermore, it has a transmission gate 89 and a P-channel transistor 90 that allow the output of the AND circuit 85 to pass under a predetermined condition, and an inverter 92 that inverts the passing output and generates a clock signal P2S of another phase.
[0026]
And it is controlled by the output R31 and has three D latches for creating a passage condition. The first D latch includes an inverter 70 for inverting the output R31, a transmission gate 71 controlled by the output R31, and two inverters 72 and 73. The second D latch includes an inverter 78 that inverts the output R31, a transmission gate 79 controlled by the output R31, and two inverters 80 and 81. The third D latch includes a transmission gate 83 controlled by the output R31 and two inverters 82 and 84. The output of the first D latch is transmitted to the second D latch via the two inverters 74 and 75 without being logically inverted. Further, the output of the first D latch is logically inverted via the inverter 76 and transmitted to the third D latch. The output of the second D latch is logically inverted via an inverter 77 and transmitted to the first D latch.
Note that the circuit shown in FIG. _vco Two-phase clock signals P1S and P2S having a frequency ½ of the above frequency are generated. The circuit shown in FIG. 3 is an example of a pulse generator, and the first pulse generator 3 can be configured by another circuit configuration.
[0027]
FIG. 4 is a circuit diagram showing an example of the configuration of the second pulse generator. Here, the case where the second pulse generator 4 introduces the outputs R12, R32, R42 of the second delay circuit 2 is taken as an example. As shown in the figure, the second pulse generator 4 has an inverted exclusive OR circuit (EXNOR circuit) 86 that inverts the exclusive OR of the output R12 and the output R42. Further, it has a transmission gate 87 and a P-channel transistor 88 that allow the output of the EXNOR circuit 86 to pass under a predetermined condition, and an inverter 91 that inverts the passing output to produce a one-phase clock signal P1T. Furthermore, it has a transmission gate 89 and a P-channel transistor 90 that allow the output of the EXNOR circuit 86 to pass under a predetermined condition, and an inverter 92 that inverts the passing output to generate a clock signal P2T of another phase. And in order to create a passage condition, it has two inverters 93 and 94 which let the output R32 pass, and two-stage inverters 95 and 96 which introduce the output of the inverter 93.
Note that the circuit shown in FIG. 4 is an example of a pulse generator, and the second pulse generator 4 can be configured by another circuit configuration.
[0028]
FIG. 5 is a circuit diagram showing one configuration example of the phase comparator. In this example, the phase comparator 5 includes an inverter 100 that receives the reference clock signal ref, an inverter 113 that receives the clock signal CLK, an NAND circuit 101 that receives the output of the inverter 100 and the output of the inverting AND circuit (NAND circuit) 111. , And an NAND circuit 106 for inputting the output of the inverter 113 and the output of the NAND circuit 112. Further, a first flip-flop composed of two NAND circuits 102 and 103 having the output of the NAND circuit 101 as a set input, and a second flip-flop composed of two NAND circuits 104 and 105 having the output of the NAND circuit 106 as a reset input. It has a flip-flop. Further, the NAND circuit 107 takes the logical product of the output of the NAND circuit 101 and the Q output of the first flip-flop, and the NAND circuit 108 calculates the output of the NAND circuit 106 and the inverted Q output of the second flip-flop. Logical AND. Then, the NOR circuit 109 and the inverter 110 take the logical sum of the outputs of the two NAND circuits 107 and 108.
[0029]
The NAND circuit 111 receives outputs of the NAND circuit 101, the NAND circuit 102, the inverter 110, and the NAND circuit 112. The NAND circuit 112 inputs the outputs of the NAND circuit 106, the NAND circuit 105, the inverter 110, and the NAND circuit 111. The output of the NAND circuit 111 is a U signal that instructs the charge pump 6 to increase the voltage, and the output of the NAND circuit 112 is a D signal that instructs the charge pump 6 to decrease the voltage.
Note that the circuit shown in FIG. 5 is an example of a phase comparator, and the phase comparator 5 can be configured by another circuit configuration.
[0030]
FIG. 6 is a circuit diagram showing a configuration example of the charge pump. In this example, the charge pump 6 has a circuit configuration that outputs a high level signal when the U signal becomes low level, and outputs a low level signal when the D signal becomes low level. . That is, the charge pump 6 includes the P channel transistor 122 to which the inversion level of the U signal is applied to the gate, the P channel transistors 123 and 126 having the gate connected to the source side of the P channel transistor 122, and the P channel transistors 123 and 126. A P-channel transistor 124 whose drain side is connected to the gate and a U signal is applied to the gate, an N-channel transistor 125 connected between the P-channel transistor 124 and the ground potential, and an input terminal for the U signal and the P-channel transistor 124 An N-channel transistor 121 is provided between the gate and the gate.
[0031]
The charge pump 6 includes a P-channel transistor 129 to which a D signal is applied to the gate, a P-channel transistor 128 connected between the drain of the P-channel transistor 129 and the power supply, and a gate connected to the source of the P-channel transistor 129. N-channel transistors 130 and 132, and an N-channel transistor 131 having a drain side connected to the gates of the N-channel transistors 130 and 132 and a D signal applied to the gate. The D signal input terminal is provided with an inverter 127 for adjusting the load capacity to the load capacity on the U side, that is, for compensating for the amount by the inverter 120.
[0032]
The circuit shown in FIG. 6 is an example of a charge pump, and the charge pump 6 can be configured by other circuit configurations. Voltage instruction signal P output from the charge pump 6 _out As a result, the capacitor 141 in the low-pass filter 7 configured as shown in FIG. The voltage of the capacitor 141 is the control voltage V _cnt Is supplied to the first delay circuit 1 and the second delay circuit 2.
[0033]
Next, the operation will be described.
Each element is selected so that the electrical characteristics of each element in the first delay circuit 1 match the electrical characteristics of each element in the corresponding second delay circuit 2.
During actual operation of the semiconductor device, the switch 15 is closed and the switch 9 is opened. The switches 11 and 13 are set so as to output the two-phase clocks P1S and P2S from the first pulse generator 3. Therefore, the clocks P1S and P2S are supplied to each part of the semiconductor device as two-phase clocks P1 and P2 which are system clocks. Further, the switch 10 is set so as to connect the output terminal of the clock P1 and the input terminal of the clock signal CLK of the phase comparator 5.
[0034]
And clock input terminal X _in The clock signal is input to the. Here, a case where a clock signal of 25 MHz is input is taken as an example. The clock signal is supplied as a reference clock signal ref to the phase comparator 5 through the buffer 8. The clock P1S is supplied to the other input terminal of the phase comparator 5 as the clock signal CLK. As shown in FIG. 8, the phase comparator 5 configured as shown in FIG. 5 makes the U signal significant when the phase of the clock P1S is delayed from the reference clock signal ref. In this example, the U signal is set to a low level. When the phase of the clock P1S is ahead of the reference clock signal ref, the D signal is made significant. That is, the D signal is set to a low level. When both phases match, neither the U signal nor the D signal is significant.
[0035]
In the charge pump 6 configured as shown in FIG. 6, when the U signal is in a significant state, the P-channel transistor 126 conducts, and as shown in FIG. 8, the output terminal of the charge pump 6 has a high level. Voltage instruction signal P _out Occurs. When the D signal is in a significant state, the N-channel transistor 132 is turned on, and a low level voltage instruction signal P is applied to the output terminal of the charge pump 6 as shown in FIG. _out Occurs. When neither the U signal nor the D signal is significant, neither P-channel transistor 126 nor N-channel transistor 132 conducts, and P _out As shown in the figure, neither the high level nor the low level appears at the output terminal of the charge pump 6.
[0036]
Voltage instruction signal P _out Charges and discharges the capacitor 141 of the low-pass filter 7 configured as shown in FIG. Therefore, the control voltage V which is the voltage of the capacitor 141 is _cnt Becomes higher when the phase of the clock P1S is later than the reference clock signal ref. When the phase of the clock P1S is ahead of the reference clock signal ref, the control voltage V _cnt Becomes lower. When both phases match, the control voltage V _cnt Is kept constant.
[0037]
The first delay circuit 1 constitutes a ring oscillator based on voltage control and a delay circuit. In the first delay circuit 1 configured as shown in FIG. _cnt Is applied to P-channel transistors 20, 22, 26, 30, 34, 38, 42, 46, 50, 54 and N-channel transistors 21, 25, 29, 33, 37, 41, 45, 49, 53, 57. The Therefore, the control voltage V _cnt The current flowing through each inverter in the first delay circuit 1 changes in accordance with the magnitude of. Since the delay amount changes according to the current change, the oscillation frequency and the delay amount of each delay stage change. As described above, since the first pulse generator 3 has the frequency dividing function, when the synchronization is established in the PLL 200, the output signal f _vco In this case, the frequency is stabilized at 50 MHz, which is twice the frequency 25 MHz of the clock P1S. Control voltage V _cnt Is stabilized to a voltage when the frequency of the clock signal CLK input to the phase comparator 5 is stable at 25 MHz. Therefore, when synchronization is established, the delay amount in each delay stage is also stabilized.
FIG. 9 is a timing chart showing waveforms of respective parts in the first delay circuit 1 and the first pulse generator 3. However, the outputs R51, R61, and R71 are not shown in FIG.
[0038]
The first pulse generator 3 configured as shown in FIG. 3 introduces outputs R11, R31, R41 from the first delay circuit 1, for example. Note that the delay stage from which the signal is extracted is determined according to the required skew amount. In this case, the AND circuit 85 takes the logical product of the output R11 and the output R41, and the output of the AND circuit 85 passes through the transmission gates 87 and 89 by controlling the outputs of the inverters 81 and 84. Outputs of the transmission gates 87 and 89 become two-phase clocks P1S and P2S via inverters 91 and 92, respectively. As described above, as shown in FIG. 9, the phase difference t corresponding to the delay amount by the three delay stages in the first delay circuit 1. _d1 Stable two-phase clocks P1S and P2S having the above are obtained.
The two-phase clocks P1S and P2S pass through the switches 11 and 13 and are supplied as system clocks to the respective units in the semiconductor device.
[0039]
When testing the semiconductor device, the switch 15 is opened and the switch 9 is closed. The switches 11 and 13 are set to output two-phase clocks P1T and P2T from the second pulse generator 4. Therefore, the clocks P1T and P2T are output as two-phase clocks P1 and P2. The switch 10 is set so that the one-phase clock P1S from the first pulse generator 3 is directly input to the input terminal of the clock signal CLK of the phase comparator 5.
[0040]
And clock input terminal X _in Clock signal is input to the clock input terminal X _out The clock signal is also input. For example, the clock input terminal X _in 25 MHz clock signal is input to the clock input terminal X _out Is supplied with another clock signal of 25 MHz. Therefore, in this case, the clock input terminal X _out The PLL 200 establishes synchronization using the clock signal input to the reference clock signal as a reference clock signal. The frequency of the reference clock signal is the same as the frequency of the reference clock signal when the semiconductor device is actually operated. Therefore, the control voltage V when the synchronization of the PLL 200 is established. _cnt Is the control voltage V during actual operation of the semiconductor device. _cnt Is the same.
[0041]
Control voltage V when PLL200 synchronization is established _cnt Is also input to the second delay circuit 2. The configuration of the second delay circuit 2 is the same as the configuration of the first delay circuit 1. That is, in the second delay circuit 2 configured as shown in FIG. _cnt Is applied to P-channel transistors 20, 22, 26, 30, 34, 38, 42, 46, 50, 54 and N-channel transistors 21, 25, 29, 33, 37, 41, 45, 49, 53, 57. The The electrical characteristics of each element in the first delay circuit 1 match the electrical characteristics of each element in the corresponding second delay circuit 2. Therefore, when the PLL 200 is synchronized, the delay amount of each delay stage in the second delay circuit 2 is equal to the delay amount of each delay stage in the first delay circuit 1. That is, the delay amount t shown in FIG. _R12 , T _R22 , T _R32 , T _R42 Is the delay amount t shown in FIG. _R11 , T _R21 , T _R31 , T _R41 be equivalent to. 9 and 10 show only the delay amount of the clock leading edge, the delay amounts of the clock trailing edges of the outputs R12, R22, R32, and R42 are also the clocks of the outputs R11, R21, R31, and R41. Equal to trailing edge delay.
[0042]
The second pulse generator 4 configured as shown in FIG. 4 introduces outputs R12, R32, and R42 from the second delay circuit 2. In the second pulse generator 4, the EXNOR circuit 86 performs an exclusive OR of the output R12 and the output R42, and the output of the EXNOR circuit 86 passes through transmission gates 87 and 89 controlled by the output R32. Outputs of the transmission gates 87 and 89 become two-phase clocks P1T and P2T via inverters 91 and 92, respectively. As described above, as shown in FIG. 10, the phase difference t corresponding to the delay amount by the three delay stages in the second delay circuit 2. _d2 Two-phase clocks P1T and P2T having Phase difference t _d2 Is the phase difference t shown in FIG. _d1 Is the same.
The clocks P1T and P2T pass through the switches 11 and 13 and are supplied as system clocks to each part in the semiconductor device.
[0043]
At the time of the test, for example, a predetermined signal for the test is given at the time of moving from the operation # 1 to the operation # 2 in FIG. In this case, as described above, if the signal is given unconditionally, the waveform of the signal is distorted based on the wiring capacitance or the like, and there is a possibility that the test signal is not set in the semiconductor device at a desired timing. Therefore, when a predetermined signal is given to the semiconductor device, the input terminal X _in Either stop the clock signal input to, or reduce the frequency of the clock signal. Then, a predetermined signal is input to the semiconductor device. Then input terminal X _in The input of the clock signal to is resumed, or the frequency of the clock signal is restored.
[0044]
Since the PLL 200 is always operating, the control voltage V _cnt Is stable at the same value as in actual operation. Therefore, the delay amount t of each delay stage in the second delay circuit 2 _d2 Is the delay t during actual operation _d And is invariant. That is, input terminal X _in The skew of the two-phase clocks P1T and P2T does not change even if the frequency of the clock signal input to the signal changes. Also, the skew is unchanged when the frequency of the clock signal is returned to the original value. Accordingly, when a predetermined signal for testing is given, the set signal is normally propagated in the semiconductor device.
[0045]
As described above, according to the first embodiment, the skew of the system clock does not change when a predetermined signal for testing is input to the semiconductor device. Therefore, the predetermined signal is correctly set in the semiconductor device, and the semiconductor device test is executed accurately. For example, an accurate test can be performed even when the operation of a semiconductor device such as a microprocessor is switched.
[0046]
Embodiment 2. FIG.
FIG. 12 is a block diagram showing a configuration of a system clock generation circuit in the semiconductor device according to the second embodiment of the present invention. In the figure, 300 is a PLL that outputs a two-phase clock, and 4A is a pulse generator having the same configuration as the second pulse generator 4 shown in FIG. In this case, the PLL 300 is provided with a frequency divider 18 that halves the input frequency between the first delay circuit 1 functioning as a VCO and the phase comparator 5. Other components are the same as those shown in FIG. 1, but the switch 15 is an example of a switching means. However, unlike the configuration shown in FIG. 1, the switches 9, 10, 11, and 13 are not provided here.
[0047]
FIG. 13 is a circuit diagram showing one configuration example of the frequency divider. In this example, the frequency divider 18 is composed of a two-stage flip-flop. The first stage flip-flop is two inverters 173 and 174, a transmission gate 172 that returns the output of the inverter 174 to the inverter 173 under a predetermined condition, and a transmission gate 171 that applies the output of the subsequent stage flip-flop to the inverter 173 under a predetermined condition. Composed. The latter flip-flop is composed of two inverters 177 and 178, a transmission gate 176 that returns the output of the inverter 178 to the inverter 177 under a predetermined condition, and a transmission gate 175 that applies the first-stage flip-flop output to the inverter 177 under a predetermined condition. Is done. The predetermined condition is generated by a signal input to the frequency divider 18 and a signal obtained by inverting the input signal by the inverter 170. The subsequent flip-flop supplies an output to the first flip-flop via the inverter 179 and outputs a signal in which the frequency of the input signal is halved.
[0048]
Next, the operation will be described.
Each element is selected so that the electrical characteristics of each element in the first delay circuit 1 match the electrical characteristics of each element in the corresponding second delay circuit 2.
During actual operation of the semiconductor device, the switch 15 is set to a closed state. And clock input terminal X _in The clock signal is input to the. Again, a case where a clock signal of 25 MHz is input is taken as an example. Input terminal X _in The clock signal input to is supplied as a reference clock signal ref to the phase comparator 5 via the buffer 8. The clock signal CLK from the frequency divider 18 is supplied to the other input terminal of the phase comparator 5. The phase comparator 5 makes the U signal significant when the phase of the clock signal CLK is delayed from the reference clock signal ref. When the phase of the clock signal CLK is ahead of the reference clock signal ref, the D signal is made significant. When both phases match, neither the U signal nor the D signal is significant.
[0049]
As in the case of the first embodiment, when the U signal is in a significant state, the charge pump 6 performs a high level voltage instruction signal P. _out Is output. When the D signal is in a significant state, the low level voltage indicating signal P _out Is output. When neither the U signal nor the D signal is significant, the charge pump 6 does not output a high level or a low level, as in the first embodiment. Voltage instruction signal P _out Accordingly, as in the case of the first embodiment, the low-pass filter 7 controls the control voltage V when the phase of the clock signal CLK is behind the reference clock signal ref. _cnt To increase. When the phase of the clock signal CLK is ahead of the reference clock signal ref, the control voltage V _cnt Lower. When both phases match, the control voltage V _cnt Keep constant.
[0050]
The first delay circuit 1 operates in the same manner as in the first embodiment and oscillates at 50 MHz. The frequency divider 18 introduces one of the outputs of the first delay circuit 1. FIG. 12 illustrates that the output R11 is introduced. The frequency divider 18 configured as shown in FIG. 13 halves the frequency of the output R11 to generate a clock signal CLK of 25 MHz, and supplies the clock signal CLK to the phase comparator 5. As described above, the control voltage V _cnt Is stabilized to a voltage when the frequency of the clock signal CLK input to the phase comparator 5 is stable at 25 MHz. Therefore, when the PLL 300 establishes synchronization, the delay amount in each delay stage of the first delay circuit 1 is also stabilized.
[0051]
In the second embodiment, the input terminal X is connected to the second delay circuit 2 during actual operation. _in From the low-pass filter 7 of the PLL 300 and a control voltage V _cnt Is entered. In the second delay circuit 2 configured as shown in FIG. _cnt Is applied to P-channel transistors 20, 22, 26, 30, 34, 38, 42, 46, 50, 54 and N-channel transistors 21, 25, 29, 33, 37, 41, 45, 49, 53, 57. The The electrical characteristics of each element in the second delay circuit 2 match the electrical characteristics of each element in the corresponding first delay circuit 1. Therefore, when the PLL 300 is established in synchronization, the delay amount of each delay stage in the second delay circuit 2 is equal to the delay amount of each delay stage in the first delay circuit 1.
[0052]
The pulse generator 4A configured as shown in FIG. 4 introduces outputs R12, R32, and R42 from the second delay circuit 2. The pulse generator 4A operates in the same manner as the second pulse generator 4 in the first embodiment, and generates two-phase clocks P1T and P2T. That is, as shown in FIG. 10, the phase difference t according to the delay amount by the three delay stages in the second delay circuit 2. _d2 Two-phase clocks P1T and P2T having In this case, the two-phase clocks P1T and P2T are output as two-phase clocks P1 and P2 which are system clocks.
[0053]
When the test of the semiconductor device is performed, the switch 15 is opened. Also, clock input terminal X _in Clock signal is input to the clock input terminal X _out The clock signal is also input. For example, the clock input terminal X _in 25 MHz clock signal is input to the clock input terminal X _out The other 25 MHz clock signal is input to. In this case, the clock input terminal X _out The PLL 300 establishes synchronization with the clock signal input to the reference clock signal ref. The frequency of the reference clock signal ref is the same as the frequency of the reference clock signal ref during actual operation of the semiconductor device. Therefore, the control voltage V when the synchronization of the PLL 300 is established. _cnt Is the control voltage V during actual operation of the semiconductor device. _cnt Is the same.
[0054]
As described above, the control voltage V when the synchronization of the PLL 300 is established. _cnt Is also input to the second delay circuit 2. That is, the delay amount of each delay stage in the second delay circuit 2 is equal to the delay amount during actual operation. Therefore, input terminal X _in The skew of the two-phase clocks P1T and P2T does not change even if the frequency of the clock signal input to the signal changes.
[0055]
Therefore, when a predetermined signal for testing is given, the set signal is normally propagated in the semiconductor device. For example, when the operation # 1 moves to the operation # 2 in FIG. _in Even when the frequency of the clock signal input to is reduced and then a predetermined signal for testing is given, the skew between the two-phase clocks P1T and P2T is the same as the skew in actual operation. is there. That is, input terminal X _in The skew of the two-phase clocks P1T and P2T does not change even if the frequency of the clock signal input to the signal changes. Also, the skew remains unchanged when the frequency of the clock signal is returned to the original value. Therefore, when a predetermined signal for the test is given, the set signal is normally propagated in the semiconductor device.
[0056]
As described above, according to the second embodiment, the skew of the system clock does not change when a predetermined signal for testing is input to the semiconductor device during the testing of the semiconductor device. Therefore, the predetermined signal is correctly set in the semiconductor device, and the semiconductor device test is executed accurately. For example, an accurate test can be performed even when the operation of a semiconductor device such as a microprocessor is switched. Furthermore, according to this embodiment, since only one pulse generator needs to be prepared, the circuit configuration is simplified as compared with the first embodiment.
[0057]
【The invention's effect】
As described above, according to the invention of claim 1, System clock generation circuit The In the phase-locked loop The same configuration as the first delay circuit, Phase-locked loop Introduce a control voltage at a frequency corresponding to the control voltage. Second signal As well as that Second signal A second delay circuit for delaying and outputting Second pulse generation that is connected to the second delay circuit and generates two-phase third and fourth clock signals that do not overlap the high-level period in response to the second signal delayed by the second delay circuit And a first state in which the first input clock signal is supplied to the phase locked loop and the second delay circuit is opened, and a second input clock signal is supplied to the phase locked loop and the third state. The first switching means for switching between the second state in which the input clock signal is supplied to the second delay circuit and the first and second two-phase generated by the first pulse generator in the phase-locked loop Second switching means for selecting at least one of the clock signal and the two-phase third and fourth clock signals generated by the second pulse generator and outputting the selected two-phase clock signal as a system clock signal Because it was configured to have The same control voltage is applied to the first delay circuit and the second delay circuit, and during the test, Even if the frequency of the clock signal input to the semiconductor device is changed, the skew of the system clock does not change. Therefore, the predetermined signal for the test is correctly set in the semiconductor device, and there is an effect that the test of the semiconductor device is accurately executed.
[0059]
Claim 2 According to the invention of System clock generation circuit The first switching means is connected to the clock input terminal. The first switch provided between the reference clock signal input terminals of the phase locked loop And provided between the clock input terminal and the second delay circuit Second switch Therefore, even if the operation of a semiconductor device such as a microprocessor having a clock input terminal and a clock output terminal is switched, there is an effect that the test of the semiconductor device is accurately executed.
[0060]
Claim 3 According to the invention of System clock generation circuit The Phase synchronization including a first delay circuit that generates a first signal having a frequency corresponding to a control voltage based on a phase difference between a reference clock signal and a feedback clock signal, and delays and outputs the first signal A loop and the same configuration as the first delay circuit, wherein a control voltage is input to generate a second signal having a frequency corresponding to the control voltage, and the second signal is delayed and output. A pulse that is connected to the delay circuit and the second delay circuit and generates two-phase first and second clock signals that do not overlap the high-level period in accordance with the second signal delayed by the second delay circuit A first state in which the generator, the first input clock signal is supplied to the phase locked loop and the second delay circuit, and the second input clock signal is supplied to the phase locked loop and the first input clock The signal is second And switching means for switching a second state that is supplied to the delay circuit Therefore, even if the same control voltage is applied to the first delay circuit and the second delay circuit and the frequency of the clock signal input to the semiconductor device is changed during the test, the skew of the system clock is maintained. It does not change. Therefore, the predetermined signal for the test is correctly set in the semiconductor device, and there is an effect that the test of the semiconductor device is accurately executed. Furthermore, since only one pulse generator needs to be prepared, the circuit configuration can be simplified.
[0061]
Claim 4 According to the invention of System clock generation circuit Switching means is connected to the clock input terminal. Phase-locked loop The switch is provided between the reference clock signal input terminal and the semiconductor device such as a microprocessor having a clock input terminal and a clock output terminal even when the operation of the semiconductor device is switched. Has the effect of being executed. Further, since only one pulse generator needs to be prepared, there is an effect that the circuit configuration is simplified.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a system clock generation circuit in a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration example of a first delay circuit and a second delay circuit.
FIG. 3 is a circuit diagram showing a configuration example of a first pulse generator.
FIG. 4 is a circuit diagram showing a configuration example of a second pulse generator.
FIG. 5 is a circuit diagram showing a configuration example of a phase comparator.
FIG. 6 is a circuit diagram showing a configuration example of a charge pump.
FIG. 7 is a circuit diagram illustrating a configuration example of a low-pass filter.
FIG. 8 is a timing chart showing operation timings of the phase comparator and the charge pump.
FIG. 9 is a timing chart showing the operation timing of the first pulse generator.
FIG. 10 is a timing chart showing the operation timing of the second pulse generator.
FIG. 11 is a timing chart representing an operation of the system clock generation circuit in the semiconductor device according to the first and second embodiments of the present invention.
FIG. 12 is a block diagram showing a configuration of a system clock generating circuit in a semiconductor device according to a second embodiment of the present invention.
FIG. 13 is a circuit diagram illustrating a configuration example of a frequency divider.
FIG. 14 is a block diagram showing a configuration of a system clock generation circuit in a conventional semiconductor device.
FIG. 15 is a timing diagram showing an operation of the system clock generation circuit shown in FIG. 14;
FIG. 16 is a block diagram showing a configuration of a system clock generation circuit in another conventional semiconductor device.
17 is a circuit diagram showing a configuration example of the pulse generator shown in FIG. 16. FIG.
FIG. 18 is a timing chart representing an operation of the system clock generation circuit shown in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 1st delay circuit, 2 2nd delay circuit, 3 1st pulse generator, 4 2nd pulse generator (pulse generator), 4A pulse generator, 9 switch (1st switching means), 11, 13 switches (second switching means), 15 switches (switching means, first switching means), 200, 300 phase locked loop.

Claims (4)

In a system clock generation circuit that generates a two-phase clock signal in which high-level periods do not overlap,
A first delay circuit that generates a first signal having a frequency corresponding to a control voltage based on a phase difference between the reference clock signal and the feedback clock signal, and outputs the first signal by delaying the first signal; A first pulse that is connected to one delay circuit and generates two-phase first and second clock signals that do not overlap high-level periods in accordance with the first signal delayed by the first delay circuit A phase-locked loop including a generator;
A second delay circuit having the same configuration as the first delay circuit, which receives a control voltage, generates a second signal having a frequency corresponding to the control voltage, and delays and outputs the second signal When,
A second delay circuit connected to a second delay circuit and generating a second and third clock signals of two phases whose high level periods do not overlap in accordance with the second signal delayed by the second delay circuit; A pulse generator;
A first state in which the first input clock signal is supplied to the phase-locked loop and the second delay circuit is opened, and a second input clock signal is supplied to the phase-locked loop and the third input clock First switching means for switching between a second state in which a signal is supplied to a second delay circuit;
Selecting at least one of the two-phase first and second clock signals generated by the first pulse generator and the two-phase third and fourth clock signals generated by the second pulse generator; Second switching means for outputting the selected two-phase clock signal as a system clock signal;
A system clock generation circuit comprising: The first switching means is provided between the first switch provided between the clock input terminal and the reference clock signal input terminal of the phase locked loop, and between the clock input terminal and the second delay circuit. 2. The system clock generation circuit according to claim 1, further comprising a second switch . In a system clock generation circuit that generates a two-phase clock signal in which high-level periods do not overlap,
A phase including a first delay circuit that generates a first signal having a frequency corresponding to a control voltage based on a phase difference between the reference clock signal and the feedback clock signal, and outputs the first signal by delaying the first signal. A synchronous loop,
A second delay circuit having the same configuration as the first delay circuit, which receives a control voltage, generates a second signal having a frequency corresponding to the control voltage, and delays and outputs the second signal When,
A pulse generator that is connected to a second delay circuit and generates two-phase first and second clock signals in which high-level periods do not overlap in accordance with the second signal delayed by the second delay circuit When,
A first state in which the first input clock signal is supplied to the phase-locked loop and the second delay circuit, a second input clock signal is supplied to the phase-locked loop, and the first input clock signal is the second Switching means for switching between the second state supplied to the delay circuit of
A system clock generation circuit comprising: 4. The system clock generation circuit according to claim 3, wherein the switching means includes a first switch provided between the clock input terminal and the reference clock signal input terminal of the phase locked loop.

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