JPH07168652A - Synchronous resetting circuit - Google Patents

Abstract

PURPOSE:To perform synchronous resetting by using the asynchronous reset terminal of a flip-flop. CONSTITUTION:An asynchronous reset signal is synchronized by a reset signal and clock synchronizing circuit 3 with a clock and a reset signal for evading malfunction due to a voltage drop in simultaneous operation is generated by a 1st delay circuit 4 and a 2nd delay circuit 5 to reset a 1st flip-flop groups 8, a 2nd flip-flop group 9, and a 3rd flip-flop group 10. When they are released from being reset, the ending edge of the reset signal is aligned through two reset ending timing circuits 6 and 7 to release all the flip-flops from being reset at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop synchronous reset circuit.

[0002]

2. Description of the Related Art A conventional synchronous reset circuit of this type is used for initializing a flip-flop for holding various information of an information processing device and compensating the state of the flip-flop after the initialization. FIG. 3 is a block diagram showing an example of such a conventional synchronous reset circuit.

The synchronous reset input terminal 10 and the asynchronous reset input terminal 22 are terminals for inputting signals for initializing the entire information processing apparatus, and a clock input terminal 12
Is a terminal for inputting a clock pulse for controlling a flip-flop of the information processing apparatus, and the data input terminal 23 is an input terminal for data processed by the information processing apparatus.

A first flip-flop group 19, a second flip-flop group 20, and a third flip-flop group 21.
Captures the state of the signal input to the data input terminal S by the rising edge of the clock input to the clock terminal C, holds it until the rising edge of the next clock, and inputs the clock to the asynchronous reset terminal R by It is a group of flip-flops that reset the states regardless of the input states of the data input terminal S and the clock terminal C and share the input terminal C in common. The number of each flip-flop group is a value obtained by dividing the number of flip-flops into a number that does not cause a malfunction due to a voltage drop that occurs when the flip-flops are simultaneously changed.

The reset signal clock synchronization circuit 13 is
It is a flip-flop that captures the input state of the data input terminal S at the rising edge of the clock pulse input to the clock input terminal C and holds it until the rising edge of the next clock pulse.

First delay circuit 14 and second delay circuit 15
Is a circuit for sending an asynchronous reset input signal for a certain period of time and outputting it. The delay value of the first delay circuit 14 is a value obtained by calculating the time for preventing the power reduction when a plurality of flip-flops operate in synchronization, and the delay value of the second delay circuit 15 is twice the delay value of the first delay circuit 14. Is the value of.

The first data signal input inhibiting circuit 16, the second data signal input inhibiting circuit 17, and the third data signal input inhibiting circuit 18 are circuits for forcibly resetting and outputting input data by a synchronous reset signal. is there.

Next, the operation will be described. In the case of resetting the information processing device having a plurality of flip-flops, first, the signal at the asynchronous reset input terminal 22 is set to the valid state. This is to prevent malfunction due to voltage drop caused by simultaneous operation of many flip-flops.

The valid state of the reset signal input to the asynchronous reset signal input terminal 22 is input to the reset terminal C of the first flip-flop group 19 to reset the first flip-flop group 19. In addition, the valid state of the asynchronous reset input signal is also input to the first delay circuit 14 and is output with a delay of a delay time for preventing malfunction due to simultaneous operation, and is transmitted to the input terminal C of the second flip-flop group 20,
The flip-flop group 20 is reset. The valid state of the asynchronous reset signal is also input to the second delay circuit 15, and is output from the first delay circuit 14 by a delay time that is longer than the delay time for preventing malfunction due to simultaneous operation with respect to the input signal. Is transmitted to the reset terminal C of the flip-flop group 21 and resets the third flip-flop group 21.

Then, in order to compensate the state of the flip-flop group after the reset is completed, the signal of the synchronous reset input terminal 10 is made valid while the signal of the asynchronous reset input terminal 22 is being made valid. The valid state of the synchronous reset input signal is synchronized by the reset signal clock synchronization circuit 13 with the rising edge of the clock signal input to the clock input terminal 12. The valid state of the synchronized reset signal synchronized with the clock signal is introduced to the first data signal input inhibition circuit 16, the second data signal input inhibition circuit 17, and the third data signal input inhibition circuit 18.

Each of the data signal input inhibiting circuits disconnects the data input to the data input terminal 23 from the input terminal of the flip-flop by the synchronous reset signal,
The flip-flop is reset by changing it to the reset state. To release the reset, first set the signal of the asynchronous reset input terminal 22 to the disabled state, and then, after a time longer than the delay value of the second delay circuit 15, set the signal of the synchronous reset signal terminal 10 to the disabled state. Done by.

The invalid state of the signal at the asynchronous reset input terminal 22 is directly transmitted to the first flip-flop group 19 and to the second flip-flop group 20 by the first delay circuit 1.
4 and then to the third flip-flop group 21,
It is transmitted through the second delay circuit 15. However, since the signal of the synchronous reset input terminal 10 is valid at this point, the first flip-flop group 19, the second flip-flop group 20 and the third flip-flop group 21 are not included in the data signal input inhibiting circuits 16 and 17. And 18, the input data is not transmitted to the data signal input terminal S.
The input data does not change and the reset state is maintained.

When the signal of the synchronous reset input terminal 10 becomes the invalid state, the invalid state of the synchronous reset signal is clock-synchronized by the reset signal clock synchronizing circuit 13, and then the first data signal inhibiting circuit 16 The signal is transmitted to the 2-data signal input suppression circuit 17 and the third data signal input suppression circuit 18.

When the synchronous reset of the first data signal input inhibiting circuit 16, the second data signal input inhibiting circuit 17 and the third data signal input inhibiting circuit 18 is released, the data signal is directly applied to the data input terminal S of the flip-flop. Transmitted
The reset state is released and the data of the flip-flop changes at the next rising edge of the clock. All flip-flops transmit the release state of the synchronous reset at the same time, and the operations are simultaneously started at the rising edge of the next clock.

[0015]

In the above-described conventional synchronous reset circuit, the information processing apparatus requires two reset terminals, a synchronous reset input terminal and an asynchronous reset input terminal, which leads to an increase in the number of terminals. Moreover, the procedure of the reset operation is complicated. Further, since the synchronizing signal is input to the data input terminal of the flip-flop, a circuit for synchronizing reset is required for the input data of the flip-flop, which increases the circuit scale and increases the signal delay time of the input data. There is a point.

[0016]

A synchronous reset circuit according to the present invention is a synchronous reset circuit in an information processing apparatus having a plurality of flip-flops each having an asynchronous reset terminal and operating in synchronization with a clock. A synchronization circuit that synchronizes the reset signal input to the asynchronous reset terminal with the clock of the flip-flop to be reset, and a plurality of signals in which the reset start timing of the reset signal synchronized by the synchronization circuit is deviated for a certain period of time are created. A delay circuit and a circuit for aligning all reset end timings of the signal shifted by the delay circuit and the reset signal synchronized by the synchronizing circuit are characterized.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1 showing an embodiment of the present invention,
In this embodiment, a synchronous reset input terminal 1, a clock input terminal 2, a reset signal, a clock synchronization circuit 3, a first delay circuit 4, a second delay circuit 5, a first reset end timing, a synchronization circuit 6, and a second reset end timing. Synchronization circuit 7,
First flip-flop group 8 and second flip-flop group 9
And a third flip-flop group 10.

In FIG. 1, a synchronous reset input terminal 1
Is a terminal for inputting a reset signal for initializing the entire information processing apparatus, and the clock input terminal 2 is
This is a terminal for inputting a clock pulse for controlling a flip-flop of the information processing device.

Each of the first flip-flop group 8, the second flip-flop group 9 and the third flip-flop group 10 is input to a data input terminal (not shown) at the rising edge of the clock input to the clock terminal C. The state of the signal is taken in and held until the next rising edge of the clock, and the asynchronous reset terminal R is input to reset the state regardless of the input states of the data input terminal S and the clock terminal C, and to the input terminal C. It is a group of flip-flops having a common clock input. The number of each flip-flop group is a value obtained by dividing the number of flip-flops into a number that does not cause a malfunction due to a voltage drop that occurs when the flip-flops are simultaneously changed.

The reset signal clock synchronization circuit 3 is a circuit for outputting the reset input signal in synchronization with the signal at the clock input terminal 2. The first delay circuit 4 supplies the reset signal clock-synchronized by the reset signal synchronization circuit 3 to
It is a circuit that delays the output for a time period that avoids the occurrence of malfunction due to simultaneous operations. The second delay circuit 5 inputs the input signal
This circuit delays the output by a time twice as long as that of the first delay circuit 4 for avoiding malfunction due to simultaneous operation.

First reset end timing synchronization circuit 6
The second reset end timing synchronization circuit 7 is a circuit that generates a reset signal for the flip-flop based on the output of the delay circuit and the output of the synchronous reset.

Next, the operation of this circuit will be described. The valid state of the reset input signal input from the synchronous reset input terminal 1 is output by the reset signal clock synchronization circuit 3 after synchronizing with the rising edge of the same clock as the flip-flop group to be reset input from the clock input terminal 2. It The valid state of the synchronized reset signal is input to the asynchronous reset terminal R of the first flip-flop group 8 to reset the first flip-flop group 8.

The valid state of the synchronous reset signal is also input to the first delay circuit 4 to generate a signal delayed by a time period for avoiding the occurrence of malfunction due to the simultaneous operation, and through the first reset end timing generating circuit 6, 2 flip-flop groups 9
Is input to the asynchronous reset terminal R of the second flip-flop group 9 and is reset. The valid state of the synchronous reset signal is also input to the second delay circuit 5 and generates a signal delayed by a time period for avoiding malfunction due to simultaneous operation with respect to the signal delayed by the first delay circuit 4. , And is input to the asynchronous reset terminal R of the third flip-flop group 10 via the second reset end timing generation circuit 7 to reset the third flip-flop group 10.

When the reset operation is finished, the invalidation state of the reset signal at the synchronous reset input terminal 1 is synchronized with the rising edge of the clock signal at the clock input terminal 2 by the reset signal clock synchronization circuit 3.
The first flip-flop group 8 is reset. The invalidated state of the synchronized reset signal is independent of the output states of the first delay circuit 4 and the second delay circuit 5 in the first reset end timing synchronization circuit 6 and the second reset signal end timing synchronization circuit 7. End the reset signal,
The reset state of the second flip-flop group 9 and the third flip-flop group 10 is released. The first flip-flop group 8, the second flip-flop group 9, and the third flip-flop group 10, which have been released from the reset state, all start operating at the rising edge of the next clock.

FIG. 2 is a timing chart of each point in FIG. That is, T1 is an input signal of the synchronous reset input terminal 1, which is the first flip-flop group 8, the second flip-flop group 9, and the third flip-flop group 10.
It is a reset input signal for resetting. T2 is an input signal of the clock input terminal 2 and is input to the reset signal clock synchronization circuit 3 and the first flip-flop group 8, the second flip-flop group 9 and the third flip-flop group 10, and the data input timing is set. It is a clock pulse to give.

T3 is an output signal of the synchronous reset signal clock synchronization circuit 1, which is a signal obtained by synchronizing the reset input signal of T1 with the rising edge of the clock pulse of T2. T4 is an output signal of the first delay circuit 4, which is a signal obtained by delaying the synchronous reset signal of T3 by a period for preventing malfunction due to voltage drop due to simultaneous operation. T5 is an output signal of the second delay circuit 5, which is a signal obtained by delaying the synchronous reset signal of T3 by a time longer than that of T4 by a time for preventing malfunction due to voltage drop due to simultaneous operation.

T6 is an output of the first reset end timing synchronization circuit 6, and is a reset signal of the second flip-flop group 9 in which the synchronous reset signal of T3 and the signal passed through the delay circuit of T4 are combined. T7 is an output signal of the second reset end timing synchronization circuit 7, and is a reset signal of the third flip-flop group 10 which is a combination of the synchronous reset signal of T3 and the signal passed through the delay circuit of T5.

The reset signal of the first flip-flop group 8 is T3, the reset signal of the second flip-flop group 9 is T6, and the reset signal of the third flip-flop group 10 is T7.

The valid state of the reset operation is that T6 is longer than T3 in time for preventing malfunction due to simultaneous operation (ab).
Only after a delay, T7 becomes effective (b-
Only after c), it becomes effective. At the end of the reset, T3 is d, T6 is e, T7 is f, which are all the same, and the operations are started all at the rising edge g of the next clock.

[0030]

As described above, in the synchronous reset circuit according to the present invention, the number of reset input terminals is one and the clock is synchronized by the flip-flop to make the synchronous reset signal. Is also simplified. Also, since there is no circuit for synchronous reset in front of the data input terminal of the flip-flop and synchronous reset is performed by the asynchronous reset terminal, it is possible to reduce the circuit scale, and the data signal input of the flip-flop can be reduced. This has the effect that the delay time can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a timing chart of the embodiment shown in FIG.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 Synchronous reset input terminal 2 Clock input terminal 3 Reset signal Clock synchronization circuit 4 First delay circuit 5 Second delay circuit 6 First reset end timing synchronization circuit 7 Second reset end timing synchronization circuit 8 First flip-flop group 9 Second Flip-Flop Group 10 Third Flip-Flop Group 11 Reset Input Terminal 12 Clock Input Terminal 13 Reset Signal Clock Synchronization Circuit 14 First Delay Circuit 15 Second Delay Circuit 16 First Data Signal Input Inhibition Circuit 17 Second Data Signal Input suppression circuit 18 Third data signal input suppression circuit 19 First flip-flop group 20 Second flip-flop group 21 Third flip-flop group 22 Asynchronous reset input terminal 23 Data input terminal

Claims (2)

[Claims] 1. In a synchronous reset circuit in an information processing apparatus having a plurality of flip-flops that have asynchronous reset terminals and operate in synchronization with a clock, a reset signal input to the asynchronous reset terminals of the flip-flops is a reset target. A synchronizing circuit for synchronizing with the clock of the flip-flop, a delay circuit for creating a plurality of signals in which the reset start timing of the reset signal synchronized by the synchronizing circuit is shifted by a fixed time, and a signal shifted by the delay circuit And a circuit for aligning all reset end timings of reset signals synchronized by the synchronization circuit. 2. The synchronous reset circuit according to claim 1, wherein the fixed time period is a time period required to avoid occurrence of malfunction due to simultaneous operation of the flip-flops.