JPH11305887A - Method for controlling microcontroller and microcontroller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the processing of a peripheral circuit from being made invalid at the time of transition to a low power consumption mode. SOLUTION: A method for controlling a microcontroller 100 equipped with a CPU 110, peripheral circuit 120, and clock supply controlling part 130 for individually outputting a clock C2 for a CPU for driving the CPU and a peripheral clock C3 for driving the peripheral circuit includes a process for judging whether or not the peripheral circuit is operated and a process for switching the CPU clock and the peripheral clock to a low power consumption mode when it is judged that the peripheral circuit is not operated in the process. The method includes also a process for switching the CPU clock to the low power consumption mode when it is judged that the peripheral circuit is operated in the process, and for switching the peripheral clock to the low power consumption mode after the operation of the peripheral circuit is ended. Therefore, the processing of the peripheral circuit can be prevented from being made invalid.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control method for a microcontroller and a microcontroller. In particular, the present invention relates to a central processing unit (hereinafter referred to as a "CPU"), a storage device such as a ROM or a RAM, and a serial IO on a single chip. The present invention relates to a control method and a microcontroller for a microcontroller having a built-in peripheral circuit such as an A / D converter and a clock supply circuit.

[0002]

2. Description of the Related Art Since a microcontroller can perform various controls by a program to be created, it is used for control applications in various fields. Among such control applications, there are control applications such as portable terminals and notebook personal computers that require low power consumption by battery operation. In such a control application, in order to extend the operation time by the battery,
It is necessary to reduce power consumption while performing high-speed processing by gradually changing the operation state to a mode that operates at high power but operates at high speed or a mode that operates at low speed and consumes low power. It has been.

Some microcontrollers include a central processing unit (hereinafter referred to as a “CPU”), a storage device such as a ROM and a RAM, and peripheral circuits such as a serial IO and an AD converter. In such a microcontroller, the clock of a functional block that is not operating is stopped, or the microcontroller is operated at a low speed in a low-speed mode by supplying a clock obtained by dividing the input clock as the operating clock of the CPU and peripheral circuits. Therefore, the power consumption was reduced.

In the microcontroller, when the low-speed mode is set, a clock obtained by dividing the input clock is supplied to the CPU and peripheral circuits as an operating clock. The time constant of the timer and the transfer rate of serial transfer fluctuate. For this reason, every time the operation clock is switched by the frequency division, it is necessary to change the time constant of the timer and the set value of the serial transfer rate, which causes a problem that the processing becomes complicated. Further, when the CPU is operated at a low speed in the low-speed mode, the peripheral circuits also operate at a low speed, and there is a problem that only a CPU with large power consumption cannot be operated at a low speed.

As a configuration of a microcontroller that does not cause the above problem, there is a configuration in which a clock to a CPU and a clock to peripheral circuits such as a serial IO and an AD converter are generated and supplied independently. However, in this configuration, synchronization between the CPU clock and the peripheral clock is required, and there is a problem that the circuit scale becomes large because the circuit can be synchronized even when the fluctuation of the clock is considered.

[0006] In order to solve the above problems, a microcontroller capable of setting operation processing of a CPU independently of peripheral circuits and suppressing the circuit scale is known. Some are shown in the gazette. The configuration of a conventional microcontroller 300 as disclosed in the publication will be described with reference to FIG.

[0007] Inside the microcontroller 300,
A CPU 310, a peripheral circuit 320 including a serial IO 321 and an AD converter 322, a clock supply control unit 330, and a memory unit 340 including a ROM 341 and a RAM 342 are connected via an internal bus 350.

The CPU 310 performs an operation based on the data stored in the memory unit 340, and further performs
0 and the clock supply control unit 330 are controlled. The serial IO 321 is a circuit that communicates with an external circuit using serial data, and the AD converter 322 is a circuit that converts analog data input from the outside into digital data.

[0009] The clock supply control unit 330 includes an external clock C supplied from outside the microcontroller 300.
CPU which is a clock for CPU 310 based on 0
A clock C2 and a peripheral clock C3 for the peripheral circuit 320 are generated. CPU clock C2
Is supplied to the CPU 310, and the peripheral clock C3 is supplied to the peripheral circuits 320 such as the serial IO 321 and the AD converter 322.

The structure of the clock supply control unit 330 is shown in FIG.
This will be described with reference to FIG. Clock supply control unit 330
Is an external clock control unit 331 that controls an external clock.
The CPU clock control unit 332 and the peripheral clock control unit 333 connected to the external clock control unit 331; the external clock control unit 331 and the CPU clock control unit 33
And a clock stop mode control circuit 334 for controlling the clock stop mode control circuit 2.

The external clock control unit 331 includes an external clock C supplied from outside the microcontroller 300.
Based on 0, an internal clock C1 serving as a reference for the clock supply control unit 330 is generated. CPU clock controller 3
32 generates a CPU clock C2 synchronized with the internal clock C1 supplied from the operation clock generator 331. The clock stop mode control circuit 334 described later
When the CPU clock stop instruction signal ST2 is supplied from the CPU, the generation of the CPU clock C2 is stopped. The peripheral clock control unit 333 includes a peripheral clock C3 synchronized with the internal clock C1 supplied from the external clock generation unit 331.
Generate

The clock stop mode control circuit 334 includes an external clock control unit 331 and a CPU clock control unit 33.
2 is a circuit for controlling the control circuit 2. The clock stop mode control circuit 334 has a control register that determines the clock supply mode to one of a CPU clock stop mode, a standby mode, and a clock stop release mode. This control register is set via the internal bus 350 by the CPU 310 or the like.

When a value specifying the CPU clock stop mode is set in the control register by the CPU 310, the clock stop mode control circuit 334 sends the CPU clock stop instruction signal ST2 to the CPU clock control unit 332.
To supply. When being supplied with the CPU clock stop instruction signal ST2 from the clock stop mode control circuit 334, the CPU clock control unit 332 stops generating the CPU clock C2. Thus, the clock supply circuit 330
Is set to the CPU clock stop mode. In the CPU clock stop mode, the peripheral clock C3 is not stopped, the peripheral circuit 320 is operating, and the CPU 310 stops operating.

On the other hand, when the value indicating the standby mode is set in the control register by the CPU 310, the clock stop mode control circuit 334 supplies the internal clock stop instruction signal ST 1 to the operation clock generator 331. When receiving the internal clock stop instruction signal ST1 from the clock stop mode control circuit 334, the operation clock generator 331 stops generating the internal clock C1. Thereby, the CPU clock control unit 332 sets the CPU clock C2
And the peripheral clock control unit 333 stops the generation of the peripheral clock C3, and the clock supply control unit 330
Is set to the standby mode. In this standby mode, C
Since both the PU clock C2 and the peripheral clock C3 stop, the microcontroller 300 enters a standby state in which the operation is completely stopped.

When the control register of the clock stop mode control circuit 334 is set to a value designating clock stop release by an external signal in the above-described CPU clock stop mode or standby mode, the clock stop release state is set. And the clock stop mode control circuit 334
The generation of the all-clock stop instruction signal ST1 or the CPU clock stop instruction signal ST2 is stopped. In this case, the operation clock generator 331 generates the internal clock C1,
The CPU clock controller 332 generates a CPU clock C2, and the peripheral clock controller 333 generates a peripheral clock C3.

The microcontroller 300 described above
According to this, the speed of the CPU clock C2 can be changed independently of the peripheral clock C3 without changing the reference internal clock C1. Therefore, the peripheral clock C
3 while the peripheral circuit 320 is operated at a constant speed, and only the CPU clock C2 is reduced to a low speed.
It is possible to reduce the power consumption by operating only the CPU 310 at low speed.

[0017]

By the way, in the microcontroller 300, in the standby mode for maximizing low current consumption, the clock stop mode control circuit 334 is used.
The CPU clock C2 and the peripheral clock C3 are stopped by stopping the internal clock C1 with the all clock stop instruction signal ST1 generated by the CPU. However, when the peripheral circuit 320 such as the serial IO 321 or the AD converter 322 shifts to the standby mode while operating, the processing data before the shift becomes invalid, and the software shift to the standby mode state requires software judgment by the program. There was a problem of becoming.

The present invention has been made in view of the above problems of the conventional microcontroller control method and microcontroller, and an object of the present invention is to provide a CPU clock even in a standby mode for maximizing low power consumption. To provide a new and improved microcontroller control method and microcontroller capable of controlling a peripheral clock.

[0019]

According to the first aspect of the present invention, there is provided an arithmetic processing unit, a peripheral circuit, an arithmetic processing unit clock for driving the arithmetic processing unit, and a peripheral circuit. A method for controlling a microcontroller comprising a clock supply control unit capable of individually outputting a clock for a peripheral circuit to be changed, and determining whether the peripheral circuit is operating when a mode change signal to a low power consumption mode is generated And, if it is determined in the step that the peripheral circuit is not operating, the operation processing unit clock and the peripheral circuit clock are switched to the low power consumption mode, and the peripheral circuit operates in the step. If it is determined that the operation is performed, the operation processing clock is switched to the low power consumption mode. Control method for a microcontroller, which comprises a step of switching the cost power mode is provided. In the transition to the low power consumption mode, the peripheral circuit may output a peripheral operation end signal to the clock supply control unit when the operation ends.

With this configuration, when the entire microcontroller is shifted to the low power consumption mode while the peripheral circuit is operating, the clock supply control unit can determine whether the peripheral circuit is operating. When the circuit is operating, it is possible to hold the clock supply to the operating peripheral circuit. Therefore, even if the peripheral circuit is operating when the entire microcontroller is shifted to the low power consumption mode, the supply of the peripheral clock is maintained until the operation is completed, and the operation of the entire microcontroller is completed simultaneously. Since this shifts to the low power consumption mode, it is not necessary to invalidate processing data of peripheral circuits such as a serial IO and an AD converter.

Further, when shifting to the low power consumption mode, it is possible to shift the entire microcontroller to the low power consumption mode without requiring software judgment by a program.

The low power consumption mode may be a low-speed mode in which the clock for the processing unit and / or the clock for the peripheral circuit is set to a low-speed clock. It is more preferable to be in a standby mode for stopping. According to the standby mode, the maximum power consumption can be reduced by stopping the supply of the clock.

According to the second aspect of the present invention, the arithmetic processing unit, the peripheral circuit, and the clock for the arithmetic processing unit for driving the arithmetic processing unit and the clock for the peripheral circuit for driving the peripheral circuit can be individually output. A control method for a microcontroller having a clock supply control unit, the method comprising: when a mode change signal to a low power consumption mode is generated, determining whether a peripheral circuit is operating; If it is determined that the peripheral circuit is not operating, the operation processing unit clock and the peripheral circuit clock are switched to the low power consumption mode. The processing unit stops the arithmetic processing, and switches the operation processing unit clock and the peripheral circuit clock to the low power consumption mode after the operation of the peripheral circuit is completed. Control method for a microcontroller, characterized in that it comprises is provided. In the transition to the low power consumption mode, the peripheral circuit may output a peripheral operation end signal to the arithmetic processing unit when the operation is completed.

With this configuration, when the entire microcontroller is shifted to the low power consumption mode while the peripheral circuit is operating, the central processing unit can determine whether the peripheral circuit is operating. When the circuit is operating, the central processing unit does not perform the arithmetic processing, and can maintain the supply of the clock to the operating peripheral circuit.
Therefore, even if the peripheral circuit is operating when the entire microcontroller is shifted to the low power consumption mode, the supply of the peripheral clock is maintained until the operation is completed, and the operation of the entire microcontroller is completed simultaneously. Shifts to the low power consumption mode.
It is not necessary to invalidate the processing data of peripheral circuits such as the A / D converter.

Further, when shifting to the low power consumption mode, it is possible to shift the entire microcontroller to the low power consumption mode without requiring software judgment by a program.

The low power consumption mode may be a low-speed mode in which the processing unit clock and / or peripheral circuit clock is set to a low-speed clock. It is more preferable to be in a standby mode for stopping. According to the standby mode, the maximum power consumption can be reduced by stopping the supply of the clock.

According to the third aspect of the present invention, there is provided a microcontroller including an arithmetic processing unit driven by a clock for an arithmetic processing unit and a peripheral circuit driven by a clock for a peripheral circuit. A mode change device for generating a mode change signal to a power mode, a judgment device for judging whether or not the peripheral operation circuit is operating upon input of the mode change signal, and a judgment that the peripheral operation circuit is not operating in the judgment device If it is determined, the operation processing unit clock and the peripheral circuit clock are switched to the low power consumption mode. If the determination unit determines that the peripheral operation circuit is operating, the operation processing unit clock is changed to the low power consumption mode. A clock supply control unit that switches to the low power consumption mode, but switches to the low power consumption mode after peripheral circuit operation is completed. Microcontroller comprising a are provided. The determining device may determine whether the peripheral circuit is operating according to a peripheral operation end signal generated when the peripheral circuit ends its operation.

According to this configuration, when the entire microcontroller is shifted to the low power consumption mode while the peripheral circuit is operating, the clock supply control unit can determine whether the peripheral circuit is operating or not. When the circuit is operating, it is possible to hold the clock supply to the operating peripheral circuit. Therefore, even if the peripheral circuit is operating when the entire microcontroller is shifted to the low power consumption mode, the supply of the peripheral clock is maintained until the operation is completed, and the operation of the entire microcontroller is completed simultaneously. Since this shifts to the low power consumption mode, it is not necessary to invalidate processing data of peripheral circuits such as a serial IO and an AD converter.

Further, when shifting to the low power consumption mode, it is possible to shift the entire microcontroller to the low power consumption mode without requiring software judgment by a program.

The low power consumption mode may be a low-speed mode in which the clock for the processing unit and / or the clock for the peripheral circuit is set to a low-speed clock. It is more preferable to be in a standby mode for stopping. According to the standby mode, the maximum power consumption can be reduced by stopping the supply of the clock.

According to a fourth aspect of the present invention, there is provided a microcontroller including an arithmetic processing unit driven by a clock for an arithmetic processing unit and a peripheral circuit driven by a clock for a peripheral circuit. A mode change device for generating a mode change signal to a power mode, a judgment device for judging whether or not the peripheral operation circuit is operating upon input of the mode change signal, and a judgment that the peripheral operation circuit is not operating in the judgment device If it is determined, the arithmetic processing unit clock and the peripheral circuit clock are switched to the low power consumption mode. If the determination unit determines that the peripheral operation circuit is operating, the arithmetic processing unit executes the arithmetic processing. Supply control for stopping the operation and switching to the low power consumption mode after the operation of the peripheral circuit is completed Microcontroller comprising bets is provided. The determining device may determine whether the peripheral circuit is operating according to a peripheral operation end signal generated when the peripheral circuit ends its operation.

With this configuration, when the entire microcontroller is shifted to the low power consumption mode while the peripheral circuit is operating, the central processing unit can determine whether the peripheral circuit is operating. When the circuit is operating, the central processing unit does not perform the arithmetic processing, and can maintain the supply of the clock to the operating peripheral circuit.
Therefore, even if the peripheral circuit is operating when the entire microcontroller is shifted to the low power consumption mode, the supply of the peripheral clock is maintained until the operation is completed, and the operation of the entire microcontroller is completed simultaneously. Shifts to the low power consumption mode.
It is not necessary to invalidate the processing data of peripheral circuits such as the A / D converter.

Further, when shifting to the low power consumption mode, it is possible to shift the entire microcontroller to the low power consumption mode without requiring software judgment by a program.

The low power consumption mode may be a low-speed mode in which the clock for the processing unit and / or the clock for the peripheral circuit is set to a low-speed clock. It is more preferable to be in a standby mode for stopping. According to the standby mode, the maximum power consumption can be reduced by stopping the supply of the clock.

[0035]

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
A preferred embodiment of a control method of a microcontroller and a microcontroller according to the present invention will be described in detail. In this specification and the drawings, components having substantially the same function and configuration are denoted by the same reference numerals, and redundant description is omitted.

(First Embodiment) A microcontroller 100 according to a first embodiment is as shown in FIG. 1 and FIG. Hereinafter, the configuration of the microcontroller 100 will be described with reference to FIGS.

Inside the microcontroller 100,
The CPU 110, the peripheral circuit 120 including the serial IO 121 and the AD converter 122, the clock supply control unit 130, and the memory unit 140 including the ROM 141 and the RAM 142 are connected via the internal bus 150.

The CPU 110 performs an operation based on the data stored in the memory unit 140,
0 and the clock supply control unit 130 are controlled. CPU1
10 outputs a standby mode signal S1 to the clock supply control unit 130 when an instruction to shift to the standby mode is issued by the memory unit 140. The operation when the standby mode signal S1 is output from the CPU 110 to shift to the standby mode will be described later.

The peripheral circuit 120 includes a serial IO 121, an AD converter 122, and the like. Serial IO121
Is a circuit that communicates with an external circuit using serial data.
The AD converter 122 is a circuit that converts analog data input from the outside into digital data. The peripheral circuit 120 outputs a peripheral operation end signal S2 to the clock supply control unit 130 when the operation of each component configuring the peripheral circuit 120 ends. The operation when the peripheral circuit 120 outputs the peripheral operation end signal S2 will be described later.

The clock supply control unit 130 controls an external clock C supplied from outside the microcontroller 100.
CPU which is a clock for CPU 110 based on 0
A clock C2 and a peripheral clock C3 which is a clock for the peripheral circuit 120 are generated. CPU clock C2
Is supplied to the CPU 110, and the peripheral clock C3 is supplied to the peripheral circuits 120 such as the serial IO 121 and the AD converter 122.

The structure of the clock supply control unit 130 is shown in FIG.
This will be described with reference to FIG. Clock supply control unit 130
Is an external clock control unit 131 that controls an external clock.
And a CPU clock control unit 132 and a peripheral clock control unit 133 connected to the external clock control unit 131.

The external clock control section 131 receives an external clock C supplied from outside the microcontroller 100.
Based on 0, an internal clock C1 serving as a reference for the clock supply control unit 130 is generated. CPU clock control unit 1
32 generates a CPU clock C2 synchronized with the internal clock C1 supplied from the operation clock generator 131. The peripheral clock control unit 133 generates a peripheral clock C3 synchronized with the internal clock C1 supplied from the external clock generation unit 131.

The operation of the microcontroller 100 configured as described above will be described with reference to the timing chart shown in FIG. The description will be given in chronological order according to the symbols T1 and T2 indicating the time shown in FIG.

At time T 1, an instruction to shift to the standby mode is issued from the memory unit 140 to the CPU 11 via the internal bus 150.
0, the CPU 110 decodes this instruction and outputs the standby mode signal S1 to the clock supply control unit 130. The external clock control unit 131 that has received the standby mode signal S1
A signal for stopping the PU clock C2 is output, and the CPU clock control unit 132 stops the CPU clock C2,
U110 shifts to the standby mode.

At this time, when the operation of the peripheral circuit 120 has been completed, the external clock control section 131 is input because the peripheral operation end signal S2 output from the peripheral circuit 120 is input to the clock supply control section 130. Stops the internal clock C1, and the entire microcontroller 100 shifts to the standby mode.

On the other hand, when the operation of the peripheral circuit 120 is not completed, the peripheral clock control unit 133 continues to supply the peripheral clock C3 to the peripheral circuit 120, and the CPU 110 enters a standby state and the peripheral circuit 120 operates. Become.
Thereafter, when the operation of the peripheral circuit 120 ends at time T2, the peripheral circuit 120 outputs a peripheral operation end signal S2 to the clock supply control unit 130. The external clock control unit 131 stops the internal clock C1, and
Stops, the peripheral clock C3 output from the peripheral clock supply control unit 133 also stops, and the entire microcontroller 100 shifts to the standby mode.

The microcontroller 100 according to the present embodiment is configured and operated as described above, so that the following excellent effects can be obtained. In other words, when the peripheral circuit 120 is operating when shifting to the standby mode, the peripheral clock C3 is supplied until the operation is completed. Then, at the same time when the operation of the peripheral circuit 120 ends, the entire microcontroller 100 shifts to the standby mode. Therefore, the processing data of the serial IO 121 and the AD converter 122 becomes valid.

Further, when shifting to the standby mode, the entire microcontroller 100 can shift to the standby mode without requiring software judgment by a program.

(Second Embodiment) A microcontroller 200 according to a second embodiment is as shown in FIGS. Hereinafter, the configuration of the microcontroller 200 will be described with reference to FIGS. The microcontroller 200 is a microcontroller 1 according to the first embodiment shown in FIGS.
This is a modification of the first embodiment, and is characterized in that a peripheral operation end signal from the peripheral circuit 220 is directly output to the CPU 210 instead of the clock supply control unit 230.

Inside the microcontroller 200,
A CPU 210, a peripheral circuit 220 including a serial IO 221 and an AD converter 222, a clock supply control unit 230, and a memory unit 240 including a ROM 241 and a RAM 242 are connected via an internal bus 250.

The CPU 210 performs an operation based on the data stored in the memory unit 240,
0 and the clock supply control unit 230. CPU2
10 outputs a standby mode signal S1 to the clock supply control unit 230 when an instruction to shift to the standby mode is issued by the memory unit 240. The operation when the standby mode signal S1 is output from the CPU 210 to shift to the standby mode will be described later.

The peripheral circuit 220 includes a serial IO 221 and an AD converter 222. Serial IO221
Is a circuit that communicates with an external circuit using serial data.
The AD converter 222 is a circuit that converts analog data input from the outside into digital data. When the operation of each component configuring the peripheral circuit 220 ends, the peripheral circuit 220 outputs a peripheral operation end signal S2 to the CPU 210 instead of the clock supply control unit 230, unlike the first embodiment. The peripheral circuit 220
The operation when the peripheral operation end signal S2 is output will be described later.

The clock supply control unit 230 controls the external clock C supplied from outside the microcontroller 200.
CPU which is a clock for CPU 210 based on 0
A clock C2 and a peripheral clock C3 for the peripheral circuit 220 are generated. CPU clock C2
Is supplied to the CPU 210, and the peripheral clock C3 is supplied to the peripheral circuits 220 such as the serial IO 221 and the AD converter 222.

The configuration of the clock supply control unit 230 is shown in FIG.
This will be described with reference to FIG. Clock supply control unit 230
Is an external clock control unit 231 that controls an external clock.
And a CPU clock controller 232 and a peripheral clock controller 233 connected to the external clock controller 231.

The external clock control unit 231 controls the external clock C supplied from outside the microcontroller 200.
Based on 0, an internal clock C1 serving as a reference for the clock supply control unit 230 is generated. CPU clock control unit 2
32 generates a CPU clock C2 synchronized with the internal clock C1 supplied from the operation clock generator 231. The peripheral clock controller 233 generates a peripheral clock C3 synchronized with the internal clock C1 supplied from the external clock generator 231.

The operation of the microcontroller 200 configured as described above will be described with reference to the timing chart shown in FIG. The description will be given in chronological order according to the symbols T1 and T2 indicating the time shown in FIG.

The features of this embodiment are as follows. That is, at time T1, when an instruction to shift to the standby mode is issued from the memory unit 240, the CPU 2
10 decodes this instruction and, at the same time,
The point is that it is determined from 0 whether or not the operation end signal S2 is output.

At time T 1, an instruction to shift to the standby mode is issued from the memory 240 to the CPU 21 via the internal bus 250.
0, the CPU 210 decodes this instruction and outputs the standby mode signal S1 to the clock supply control unit 130. At the same time, the operation end signal S
It is determined whether or not 2 has been output.

When the CPU 210 determines that the operation of the peripheral circuit 220 has been completed, the CPU 210 outputs a standby mode signal S 1 to the clock supply control unit 230. Upon receiving the standby mode signal S1, the clock supply control unit 230 stops the internal clock C1, and
2 and the supply of the peripheral clock C3 are stopped, and the entire microcontroller 200 shifts to the standby mode.

On the other hand, if the CPU 210 determines that the operation of the peripheral circuit 220 has not been completed, the CPU 210
Is a NOP (No Operatio) that does not perform arithmetic processing.
n) The instruction is repeated and no operation is performed. At this time, the standby mode signal S1 is supplied to the clock supply control unit 230.
Is not output, the CPU 210 does not perform the arithmetic processing, and the peripheral circuit 220 is in the operating state.

Thereafter, at time T2, when the operation of the peripheral circuit 220 ends, the peripheral circuit 220 outputs a peripheral operation end signal S2 to the CPU 210. The CPU 210 receives the peripheral operation end signal S2 and outputs a standby mode signal S1 to the external clock control unit 230. The external clock control unit 231 stops the internal clock C1, and
When 1 stops, the peripheral clock C3 output from the peripheral clock supply control unit 233 also stops, and the entire microcontroller 200 shifts to the standby mode.

The microcontroller 200 according to the present embodiment is configured and operated as described above, and can exert the following excellent effects. In other words, when the peripheral circuit 120 is operating when shifting to the standby mode, the CPU operates until the operation is completed.
Reference numeral 210 denotes a NOP (No OPera) that does not perform arithmetic processing.
(tion) The instruction is repeated and no operation is performed. Then, at the same time when the operation of the peripheral circuit 220 ends, the entire microcontroller 200 shifts to the standby mode. Therefore, the serial IO 221 and the AD converter 22
The processing data of No. 2 becomes valid.

Further, when shifting to the standby mode, the entire microcontroller 200 can shift to the standby mode without requiring software judgment by a program.

The preferred embodiments of the microcontroller control method and microcontroller according to the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to such examples. It is obvious that those skilled in the art can conceive various changes or modifications within the scope of the technical idea described in the claims.
It is understood that these also belong to the technical scope of the present invention.

For example, in the above-described embodiment, an example has been described in which the transition to the standby mode is performed by an instruction from the CPU, but the present invention is not limited to this. For example, the present invention can be similarly applied to a case where a transition is made to the standby mode by a signal input from outside the microcontroller.

Further, in the above-described embodiment, only the standby mode for reducing power consumption has been described, but the present invention is not limited to this. Even in the low-speed mode in which the power consumption is reduced by operating the CPU and peripheral circuits at a low speed, the operation for switching to the supply of the low-speed clock is performed instead of the operation in which the clock is stopped in the above embodiment. Accordingly, the present invention is also applicable.

[0067]

As described above, according to the present invention,
When the peripheral circuit is operating when shifting to the standby mode, a peripheral clock is supplied until the operation is completed. At the same time as the operation is completed, the entire microcontroller shifts to the standby mode. No need to invalidate processing data.

Further, when shifting to the standby mode, the entire microcontroller can shift to the standby mode without requiring software judgment by a program.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram showing one embodiment of a microcontroller according to the present invention.

FIG. 2 is an explanatory diagram illustrating a configuration of a clock supply control unit of the microcontroller of FIG. 1;

FIG. 3 is a timing chart of the microcontroller of FIG. 1;

FIG. 4 is an explanatory diagram showing another embodiment of the microcontroller according to the present invention.

FIG. 5 is an explanatory diagram illustrating a configuration of a clock supply control unit of the microcontroller in FIG. 4;

FIG. 6 is a timing chart of the microcontroller of FIG. 4;

FIG. 7 is an explanatory view schematically showing a conventional microcontroller.

FIG. 8 is an explanatory diagram illustrating a configuration of a clock supply control unit of the microcontroller of FIG. 7;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 Microcontroller 110 CPU 120 Peripheral circuit 121 Serial IO 122 A / D converter 130 Clock supply control unit 131 External clock control unit 132 CPU clock control unit 133 Peripheral clock control unit 140 Memory unit 141 ROM 142 RAM 150 Internal bus C0 External clock C1 Internal clock C2 CPU clock C3 Peripheral clock S1 Standby mode signal S2 Peripheral operation end signal

Claims (4)

[Claims] 1. An arithmetic processing unit, a peripheral circuit, and a clock supply control unit capable of individually outputting a clock for an arithmetic processing unit for driving the arithmetic processing unit and a clock for a peripheral circuit for driving the peripheral circuit. A control method for a microcontroller, comprising: when a mode change signal to a low power consumption mode is generated, determining whether the peripheral circuit is operating; and in the step, the peripheral circuit is not operating. If it is determined that the peripheral processing circuit is operating in the step, the operation processing clock and the peripheral circuit clock are switched to a low power consumption mode. The internal clock is switched to the low power consumption mode, but the peripheral circuit clock is switched to the low power consumption mode after the operation of the peripheral circuit is completed. And controlling the microcontroller. 2. An arithmetic processing unit, a peripheral circuit, and a clock supply control unit capable of individually outputting an arithmetic processing unit clock for driving the arithmetic processing unit and a peripheral circuit clock for driving the peripheral circuit. A control method for a microcontroller, comprising: when a mode change signal to a low power consumption mode is generated, determining whether the peripheral circuit is operating; and in the step, the peripheral circuit is not operating. If it is determined that the peripheral processing circuit is operating in the step, the operation processing clock and the peripheral circuit clock are switched to a low power consumption mode. The unit stops arithmetic processing, and the operation processing unit clock and the peripheral circuit clock are switched to a low power consumption mode after the operation of the peripheral circuit is completed. And controlling the microcontroller. 3. A microcontroller comprising an arithmetic processing unit driven by a clock for an arithmetic processing unit and a peripheral circuit driven by a clock for a peripheral circuit, wherein the microcontroller generates a mode change signal to a low power consumption mode. A mode change device that performs the operation, a determination device that receives a mode change signal to determine whether the peripheral operation circuit is operating, and a determination device that determines that the peripheral operation circuit is not operating when the determination device determines that the peripheral operation circuit is not operating. The clock for the arithmetic processing unit and the clock for the peripheral circuit are switched to a low power consumption mode, and when the determination unit determines that the peripheral operation circuit is operating, the clock for the arithmetic processing unit is set to low. The clock for the peripheral circuit is switched to the power consumption mode, and the clock for switching to the low power consumption mode after the operation of the peripheral circuit is completed. And a supply controller. 4. A microcontroller comprising an arithmetic processing unit driven by a clock for an arithmetic processing unit and a peripheral circuit driven by a clock for a peripheral circuit, wherein the microcontroller generates a mode change signal to a low power consumption mode. A mode change device that performs the operation, a determination device that receives a mode change signal to determine whether the peripheral operation circuit is operating, and a determination device that determines that the peripheral operation circuit is not operating when the determination device determines that the peripheral operation circuit is not operating. The operation processing unit clock and the peripheral circuit clock are switched to a low power consumption mode, and when the judgment device judges that the peripheral operation circuit is operating, the operation processing unit executes the operation processing. After the operation of the peripheral circuit ends, the clock for switching to the low power consumption mode is stopped. And a lock supply control unit.