JPH04167113A - Information processor - Google Patents

Abstract

PURPOSE:To satisfactorily reduce power consumption of the information processor with simple constitution by stopping the supply of a clock signal to an auxiliary processing means when this means is not used. CONSTITUTION:A data bus 3, an address bus 4 and a control bus 5 aredirectly connected to a CPU 1 serving as a main processing means and a coprocessor 6 serving as an auxiliary processing means respectively. A clock control circuit 15 controls the supply of a clock signal S1 to the coprocessor 6 with a clock control signal S2 supplied from a control port circuit 9. Thus a clock supply control means stops the supply of the clock signal to the coprocessor 6 when this processor 6 is not used. Thus the internal state of the coprocessor 6 is not changed in response to the clock signal. Then power consumption of the information processor is reduced with simple constitution.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information processing device that is equipped with auxiliary processing means (coprocessor, DMAC, etc.) in addition to a main processing means (microprocessor), and particularly relates to an information processing device that has low power consumption. This is what we are trying to achieve.

[Prior Art] Recently, many portable information processing devices such as electronic notebooks, laptop-type personal computers, and laptop-type word processors have been provided. Some of these information processing devices operate not only on a driving power source formed from a commercial power source using a power adapter, but also on battery power, and some operate only on battery power. . Therefore, there is a need for even lower power consumption than other information processing devices.

In addition, high-speed processing is required in information processing devices such as those described above, and therefore, rather than entrusting all processing to a microprocessor (CPU), the negative part of the processing (for example, specific numerical calculation processing) is carried out by a dedicated processor. There are some that are left to a coprocessor (for example, a coprocessor).

Figure 3 shows a conventional information processing threshold 1 that also includes a coprocessor.
This figure mainly shows the configuration for low power consumption.

In FIG. 3, a clock signal is given from a clock oscillator 2 to a CPU that mainly controls processing of the information processing device, and the CPU performs various processing based on an internal clock signal obtained by dividing this clock signal internally. , and, as necessary, sends and receives data to and from the data bus 3, outputs an address to the address bus 4, and outputs a control signal to the control signal line.

As described above, this information processing device includes a coprocessor 6 that executes dedicated processing that is not executed by CP[Jl. An intermittent circuit 7 is inserted between the coprocessor 6 and the system buses 3 to 5, and the intermittent circuit #17 connects or disconnects the coprocessor 6 and the system buses 3 to 5. It is done like this. Naturally,
While connected to the system buses 3 to 5, the coprocessor 6 receives power from the power switching circuit 8 and executes dedicated processing. Note that the coprocessor 6 also executes processing in synchronization with the tarok signal from the clock oscillator 2 provided via the intermittent circuit 7.

Power is constantly supplied to elements other than the coprocessor 6 in FIG. 3, and illustration of the power supply circuit therefor is omitted in FIG.

A control signal for the intermittent circuit 7 is given from a control boat circuit 9. The control boat circuit 9 is connected to the system buses 3 to 5, and is configured to receive commands from the CPU to connect or disconnect the intermittent circuit 7. The control port circuit 9 also controls supply and stop of power from the power switching circuit 8 . Therefore, commands for power control are given from the CPU.

This information processing device further includes a reset circuit 1o. The reset circuit 10 is also configured to output a reset signal to the CPUI and coprocessor 6 in response to a control signal from the control port circuit 9. Therefore, commands for reset control are also given to the control port circuit 9 from the CPUI. The reset circuit i\811 provides a reset signal directly to the CPUI and to the coprocessor 6 via the intermittent circuit 7 to synchronize the CPUI and the coprocessor 6.

In the above configuration, when the coprocessor 6 goes from an unused state where the supply from the power switching circuit B8 is stopped and the intermittent circuit 7 is cut off to a state where processing by the coprocessor 6 is required, the CPU 1 outputs commands to the control boat circuit 9 in the following order.

The CPU first outputs a command for the power switching circuit 8 to start supplying power to the coprocessor 6,
Then, the intermittent circuit 7 connects the coprocessor 6 and the system bus 3.
5, and finally, the reset circuit 10 outputs a command to provide a reset signal to the CPUI and the coprocessor 6 to establish synchronization.

At this stage, the CPUI gives necessary data to the coprocessor 6 to execute the required processing.

When processing by the coprocessor 6 becomes unnecessary, the CPU
I outputs commands to the control boat B9 in the following order.

The CPU first outputs a command to disconnect the intermittent FI@7 from the coprocessor 6 and the system buses 3 to 5, and then the power switching circuit 8 outputs a command to stop the power supply to the coprocessor 6. This means that the impact of a power outage is transmitted to the CPU via system buses 3 to 5.
etc., so that it does not reach the same level.

As described above, the conventional information processing device has a coprocessor 6
Reduces power consumption by directly controlling the power supply to
power save).

“Problems to be Solved by the Invention” However, in the conventional device, high speed is required, and the disconnection circuit 7, which disconnects and connects many signal lines including a bidirectional bus,
Further, since the power supply switching circuit 8 that performs switching operation is required, the overall configuration becomes complicated and large. In addition, the intermittent circuit 7 provided to reduce power consumption has an electrical configuration (for example, a digital switch) rather than a mechanical one in order to achieve high speed, and power is not supplied to the coprocessor 6. It is necessary for power to be supplied even when the device is not in use, and it is not possible to achieve a sufficient reduction in power consumption as a whole. Furthermore, since the power supply to the coprocessor 6 is completely stopped, the CPUI and the coprocessor 6 must be reset together to ensure synchronization when the power is resupplied as described above.
There is a problem that processing by the UI is temporarily interrupted.

The present invention has been made in consideration of the above points, and it is possible to achieve sufficient reduction in power consumption with a simple configuration, and furthermore, the processing of the main processing means can be interrupted to reduce power consumption. The purpose of this invention is to provide an information processing device that does not cause any problems.

[Means for Solving the Problems] In order to solve the problems, in the present invention, in an information processing apparatus equipped with an auxiliary processing means, which may be in an unused state, in addition to a main processing means, the auxiliary processing means may be in an unused state. A clock supply control means is provided which detects that the apparatus is in use and stops supplying the clock signal to the auxiliary processing means.

[Function] According to the present invention, when the auxiliary processing means is not in use, the clock supply control means stops supplying the clock signal to the auxiliary processing means, so that the auxiliary processing means can change its internal state according to the clock signal. We aim to reduce power consumption through a simple configuration.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Here, FIG. 1 is a block diagram showing the configuration of this embodiment, and FIG. 2 is a timing chart of each part thereof. Note that in FIG. 1, parts corresponding to those in FIG. 3 are given the same reference numerals.

In FIG. 1, in this embodiment, a data bus 3 is a system bus connected to a CPU which is a main processing means.
, address bus 4, and control bus 5, a coprocessor 6 serving as auxiliary processing means is directly connected.

The clock oscillator 2 is connected to the CPUI and a clock control circuit 15 which is a clock supply control means, and
The clock signal S1 is directly supplied to the UI, and the clock signal S1 is supplied to the coprocessor 6 by the clock control circuit 15.
Give through. When a clock control signal S2 given from a control boat circuit 9 (to be described later) instructs passage, the tarock control circuit 15 outputs a signal to the clock oscillator 2.
The clock signal S1 from the clock signal S1 is passed through and applied to the coprocessor 6, and the supply of the clock signal S1 to the coprocessor 6 is stopped when the clock control signal S2 instructs to block the passage. Therefore, the clock signal S to the coprocessor 6
3 is interrupted.

Reset #! 10 is connected to the CPUI and reset control circuit 16, and provides a reset signal S4 to these. The reset control circuit 16 is further supplied with a clock signal S1 from the clock oscillator 2 and a clock control signal S2 from the control boat circuit 9. When the clock control signal S1 instructs to pass through the clock control circuit 15, the reset control circuit 16 applies the reset signal S4 applied during that time to the coprocessor 6 as is. Further, when the reset control circuit 16 detects a transition from a state where the clock control signal S2 instructs the clock control circuit 15 to stop passing to a state where the clock control signal S2 instructs the clock control circuit 15 to pass,
A reset signal S5 of a predetermined time synchronized with the clock signal S1 is generated and provided to the coprocessor 6.

The control boat circuit 9 of this embodiment outputs the above-mentioned clock control signal S2 in accordance with a CPU command. In addition, the control boat circuit 9 is
It forms a chip select signal S6 for the lever processor 6 in accordance with a command from the CPUI. The coprocessor 6 connects to the system buses 3 to 5 when the chip select signal S6 is in the selected state, and sets the input/output terminals to high impedance and connects to the system buses 3 to 5 when the chip select signal S6 is in the non-selected state. This disconnects the connection.

Next, the operation of the information processing device having the above configuration will be explained in the second section.
This will be explained with reference to the figures.

The CPU frequency divides the clock signal S1 shown in FIG. 2(A) from the clock oscillator 2 to form an internal clock signal S7 shown in FIG. 2(B), and this internal clock signal S7
Perform various processing based on the .

When the CPU 1 is executing processing by the coprocessor 6, the CPU 1 receives an active chip select signal S6 from the control boat circuit 9 (the one shown is logic "H").
(Figure 2 (C)) is output. When this state becomes such that processing by the coprocessor 6 is no longer necessary, the CPU
I gives a predetermined command to the control boat circuit 9 to make the chip select signal S6 inactive (
Time tl>. At this time, the coprocessor 6 performs a process of disconnecting from the system buses 3-5.

At time t2, when a predetermined period of time has elapsed from time t1 at which the command to make the chip select signal S6 inactive was output, the CPLII gives a command to the control boat circuit 9 to output the clock control signal S shown in FIG.
2 is activated (the one shown is logic "H").

As a result, the clock control circuit 15 receives the clock signal S1.
, and the supply of the tarock signal S3 to the clock input terminal of the coprocessor 6 is stopped (see FIG. 2(E)).
reference).

Therefore, in this clock stopped state, the coprocessor 6 does not change its internal state, reducing power consumption.

When the CPU 6 uses the coprocessor 6 again, it first gives a predetermined command to the control boat circuit 9 to make the clock control signal S2 inactive (at time t3).
). As a result, the coprocessor 6 receives the clock signal S3.
is supplied again (see FIG. 2(E)). Further, a reset signal S5 shown in FIG. 2(F), which is in the active state for a predetermined time period from time t3 (t3 to t4>active), is generated by the reset control port 816 and supplied to the coprocessor 6.

When the supply of the clock signal S3 (Sl) is resumed, it takes some time for the clock signal S3 given to the coprocessor 6 to become stable due to transient characteristics, etc. If the coprocessor 6 is operated in this unstable state, Also, synchronization with the CPUI cannot be established.

Therefore, give the reset signal S5 and wait until the clock signal S3 becomes stable and the inside of the coprocessor 6 is synchronized with the CPUI. Also, by resetting the coprocessor 6, the processing that was being performed immediately before this restart does not affect the processing due to this restart.

After outputting a predetermined command to make the clock control signal S2 inactive, the CPUI outputs a predetermined command to the control boat circuit 9 at time t5, after a period longer than the period in which the reset signal S5 is active, to output a chip select signal. Activate S6. Thereby, the coprocessor 6 is connected to the system buses 3 to 5. In this way, processing by the coprocessor 6 becomes possible.

Therefore, according to the above-described embodiment, an intermittent circuit and a dedicated power switching circuit for the coprocessor 6 are not required in order to reduce power consumption, so the overall configuration can be simplified. Furthermore, since power consumption is reduced by stopping the supply of the clock signal S3 to the coprocessor 6, time #1 (
15, 16) consumes only a small amount of power during the period of low power consumption, and can achieve a sufficient reduction in power consumption. Furthermore, when using the coprocessor 6 again,
No reset is required to the CPUI, so the C
PUI processing is never interrupted.

Note that although the present invention is particularly effective for devices that operate on battery power, it can also be applied to devices that operate on a drive power source generated from a commercial power source.

Further, the auxiliary processing means is not limited to a coprocessor, but may be another device such as a DMAC.

The information processing device to which the present invention is applied includes a main processing means (CPU
) in addition to auxiliary processing means, and includes so-called home appliances if they are equipped with these means.

[Effects of the Invention] As described above, according to the present invention, since the supply of clock signals to the auxiliary processing means is stopped when the auxiliary processing means is not used, sufficient power consumption can be reduced with a simple configuration. Accordingly, it is possible to realize an information processing device that can measure the amount of time required for processing the data without interrupting the operation of the main processing means.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of an information processing apparatus according to the present invention, FIG. 2 is a timing chart of each part thereof, and FIG.
The figure is a block diagram showing a conventional device. DESCRIPTION OF SYMBOLS 1... CPU (main processing means), 2... Clock oscillator, 3-5... System bus, 6... Coprocessor (auxiliary processing means), 9... Control boat circuit,
15... Clock control circuit (clock supply control means)
, 16... Reset control circuit.

Claims (1)

[Claims] In an information processing device that includes, in addition to a main processing means, an auxiliary processing means that may be in an unused state, detecting that the auxiliary processing means is in an unused state and supplying a clock signal to the auxiliary processing means. An information processing device characterized by comprising a clock supply control means for stopping the clock supply.