JP2007079904A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which dispenses with preparation of pins for setting magnification etc., and which dispenses with supply of external reset signal at the time of changing of magnification etc. <P>SOLUTION: A semiconductor integrated circuit 10 is provided with a clock generator 11 which is necessary to reset when the kind of generating internal clock is re-specified, while being able to specify the kind of generating internal clock to generate internal clock supplying to various internal circuits from external clock, and a reset signal generating circuit 12 and a setting circuit 13 which can execute processing which specifies the kind of generating internal clock to the clock generator 11 and processing which resets clock generator 11, based on commands from a CPU. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit including a clock generator capable of designating operation content (such as a multiplication rate).

  Some semiconductor integrated circuits used in computers, printers, etc. have clock generators that can specify the operation content (multiplication rate and frequency modulation rate can be specified / set to generate an internal clock from an external clock) There is something with a circuit.

  As schematically shown in FIG. 5, such an existing semiconductor integrated circuit 20 has a circuit (for example, a non-terminal) provided with pins (terminals) for designating the multiplication factor and frequency modulation rate of the clock generator 21. (See Patent Document 1). Further, the existing semiconductor integrated circuit 20 is also a circuit that must be reset (an external reset signal must be asserted for a predetermined time) when changing the multiplication rate or the frequency modulation rate.

  In other words, the circuit configuration of the existing semiconductor integrated circuit 20 requires a pin for setting a multiplication rate and the like, and it is difficult to change the multiplication rate by software (an external reset signal is supplied when the multiplication rate is changed) Need to be).

μPD77111 Family User's Manual Internet <URL: http://www.necel.com/nesdis/image/U14623EJ3V0UM00.pdf>

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit that does not need to prepare a pin for setting a multiplication rate and the like and does not need to supply an external reset signal when changing the multiplication rate. .

  In order to solve the above-described problems, in the present invention, a semiconductor integrated circuit that is connected to a CPU is used to generate various internal circuits and an internal clock supplied to the various internal circuits from an external clock. The type of internal clock to be generated can be specified, a clock generator that must be reset when the type of internal clock to be generated is specified again, and a process for specifying the type of internal clock to be generated to the clock generator The process of resetting the clock generator is configured to include a reboot control circuit that is executed based on a command from the CPU.

  That is, the semiconductor integrated circuit of the present invention has a reboot control circuit that changes the operation content of the clock generator in accordance with a command from the CPU. Therefore, the semiconductor integrated circuit of the present invention does not need to prepare a pin for setting a multiplication rate (a pin for designating the type of internal clock to be generated) and supplies an external reset signal when the multiplication rate is changed. It will function as a circuit that does not need to be.

  In realizing the semiconductor integrated circuit of the present invention, in order for the CPU to grasp the operating state of the semiconductor integrated circuit (clock generator), the reboot control circuit is rebooted to indicate whether or not the own circuit has already functioned. It is desirable to use a circuit having a register accessible by the CPU for storing the flag.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  As schematically shown in FIG. 1, a semiconductor integrated circuit 10 according to an embodiment of the present invention includes several (one in the figure) performing various processes for the original purpose of the semiconductor integrated circuit 10. This is a circuit (so-called ASIC) including an internal circuit, a clock generator 11, a reset signal generation circuit 12, and a setting circuit 13. The semiconductor integrated circuit 10 is a circuit that is used by being connected to a CPU.

  The clock generator 11 provided in the semiconductor integrated circuit 10 is the same circuit as the clock generator 21 in the semiconductor integrated circuit 20 of FIG. That is, the clock generator 11 is a circuit that can specify a multiplication rate and a frequency modulation rate, and also needs to input a reset signal when redesignating the multiplication rate / frequency modulation rate. In the semiconductor integrated circuit 10 according to the present embodiment, three types of signals (external reset signal, signal for specifying a multiplication factor, and signal for specifying a frequency modulation factor) input from the outside to the clock generator 21 are The circuit is configured to be input from the reset signal generation circuit 12 to the clock generator 11.

  The reset signal generation circuit 12 and the setting circuit 13 are provided in the semiconductor integrated circuit 10 so that the operation content (multiplication rate, frequency modulation rate) of the clock generator 11 can be changed by a command from the CPU. (A circuit corresponding to the reboot control circuit of the present invention).

  As illustrated, the reset signal generation circuit 12 is a circuit including an SSCG [Spread Spectrum Clock Generator] setting reflection register, a multiplication factor setting reflection register, a reboot circuit, an AND gate, a reset counter, and the like. As is clear from the figure, the reset signal generation circuit 12 has a function of outputting an external reset signal as it is as Reset1x and a function of outputting Reset1x for resetting each internal circuit.

  The setting circuit 13 is a circuit including an SSCG setting register, a multiplication rate setting register, a reboot flag register, a reboot execution flag register, and the like. The setting circuit 13 is a circuit that allows the CPU to access each register in the setting circuit 13.

  Hereinafter, the configurations and operations of the reset signal generation circuit 12 and the setting circuit 13 will be described more specifically with reference to FIGS. Of these drawings, FIG. 2 is a configuration diagram showing the connection between the parts of the semiconductor integrated circuit 10 more clearly. This configuration diagram shows only one setting register (SSCG setting register, multiplication rate setting register) and one setting reflection register (SSCG setting reflection register, multiplication rate setting reflection register).

  The SSCG setting register and the multiplication rate setting register (see FIGS. 1 and 2) in the setting circuit 13 are set by the CPU with information for specifying the frequency modulation rate and information for specifying the multiplication rate, respectively. Register. The reboot execution flag register is a register in which a predetermined value is set by the CPU when it is necessary to cause the clock generator 11 to start an operation having contents corresponding to information set in each setting register. Hereinafter, information stored in the reboot execution flag register is referred to as a reboot execution flag, and the predetermined value is referred to as “ON”. A signal that can be output from the reboot execution flag register (a signal indicating the value of the reboot execution flag; see FIG. 2) is referred to as a reboot execution signal.

  The reboot flag register is a register provided in the semiconductor integrated circuit 10 so that a reboot flag indicating whether or not a reboot has been performed can be stored. The reboot flag register is a register that is reset by an external reset signal, as shown in FIG. Also,

  The SSCG setting reflection register and the multiplication factor setting reflection register in the reset signal generation circuit 12 are respectively set to the SSCG setting register and the multiplication factor when the reboot is executed (when the reboot execution flag is set to “ON”; details will be described later). This is a register in which information set in the register is read. In addition, the SSCG setting reflection register and the multiplication rate setting reflection register are also registers in which the clock generator 11 to which the reset signal is input starts the operation according to the information stored therein. Furthermore, each setting reflection register is a register that is reset by an external reset signal (not reset by Reset1x).

  As shown in FIG. 2, the reboot circuit is a circuit to which a reboot execution signal from the reboot execution flag register is input via two FFs. Two FFs are provided because the clock (external clock) used by the reboot circuit is different from the clock (internal clock generated by the clock generator 11) used by the reboot execution flag register (in an asynchronous relationship). This is because it is a certain clock).

  This reboot circuit is composed of a counter or the like that counts an external clock and can take an idle state, a setting wait state, and a reboot execution state. Here, the idle state is a state in which the reboot execution signal is being asserted (the signal from the FF goes high). The setting wait state is a state waiting for the value of the setting register to be taken into the setting reflection register (a state waiting for the elapse of one clock time), and the reboot execution state is This is a state where a signal to the AND gate is asserted for a certain period of time (a state where Reset1 is asserted for a certain period of time).

  Then, as shown in FIG. 3, when the reboot execution signal is asserted (the signal from the FF becomes high level), the reboot circuit shifts to the setting wait state and then enters the reboot execution state. It is a circuit to be transferred.

  As is clear from the above description, when the reboot execution flag is turned ON by the CPU, the semiconductor integrated circuit 10 according to the present embodiment receives the value of each setting register in the setting reflection register, and then the clock generator 11 is reset (Reset1 is asserted for a certain period of time) (ie, it is not necessary to prepare a pin for setting the multiplication rate, etc., and it is not necessary to supply an external reset signal when changing the multiplication rate) It has become.

  The semiconductor integrated circuit 10 is provided with a reboot flag register capable of storing a reboot flag indicating whether or not a reboot has been performed. Therefore, as illustrated in FIG. 4, the semiconductor integrated circuit 10 is a circuit that allows the CPU to change the processing contents depending on whether or not the reboot flag is “ON”.

  Therefore, if this semiconductor integrated circuit 10 is used, an information processing apparatus capable of controlling the frequency of the internal clock by software can be manufactured at low cost.

1 is a configuration diagram of a semiconductor integrated circuit according to an embodiment. FIG. 1 is a main part configuration diagram of a semiconductor integrated circuit according to an embodiment. FIG. 5 is a timing chart for explaining a function of a reboot circuit provided in the semiconductor integrated circuit according to the embodiment. The flowchart for demonstrating the use of a reboot flag register. The block diagram of the conventional semiconductor integrated circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10,20 Semiconductor integrated circuit, 11, 21 Clock generator 12 Reset signal generation circuit, 13 Setting circuit

Claims (2)

A semiconductor integrated circuit used in connection with a CPU,
Various internal circuits,
A clock generator for generating an internal clock to be supplied to the various internal circuits from an external clock, the type of the internal clock to be generated being specified, and a reset required when re-specifying the type of the internal clock to be generated When,
And a reboot control circuit for executing a process for designating a type of an internal clock to be generated for the clock generator and a process for resetting the clock generator based on a command from the CPU. Integrated circuit. 2. The semiconductor according to claim 1, wherein the reboot control circuit is a circuit having a register accessible by the CPU for storing a reboot flag indicating whether or not the own circuit has already functioned. Integrated circuit.