JPH11143574A - Clock generation circuit and clock generation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce noise generated in a microcomputer having plural oscillator circuits and to reduce power consumption. SOLUTION: This circuit is provided with a 1st oscillator circuit 1 which generates a low frequency clock signal, a 1st frequency dividing circuit 3 that divides the output, a 2nd oscillator circuit 2 which generates a high frequency clock signal, a 2nd frequency dividing circuit 2 which divides the output and a selection circuit 9 which selects the output of the circuit 3 and the output of the circuit 4. When a system is off, the circuit 1 is operated, also the circuit 2 is stopped and the circuit 9 selects the output of the circuit 3. When the system is on, the circuit 1 is stopped, also the circuit 2 is operated to supply a harmonic clock signal to the system and further the output of the circuit 4 is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a clock generation circuit and a clock generation method for a microcomputer having a plurality of oscillation circuits.

[0002]

2. Description of the Related Art In a system incorporating a conventional microcomputer, such as a video deck, power is supplied to the microcomputer even when the system is turned off. However, when the microcomputer operates in this state, the power consumption increases. Therefore, as shown in FIG. 6, two oscillation circuits are prepared, and the first oscillation circuit 17 is assigned to some functions such as a clock function. , Assigning the second oscillation circuit 18 to most other functions,
When the system power is off, the second
The oscillation circuit 18 is stopped, and functions other than some functions such as a clock function are stopped to reduce power consumption during standby. One example of such a conventional method is
It is described in JP-A-59-195726.

[0003]

However, the above-mentioned prior art has a problem that noise is large during a normal operation in which the power supply of the system is turned on. This is because when the system power is on, two high-frequency and low-frequency oscillating circuits are operating, and since these oscillating circuits are composed of high-speed analog circuits, they are noise sources even in microcomputers. That's why.

[0004] In addition, at the time of normal operation in which the power supply of the system is turned on, there is a problem that power consumption is increased because two oscillation circuits are operating.

An object of the present invention is to reduce the noise generated by a microcomputer,
An object of the present invention is to provide a clock generation circuit capable of reducing power consumption of a microcomputer.

[0006]

According to the present invention, there is provided a first oscillation circuit for generating a low frequency clock signal, a first frequency dividing circuit for dividing the output of the first oscillation circuit and outputting a low frequency clock signal. A second oscillator circuit for generating a high-frequency clock signal;
A second frequency divider for dividing the output of the second oscillator to output a low frequency clock signal having the same frequency as the first frequency divider; an output of the first frequency divider and an output of the second frequency divider 4 When the system is off, the first oscillating circuit is operated and the second oscillating circuit is stopped, the output of the first frequency dividing circuit is selected by the selecting circuit, and the low frequency clock is supplied to the system. A signal is supplied, and when the system is on, the first oscillation circuit is stopped and the second oscillation circuit is operated to supply a high-frequency clock signal to the system, and the output of the second frequency divider circuit is selected by the selection circuit. And supplying a low-frequency clock signal to the system.

According to the present invention, when the second oscillation circuit is operating, the second frequency divider operates, and a signal having the same frequency as the signal generated by the first oscillation circuit and the first frequency divider can be generated. I did it. Thus, when the power of the system is on, the first oscillation circuit can be stopped, so that generation of noise can be suppressed. Conversely, when the power of the system is off, the second oscillation circuit stops, and the operation of the microcomputer stops. In this state, only a specific function can be operated by the first oscillation circuit and the first frequency dividing circuit.

[0008]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a clock generation circuit according to the present invention. The clock generation circuit shown in FIG. 1 includes a first oscillation circuit 1 for generating a low-frequency clock.
A second oscillation circuit 2 for generating a high frequency clock;
A first frequency dividing circuit 3 for dividing the output of the transmitting circuit 1, a second frequency dividing circuit 4 for dividing the output of the second transmitting circuit 2, an output of the first frequency dividing circuit 3 and a second frequency dividing circuit 4 includes a selection circuit 5 for selecting the output of the inverter 4 and an inverter 6.

When the selection signal 9 is 0, that is, when the output of the inverter 6 is 1, the first frequency dividing circuit 3 does not perform the frequency division operation, and when the selection signal 9 changes from 0 to 1, that is, the inverter 6 Starts the frequency division operation when the output of the counter changes from 1 to 0. The second frequency dividing circuit 4 does not perform the frequency dividing operation when the selection signal 9 is 1, and starts the frequency dividing operation when the selection signal 9 changes from 1 to 0. The first oscillation circuit 1 stops oscillation when the first oscillation stop signal 10 is 0, and the second oscillation circuit 2 stops oscillation when the second oscillation stop signal 11 is 0. When the selection signal 9 is 1, the selection circuit 5
The output of the frequency divider 3 is selected, and when the selection signal 9 is 0, the output of the second frequency divider 4 is selected.

Here, the first oscillation circuit 1 is an oscillation circuit for operating a specific function (for example, a clock) at the time of standby when the system power supply is off, and the second oscillation circuit 2 is used for operating the system. An oscillation circuit for operating other functions during a normal operation when the power is on.

Next, the operation of the embodiment shown in FIG.
This will be described with reference to FIGS. FIG. 2 is a flowchart for controlling the clock generation circuit shown in FIG. 1, FIG. 3 is a time chart showing waveforms of various parts in FIG. 1 when the system is powered on, and FIG. 3 is a time chart showing waveforms of the respective parts in FIG. 1 when turned off.

First, the operation when the power of the system is turned on will be described. When the system powers on,
A reset is input to the microcomputer. With this reset input, the first oscillation stop signal 10 and the second oscillation stop signal 11 become 1, and the first oscillation circuit 3 and the second oscillation circuit 4 start operating. At this time, since the selection signal 9 is 1, the first clock signal 7 has the first frequency divider 3
Output is selected.

Thereafter, the microcomputer starts operating according to the built-in program shown in FIG. At the beginning of this program, the initial setting of the first frequency dividing circuit 3 and the second frequency dividing circuit 4 (setting the frequency dividing ratio and setting so that signals of the same frequency are output from the outputs of the two frequency dividing circuits) is performed. Then, the selection signal 9 is set to 0 in synchronization with the fall of the first clock signal 7. Thus, the first clock signal 7 is
The output of the first frequency divider 3 is switched to the output of the second frequency divider 4 by the selection circuit 5.

Thereafter, the first oscillation stop signal 10 is set to 0, and the first oscillation circuit 1 is stopped.

Next, the operation when the power of the system is turned off will be described. When it is detected that the power of the system is off, the first oscillation stop signal 10 is set to 1 and the first oscillation circuit 1
Start operation. When the selection signal 9 is set to 1 after the operation of the first oscillation circuit 1 is stabilized, the first clock signal 7 is output from the output of the second frequency division circuit 4 by the selection circuit 5 to the first frequency division circuit 3. Switch to the output of

Thereafter, the second oscillation stop signal 11 is set to 0, and the second oscillation circuit 2 is stopped. When the second oscillation circuit 2 stops, the second clock signal 8 stops, so that all other functions stop.

Next, another embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram showing another embodiment of the present invention.

Referring to FIG. 5, the result of selecting the output of the first frequency divider 14 and the output of the first oscillator 12 by the selector 16 is connected to the second frequency divider 15. In a normal use of a microcomputer, the frequency output from the second oscillation circuit is higher than the frequency output from the first oscillation circuit. Therefore, in the configuration of FIG. 1, unless the frequency division ratio of the second frequency divider is increased, the same frequency as the output of the first frequency divider cannot be output, and the circuit scale of the second frequency divider increases. There is. In this embodiment, the output of the first frequency divider 14 is connected to the second frequency divider 15 and the second frequency divider 15 is shared, thereby reducing the frequency division ratio of the first frequency divider 14. ing.

This embodiment has a new effect that the number of bits of the counter provided in the clock generation circuit can be reduced.

[0021]

As described above, according to the present invention, although two oscillation circuits may operate temporarily at the same time, since only one of the oscillation circuits generally operates, noise generated by the microcomputer is reduced. Can be reduced. This effect also depends on the ratio between the frequencies of the two oscillation circuits. When the frequency of the first oscillation circuit is 1/10 of the frequency of the second oscillation circuit, noise of 2% to 5% can be reduced. .

Further, according to the present invention, since only one of the oscillation circuits is operated, the power consumption of the microcomputer can be reduced. The power consumption can be reduced by 2% to 5% compared to when the two oscillation circuits are operating.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a clock generation circuit of the present invention.

FIG. 2 is a flowchart for controlling the clock generation circuit of the present invention.

FIG. 3 is a time chart showing waveforms of respective units when the power of the system is turned on.

FIG. 4 is a time chart showing waveforms of respective units when the power of the system is turned off.

FIG. 5 is a block diagram showing another embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional clock generation circuit.

[Explanation of symbols]

 1,12,17 First oscillation circuit 2,13,18 Second oscillation circuit 3,14 First frequency divider 4,15 Second frequency divider 5,16 Selection circuit 6 Inverter 7 First clock signal 8 Second clock Signal 9 Selection signal 10 First oscillation stop signal 11 Second oscillation stop signal

Claims (7)

[Claims] A first oscillation circuit for generating a low frequency clock signal; a second oscillation circuit for generating a high frequency clock signal;
Means for determining whether the system power is on or off,
When the system is off, the first oscillation circuit is operated and the second oscillation circuit is stopped to supply a low-frequency clock signal to the system. When the system is on,
The first oscillation circuit is stopped and the second oscillation circuit is operated to supply a high frequency clock signal to the system, and further divide the high frequency clock signal to supply a low frequency clock signal to the system. Clock generation circuit. A first oscillation circuit for generating a low-frequency clock signal; a first frequency-dividing circuit for dividing the output of the first oscillation circuit to output a low-frequency clock signal; A second oscillation circuit, a second frequency divider for dividing the output of the second oscillation circuit and outputting a low frequency clock signal having the same frequency as the first frequency divider, and an output of the first frequency divider and A selecting circuit for selecting an output of the second frequency dividing circuit, wherein when the system is off, the first oscillating circuit is operated and the second oscillating circuit is stopped; To provide a low-frequency clock signal to the system and when the system is on,
The high frequency clock signal is supplied to the system by stopping the first oscillation circuit and operating the second oscillation circuit, and further selecting the output of the second frequency dividing circuit by the selection circuit to supply the low frequency clock signal to the system. And a clock generation circuit. 3. A first oscillation circuit for generating a low-frequency clock signal, a second oscillation circuit for generating a high-frequency clock signal, and a low frequency output from the first oscillation circuit by dividing the output of the second oscillation circuit. A first frequency divider for outputting a low frequency clock signal having the same frequency as the frequency clock signal; a selector for selecting an output of the first oscillator and an output of the first frequency divider; And a second frequency dividing circuit for outputting a low frequency clock signal to the system when the system is off. When the system is off, the first oscillating circuit is operated and the second oscillating circuit is stopped. When the output of the first oscillation circuit is selected, when the system is on, the first oscillation circuit is stopped and the second oscillation circuit is operated to supply a high-frequency clock signal to the system. Clock generation circuit and selects the output of the second frequency divider Ri. 4. When the system is off, a first oscillation circuit for generating a low frequency clock signal is operated, and a second oscillation circuit for generating a high frequency clock signal is stopped to supply a low frequency clock signal to the system. When the system is on, the first oscillation circuit is stopped,
A clock generation method, comprising: operating the second oscillation circuit to supply a high-frequency clock signal to a system; and further dividing the high-frequency clock signal to supply a low-frequency clock signal to the system. 5. When a system is off, a first oscillation circuit for generating a low frequency clock signal is operated, and a second oscillation circuit for generating a high frequency clock signal is stopped to supply a low frequency clock signal to the system. When the system is on, the first oscillation circuit is stopped,
A high-frequency clock signal is supplied to the system by operating the second oscillation circuit, and a frequency divider circuit divides the high-frequency clock signal to supply a clock signal having the same frequency as the low-frequency clock signal to the system. Clock generation method. 6. A microcomputer having a low frequency oscillating circuit for generating a low frequency clock signal and a high frequency oscillating circuit for generating a high frequency clock signal, wherein the microcomputer operates the low frequency oscillating circuit when the microcomputer is on standby. Stop the oscillation circuit,
A microcomputer which stops the low-frequency oscillation circuit and operates the high-frequency oscillation circuit during normal operation of the microcomputer. 7. A microcomputer having a low-frequency oscillation circuit for generating a low-frequency clock signal and a high-frequency oscillation circuit for generating a high-frequency clock signal, wherein the microcomputer operates the low-frequency oscillation circuit when the microcomputer is on standby. Stop the oscillation circuit,
During normal operation of the microcomputer, the low-frequency oscillation circuit is stopped, and the high-frequency oscillation circuit is operated. Further, a clock signal output from the high-frequency oscillation circuit is divided by the frequency dividing circuit to the same frequency as the low-frequency oscillation circuit. A microcomputer characterized by the above-mentioned.