JP2002091608A - Device for supplying clock and method for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock supplying device and method capable of performing a high speed operation by supplying a clock without waiting for the oscillation stabilization of a clock multiplying PLL even just after a power is supplied, and reducing power consumption by stopping the operation of the clock multiplying PLL in a power saving mode. SOLUTION: This clock supplying device A is provided with a reference clock inputting means 101, an outside reset inputting means 102, a clock supplying PLL 103, a control circuit 104, a frequency-dividing circuit 105, a first selector 106, a second selector 107, and a third selector 108, and connected to a microcomputer 10, a first functioning block 11, and a second functioning block 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a clock supply device and a clock supply method for realizing low power consumption in a system LSI built in a microcomputer operating at high speed.

[0002]

2. Description of the Related Art Conventionally, a clock supply device for supplying a clock to a system LSI built in a microcomputer that requires high-speed operation is a clock multiplication device that multiplies the frequency of a reference clock input from the outside to a predetermined multiple. It is configured to output a high-speed multiplied clock by a PLL (phase locked loop) (generally 100 MHz
z or more. ), The multiplied clock obtained in this way is used as the operation clock of the system LSI. On the other hand, when operating the system LSI with reduced power consumption, that is, when operating in the power saving mode, the clock supply device divides the multiplied clock and supplies the divided clock with the reduced frequency as the operation clock. In addition, the supply of the operation clock to the blocks that do not operate in the power saving mode among the operation blocks connected to the system LSI is configured to be stopped.

Here, a clock supply device in a conventional system LSI will be described with reference to FIGS. As shown in FIG. 3, a conventional clock supply device X
Comprises a reference clock input means 301, an external reset input means 302, a clock multiplying PLL 303, a control circuit 304, a frequency dividing circuit 305, a first selector 306, a second selector 307, and a third selector 308. ing. The clock supply device X is an operation block, a microcomputer 10 and a first function block 1.
1 and the second functional block 12.

The clock multiplying PLL 303 receives the reference clock a, multiplies the frequency of the input reference clock a by a predetermined multiple, and outputs the multiplied clock c.
The control circuit 304 receives the reference clock a, the external reset signal b, and the power saving mode signal m, and outputs a clock control signal h, a frequency division reset signal d, and a system reset signal l. The frequency dividing circuit 305 outputs the multiplied clock c
Is input, and the input multiplied clock c is set to a predetermined frequency division number, for example, divide-by-2, divide-by-4, and divide-by-8, so that the first divided clock e, the second divided clock f, and the third divided clock are respectively obtained. Output as clock g.

[0005] The first selector 306 includes a first frequency-divided clock e, a second frequency-divided clock f, a third frequency-divided clock g,
The clock control signal h is input, and the first frequency-divided clock e and the second frequency-divided clock f are determined based on the value of the clock control signal h.
And the third divided clock g, the necessary divided clock is selected, and this is output to the microcomputer 10 as the first system clock i. The output of the first system clock i is stopped depending on the value of the clock control signal h.

The second selector 307 includes a first divided clock e, a second divided clock f, a third divided clock g,
The clock control signal h is input, and the first frequency-divided clock e and the second frequency-divided clock f are determined based on the value of the clock control signal h.
And the third divided clock g, the necessary divided clock is selected, and the selected divided clock is output to the first functional block 11 as the second system clock j. The output of the second system clock j is stopped depending on the value of the clock control signal h.

The third selector 308 includes a first divided clock e, a second divided clock f, a third divided clock g,
The clock control signal h is input, and the first frequency-divided clock e and the second frequency-divided clock f are determined based on the value of the clock control signal h.
And the third divided clock g, the necessary divided clock is selected, and the selected divided clock is output to the second functional block 12 as the third system clock k. The output of the third system clock k is stopped depending on the value of the clock control signal h.

[0008] The clock supply device X thus configured
Will be described with reference to FIG. First, when the power is turned on (FIG. 4.X), the external reset signal b is in a reset state, but thereafter changes to a reset release state. When the power is turned on, the clock multiplication PL
L303 receives the reference clock a and outputs a multiplied clock c whose frequency has been multiplied by a predetermined multiple of the reference clock a. At this time, the clock multiplying PLL 303 cannot supply the stable multiplied clock c because the pull-in period until the predetermined time elapses after the power is turned on and the operation is started. , The supply of the stable multiplied clock c is started. That is, the multiplied clock c in this period is in a retracted state for a while after the power is turned on, but is in a stable oscillation state after a predetermined time has elapsed.

After the external reset signal b changes from the reset state to the reset release state, the control circuit 304 counts the reference clock a for at least the time corresponding to the pull-in period of the clock multiplying PLL 303, and the pull-in period ends. Later, that is, when the multiplied clock c changes from the pulled-in state to the stable oscillation state, the frequency-divided reset signal d is changed from the reset state to the reset release state and output.

Next, the frequency dividing circuit 305 receives the frequency-multiplied clock c and the frequency-divided reset signal d, and after the frequency-divided reset signal d enters the reset release state, divides the frequency-multiplied clock c into the respective frequency division ratios. Then, they are output as a first divided clock e, a second divided clock f, and a third divided clock g, respectively.

After the first divided clock e, the second divided clock f, and the third divided clock g are in the output state, the clock control signal h changes from the stop state to the normal operation state.

When the clock control signal h is stopped, the first
The first system clock i output from the selector 306, the second system clock j output from the second selector 307, and the third system clock k output from the third selector 308 are in a stopped state.

When the clock control signal h changes from the halt state to the normal operation state, the first selector 306 selects, for example, the first frequency-divided clock e and outputs it as the first system clock i. Similarly, the second frequency-divided clock f is selected from the second selector 307, and the third frequency is selected from the third selector 308 as the second system clock j.
The divided clock g is selected and output as the third system clock k.

When the first system clock i, the second system clock j, and the third system clock k enter the normal operation state and start supplying clocks, the control circuit 304 outputs the system reset signal 1 which has been in the reset state. Output in reset release state. Microcomputer 10, first functional block 11, second functional block 12
Then, when the system reset signal 1 is inputted, the respective operations are started.

Next, as described above, the microcomputer 10, the first functional block 11, and the second functional block 12
Starts operating, the system LSI operates in the power saving mode, that is, when the power saving mode signal m changes from the normal operation state to the power saving mode state (FIG. 4.Y),
The operation of the clock supply device X will be described.

When the power saving mode signal m changes from the normal operation state to the power saving mode state, the clock control signal h output from the control circuit 304 also changes from the normal operation state to the power saving mode simultaneously with the change of the power saving mode signal m. Change to a state.

Here, the first selector 306, the second selector 307, and the third selector 308 supply the clock control signal h
Changes from the normal operation state to the power saving mode state, for example, the third selector 308 stops supplying the third system clock k, the second selector 307 stops supplying the second system clock j, and the first selector 307 stops supplying the second system clock j. 306 outputs the third divided clock g as the first system clock i. As a result, the operation speed of the microcomputer 10 is reduced to 1/8, the first function block 11 and the second function block 12 are in an operation stop state, and a power saving mode in which power consumption is reduced is set. Here, by stopping the supply of the third system clock k and the supply of the second system clock j, the operations of the first function block 11 and the second function block 12 are stopped, and the power saving mode is set. However, by stopping the supply of the first system clock i and the supply of the second system clock j,
The operation of the microcomputer 10 and the operation of the first functional block 11 may be stopped to realize the power saving mode. Further, by stopping the supply of the first system clock i and the supply of the third system clock k, the operations of the microcomputer 10 and the second function block 12 are stopped, and the power saving mode is realized. You may.

Thereafter, when the power saving mode signal m changes from the power saving mode state to the normal operation state (FIG. 4.
To explain Z), first, the clock control signal h output from the control circuit 304 changes the power saving mode signal m from the power saving mode state to the normal operation state at the same time as the power saving mode signal m changes from the power saving mode state to the normal operation state. Change.

First selector 306, second selector 30
7. After the clock control signal h changes from the power saving mode state to the normal operation state, the third selector 308 sets the first frequency-divided clock e as the first system clock i, and sets the second selector 307 Second divided clock f
As the second system clock j, the third selector 308
The microcomputer 10, the first function block 11, and the second function block 12 return to the normal operation state by outputting the third divided clock g as the third system clock k, respectively.

[0020]

However, in the conventional clock supply device X having the above configuration, after the external reset signal b changes from the reset state to the reset release state after the power is turned on, the multiplied clock c is pulled in. During the period from the state to the stable oscillation state, the clock is not supplied to the microcomputer 10, the first function block 11, and the second function block 12, so that there is a period during which these cannot operate, which is a problem.

In the conventional clock supply device X, in the power saving mode, the divided clock is supplied as described above to reduce the operation speed and realize low power consumption. In this case, the clock multiplication PLL 303 is used. The clock multiplying PLL 303 consumes power even in the power saving mode because the operation is continued even if it is not necessary to operate, which is still a problem.

Therefore, the present invention has been made in view of such a problem, and an object of the present invention is to supply a clock without waiting for oscillation stabilization of a clock multiplying PLL even immediately after power-on. It is an object of the present invention to provide a clock supply device and a clock supply method capable of performing a high-speed operation, and realizing low power consumption by stopping an operation of a clock multiplying PLL in a power saving mode. .

[0023]

According to a first aspect of the present invention, there is provided a clock supply apparatus comprising:
A clock multiplying PLL (phase locked loop) for inputting a reference clock and outputting a frequency-multiplied clock obtained by multiplying the frequency of the reference clock by a predetermined multiple, and dividing the frequency-divided clock to a predetermined frequency division ratio; A frequency divider circuit that outputs a frequency-divided clock having a frequency division ratio of: a selector that selects one of the frequency-divided clock and the reference clock and outputs it as a system clock; and a selection of the system clock that is output by the selector. And a control circuit for controlling

According to a second aspect of the present invention, in the clock supply apparatus according to the first aspect,
The control circuit receives the reference clock and an external reset signal, and outputs a frequency-divided reset signal in a reset state when the external reset signal becomes valid, and the reference clock that is input after the external reset signal is released. Is counted, and when the counted value becomes equal to or more than a predetermined number, a frequency-divided reset signal in a reset release state is output.The selector outputs the reference clock when the frequency-divided reset signal is in a reset state. When the frequency-divided reset signal is in a reset release state, the frequency-divided clock is
It is output as a system clock.

According to a third aspect of the present invention, in the clock supply device according to the first or second aspect, the control circuit inputs the reference clock and a power saving mode signal, and When the power saving mode signal becomes valid, the PLL stop signal in the normal state is counted, and the reference clock input after the power saving mode signal is released is counted a predetermined number, and the counted value becomes a predetermined number or more. When the PLL stop signal is in the normal state, the selector outputs the reference clock when the PLL stop signal is in the normal state, and outputs the divided clock when the PLL stop signal is in the stop state as the system clock. Output.

In a clock supply method according to a fourth aspect of the present invention, a reference clock is input to a system LSI, and the reference clock is frequency-multiplied to a predetermined multiple by a clock multiplication PLL (phase locked loop). A clock supply method for supplying a clock or a divided clock obtained by dividing the multiplied clock to a predetermined number as an operation clock, wherein any one of the multiplied clock or the divided clock and the reference clock is an operation clock. And a clock selecting means for selecting and outputting as.

In the clock supply method according to a fifth aspect of the present invention, in the clock supply method according to the second aspect,
The clock selecting means selects the multiplied clock or the divided clock when the system LSI is operating normally, and selects the reference clock during a predetermined period when the power of the system LSI is turned on. Output.

In the clock supply method according to a sixth aspect of the present invention, in the clock supply method according to the fourth or fifth aspect, the clock selection means is provided when the system LSI is operating normally. When the multiplied clock or the divided clock is operating in the power saving mode, the reference clock is selected and output.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. Note that the embodiment shown here is merely an example, and is not necessarily limited to this embodiment. Embodiment 1 First, a clock supply device according to the present invention will be described as a first embodiment with reference to the drawings. The clock supply device A according to the present embodiment receives a reference clock, outputs a multiplied clock obtained by multiplying the frequency of the reference clock by a predetermined multiple, and a predetermined frequency division of the multiplied clock. A frequency dividing circuit that divides the frequency by a ratio and outputs at least one or more types of frequency dividing ratios; a selector that selects one of the frequency-divided clock and the reference clock and outputs it as a system clock; And a control circuit for controlling the selection.

Further, the control circuit inputs a reference clock and an external reset signal from outside, and outputs a frequency-divided reset signal in a reset state when the external reset signal becomes valid, and inputs the divided reset signal after the external reset signal is released. The reference clock is counted by a predetermined number, and when the counted value becomes equal to or more than a predetermined number, a divided reset signal in a reset release state is output. When the divided reset signal is in a reset state, the selector divides the reference clock by dividing. When the reset signal is in the reset release state, the divided clock is output as a system clock. Further, the control circuit inputs a reference clock and a power saving mode signal from the outside, and outputs a PLL stop signal in a normal state when the power saving mode signal becomes valid, and a reference signal inputted after the power saving mode signal is released. A predetermined number of clocks are counted, and when the counted value exceeds a predetermined number, the PLL in a stopped state is stopped.
The stop signal is output, and the selector outputs the reference clock as the system clock when the PLL stop signal is in the normal state, and outputs the divided clock as the system clock when the PLL stop signal is in the stop state.

Hereinafter, the clock supply device A will be described.
This will be described in more detail with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a clock supply device A according to the present embodiment, and FIG. 2 is a diagram illustrating operation timings of the clock supply device A according to the present embodiment.

As shown in FIG. 1, a clock supply device A according to the present embodiment
, External reset input means 102, and clock multiplication PL
L103, a control circuit 104, a frequency dividing circuit 105, a first selector 106, a second selector 107, and a third selector 108. The clock supply device A includes a microcomputer 10 and a first functional block 1
1 and the second functional block 12.

The clock multiplying PLL 103 receives the reference clock a, multiplies the frequency of the input reference clock a to a predetermined multiple, and outputs the multiplied clock c.
The control circuit 104 receives the reference clock a, the external reset signal b, and the power-saving mode signal m, and receives a frequency-divided reset signal d, a clock control signal h, a system reset signal 1, a PLL stop signal n, Is output. Dividing circuit 10
Numeral 5 receives the multiplied clock c, divides the input multiplied clock c into a predetermined frequency division number, for example, divide-by-2, divide-by-4, divide-by-8, and respectively divides the first divided clock e and the second divided clock e. The divided clock f is output as the third divided clock g.

The first selector 106 generates a first divided clock e, a second divided clock f, a third divided clock g,
A reference clock a and a clock control signal h are input, and a first frequency-divided clock e and
A necessary clock is selected from the second frequency-divided clock f, the third frequency-divided clock g, and the reference clock a, and the selected clock is used as a first system clock i.
Output to 0. The output of the first system clock i is stopped depending on the value of the clock control signal h.

The second selector 107 outputs a first divided clock e, a second divided clock f, a third divided clock g,
A reference clock a and a clock control signal h are input, and a first frequency-divided clock e and
A required clock is selected from the second divided clock f, the third divided clock g, and the reference clock a, and the selected clock is output to the first functional block 11 as a second system clock j. Also, depending on the value of the clock control signal h, the second
The output of the system clock j is stopped.

The third selector 108 generates a first divided clock e, a second divided clock f, a third divided clock g,
A reference clock a and a clock control signal h are input, and a first frequency-divided clock e and
A required clock is selected from the second frequency-divided clock f, the third frequency-divided clock g, and the reference clock a, and is output to the second functional block 12 as a third system clock k. Also, depending on the value of the clock control signal h, the third
The output of the system clock k is stopped.

The clock supply device A thus configured
Will be described with reference to FIG. First, when the power is turned on (FIG. 2.X), the external reset signal b is in a reset state, but then changes to a reset release state. When the power is turned on, the clock multiplication PLL
Reference numeral 103 inputs the reference clock a and outputs a multiplied clock c whose frequency is multiplied by a predetermined multiple of the reference clock a. At this time, after the power is turned on and the operation is started, the clock multiplying PLL 103 cannot pull in the stable multiplied clock c because it is a pull-in period until a predetermined time elapses. Therefore, the supply of the stable multiplied clock c is started. In other words, the multiplied clock c during this period is in a retracted state for a while after the power is turned on, but enters a stable oscillation state after a predetermined time has elapsed.

After the external reset signal b changes from the reset state to the reset release state, the control circuit 104 counts the reference clock a for at least the time corresponding to the pull-in period of the clock multiplying PLL 103, and the pull-in period ends. Later, that is, when the multiplied clock c changes from the pulled-in state to the stable oscillation state, the frequency-divided reset signal d is changed from the reset state to the reset release state and output.

Next, the frequency dividing circuit 105 inputs the multiplied clock c and the frequency-divided reset signal d, and after the frequency-divided reset signal d is in the reset release state, the frequency-divided clock c is divided into a predetermined frequency dividing ratio. (Here, it is assumed that the frequency is divided by 2, 4, and 8.)
And outputs them as a first divided clock e, a second divided clock f, and a third divided clock g.

After the first divided clock e, the second divided clock f, and the third divided clock g are in the output state, the clock control signal h changes from the reference clock output state to the normal operation state.

When the clock control signal h is in the reference clock output state, the first selector 106, the second selector 107, and the third selector 108 select the reference clock a,
Each of the first selector 106, the second selector 107, and the third selector 108 outputs a reference clock a as a first system clock i, a second system clock j, and a third system clock k.

When the clock control signal h changes from the reference clock output state to the normal operation state, the first selector 106
From this, it is assumed that, for example, the first frequency-divided clock e is selected and output as the first system clock i. Similarly, the second divided clock f is selected from the second selector 107 and output as the second system clock j, and the third divided clock g is selected and output as the third system clock k from the third selector 108. .

After the external reset signal b changes from the reset state to the reset release state, the control circuit 104
The system reset signal 1 is changed from the reset state to the reset release state and output.

The microcomputer 10 receives the first system clock i and the system reset signal 1, the first functional block 11 receives the second system clock j and the system reset signal 1, and the second functional block 12 receives the third system clock k and the system reset signal 1. After the reset signal 1 is input and the system reset signal 1 enters the reset release state, each block starts operating at the rate of the reference clock a.

After that, after the clock control signal h changes from the reference clock output state to the normal operation state, the microcomputer 10 operates at the rate of the first frequency-divided clock e.
The first function block 11 operates at the rate of the second divided clock f, and the second function block 12 operates at the rate of the third divided clock g.

Next, as described above, the microcomputer 10, the first functional block 11, and the second functional block 12
Starts operating, the system LSI operates in the power saving mode, that is, when the power saving mode signal m changes from the normal operation state to the power saving mode state (FIG. 2.Y),
The operation of the clock supply device A will be described.

When the power saving mode signal m changes from the normal operation state to the power saving mode state, the clock control signal h output from the control circuit 104 also changes from the normal operation state to the power saving mode simultaneously with the change in the power saving mode signal m. Change to a state.

Here, the first selector 106, the second selector 107, and the third selector 108 control the clock control signal h
Changes from the normal operation state to the power saving mode state, the third selector 108 stops supplying the third system clock k, the second selector 107 stops supplying the second system clock j, and the first selector 106 stops supplying the second system clock j. Outputs the reference clock a as the first system clock i. As a result, the operation speed of the microcomputer 10 is increased by the clock multiplication PL.
The rate before the multiplication by L103, that is, the rate of the reference clock a, is followed, and the first function block 11 and the second function block 12 are in an operation stop state to realize a power saving mode with reduced power consumption. Here, by stopping the supply of the third system clock k and the supply of the second system clock j, the operations of the first function block 11 and the second function block 12 are stopped, and the power saving mode is set. However, by stopping the supply of the first system clock i and the supply of the second system clock j, the microcomputer 10 and the first
The operation of the functional block 11 may be stopped to realize the power saving mode. Further, by stopping the supply of the first system clock i and the supply of the third system clock k, the operations of the microcomputer 10 and the second function block 12 are stopped, and the power saving mode is realized. You may.

When the power saving mode signal m changes from the normal operation state to the power saving mode state, the PLL stop signal n changes from the normal state to the stop state and is output from the control circuit 104. Therefore, the clock multiplication PLL 103 is a PLL
The operation is stopped when the stop signal n changes to the stop state.

Thereafter, when the power saving mode signal m changes from the power saving mode state to the normal operation state (FIG. 2.
To explain Z), first, the PLL stop signal n output from the control circuit 104 changes from the stop state to the normal operation state and is output. The clock multiplication PLL 103 is
When the L stop signal n changes from the stop state to the normal operation state, the output of the multiplied clock c is started again. Until a predetermined time elapses, a stable multiplied clock c cannot be generated because the pull-in period is reached. After the elapse, a stable oscillation period is started, so that the supply of a stable multiplied clock is started.
That is, the multiplied clock c in this period changes from the pulled-in state to the stable oscillation state and is output.

In the control circuit 104, the power saving mode signal m
Counts the reference clock a for at least the time corresponding to the pull-in period of the clock multiplying PLL 103 after the state changes from the power saving mode state to the normal state. When the state changes, the frequency-divided reset signal d is changed from the reset state to the reset release state and output.

Next, the frequency dividing circuit 105 inputs the multiplied clock c and the frequency-divided reset signal d. And outputs them as a first divided clock e, a second divided clock f, and a third divided clock g.

Thereafter, the control circuit 104 changes the clock control signal h from the power saving mode state to the normal operation state and outputs it. Then, the first selector 106 and the second selector 1
07, the third selector 108 selects the third frequency-divided clock g and outputs it as the third system clock k after the clock control signal h changes from the power saving mode state to the normal operation state. 2 selector 107 is the second
The divided clock f is selected and output as the second system clock j, and the first selector 106 selects the first divided clock e and outputs it as the first system clock i. As a result, the microcomputer 10, the first functional block 1
1. The second function block 12 returns to the normal operation state.

As described above, according to the clock supply device of the first embodiment, the clock multiplication PLL is used when the power is turned on.
The microcomputer 10, the first functional block 11, and the second functional block 12 communicate with each other via the first selector 106, the second selector 107, and the third selector 108 during a period from the end of the pull-in period 103 to the stable oscillation state. Therefore, the operation clock (reference clock) can be input, so that the operation can be started immediately after the power is turned on.

In the power saving mode, an operation clock (reference clock) is input via the first selector 106 while the first function block 11 and the second function block 12 are stopped as described above. Thus, only the microcomputer 10 can be operated. That is, the microcomputer 10, the first functional block 11,
It is possible to stop supplying the operation clock to the non-operational blocks of the second functional block 12 and to input the reference clock to the blocks performing the operation. , While reducing power consumption.

In the power saving mode, the control circuit 104
By outputting the stopped nPLL stop signal to the clock multiplying PLL 103 from, the operation of the clock multiplying PLL 103 can be stopped, so that further lower power consumption can be realized.

Although the clock supply device has been described in the present embodiment, the configuration of the device is not limited to this as long as a similar effect can be obtained. That is, a reference clock is input to the system LSI, and the reference clock is frequency-multiplied to a predetermined multiple by a clock multiplication PLL (phase locked loop), or a divided clock obtained by dividing the frequency of the multiplied clock to a predetermined number. , As an operation clock, provided with clock selection means for selecting and outputting any one of a multiplied clock or a divided clock and a reference clock as an operation clock. Good. further,
The clock selecting means selects and outputs a multiplied clock or a divided clock when the system LSI is operating normally, and selects and outputs a reference clock during a predetermined period when the power of the system LSI is turned on. Well,
The clock selecting means selects and outputs the multiplied clock or the divided clock when the system LSI is operating normally, and selects and outputs the reference clock when the system LSI is operating in the power saving mode. It may be.

[0058]

As described above, according to the clock supply device of the first aspect of the present invention, at least the clock multiplying PLL for outputting the multiplied clock obtained by multiplying the frequency of the reference clock by a predetermined multiple, and the clock multiplying clock having at least the multiplied clock. A frequency divider circuit that outputs a frequency-divided clock having one or more types of frequency division ratios, a selector that selects one of the frequency-divided clock and the reference clock and outputs it as a system clock, and a system clock that is output by the selector. And a control circuit for controlling the selection.
If used for SI, immediately after power-on, system LSI
Operation can be started.

According to the clock supply device of the present invention, the control circuit inputs the reference clock and the external reset signal, and when the external reset signal becomes valid, the frequency-divided reset signal in a reset state. A predetermined number of the reference clocks input after the external reset signal is released, and when the counted value becomes a predetermined number or more, outputs a frequency-reset reset signal in a reset release state, and outputs the selector Outputs the reference clock as the system clock when the frequency-divided reset signal is in the reset state, and outputs the frequency-divided clock as the system clock when the frequency-divided reset signal is in the reset-released state. Then, it becomes possible to input the reference clock as the operation clock when desired. Further, with the above configuration, the clock can be supplied immediately after power-on without waiting for the oscillation stabilization time of the clock multiplication PLL.

According to the clock supply device of the third aspect of the present invention, the control circuit inputs the reference clock and the power saving mode signal, and when the power saving mode signal becomes valid, the PLL is stopped in the normal state. A predetermined number of the reference clocks inputted after the power saving mode signal is released, and when the counted value becomes equal to or more than a predetermined number, outputs a PLL stop signal in a stopped state. When the PLL stop signal is in the normal state, the reference clock is output. When the PLL stop signal is in the stop state, the frequency-divided clock is output as the system clock. Therefore, any system LSI using this clock supply device can be used. For example, the operation of the clock multiplying PLL can be stopped at a desired time, so that further lower power consumption can be realized.
With the above configuration, the clock multiplication P
The clock can be supplied without waiting for the LL oscillation stabilization time.

According to the clock supply method of the fourth aspect of the present invention, the clock supply means for selecting and outputting any one of the multiplied clock or the divided clock and the reference clock as the operation clock is provided. With a system LSI using this clock supply method, operation can be started immediately after power-on.

According to the clock supply method described in claim 5 of the present invention, the clock selecting means outputs the multiplied clock or the divided clock when the system LSI is operating normally.
Since the reference clock is selected and output during a predetermined period when the power of the system LSI is turned on, if the system LSI uses this clock supply method,
It becomes possible to input a reference clock as an operation clock when desired. Further, with the above configuration, the clock can be supplied immediately after power-on without waiting for the oscillation stabilization time of the clock multiplication PLL.

According to the clock supply method of the sixth aspect of the present invention, the clock selecting means outputs the multiplied clock or the divided clock when the system LSI is operating normally.
Since the reference clock is selected and output when operating in the power saving mode, the operation of the clock multiplying PLL can be stopped at a desired time if the system LSI uses this clock supply method. Therefore, further lower power consumption can be realized. Further, with the above configuration, the clock can be supplied immediately after power-on without waiting for the oscillation stabilization time of the clock multiplication PLL.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a clock supply device according to an embodiment.

FIG. 2 is a diagram showing operation timing of the clock supply device according to the present embodiment.

FIG. 3 is a block diagram showing a configuration of a conventional clock supply device.

FIG. 4 is a diagram showing operation timing of a conventional clock supply device.

[Explanation of symbols]

 Reference Signs List 101 Reference clock input means 102 External reset input means 103 Clock multiplication PLL 104 Control circuit 105 Divider circuit 106 First selector 107 Second selector 108 Third selector 10 Microcomputer 11 First function block 12 Second function block

Claims (6)

[Claims] 1. A clock multiplication PLL (phase locked loop) for receiving a reference clock and outputting a frequency-multiplied clock obtained by multiplying the frequency of the reference clock by a predetermined multiple, and dividing the frequency of the multiplied clock to a predetermined frequency division ratio A frequency divider circuit that outputs a frequency-divided clock having at least one or more frequency division ratios; a selector that selects one of the frequency-divided clock and the reference clock and outputs the selected clock as a system clock; And a control circuit for controlling selection of the system clock. 2. The clock supply device according to claim 1, wherein the control circuit inputs the reference clock and an external reset signal, and when the external reset signal becomes valid, outputs a frequency-divided reset signal in a reset state. Counting a predetermined number of the reference clocks input after the external reset signal is released, and when the counted value becomes a predetermined number or more, outputs a frequency-divided reset signal in a reset released state; A clock supply device that outputs the reference clock as the system clock when the frequency-divided reset signal is in a reset state, and outputs the frequency-divided clock as the system clock when the frequency-divided reset signal is in a reset release state. 3. The clock supply device according to claim 1, wherein the control circuit inputs the reference clock and a power saving mode signal, and the control circuit enters a normal state when the power saving mode signal becomes valid. A predetermined number of the reference clocks inputted after the power saving mode signal is released, and outputs a stopped PLL stop signal when the counted value becomes a predetermined number or more, A clock supply device, wherein the selector outputs the reference clock as the system clock when the PLL stop signal is in a normal state and the divided clock as the system clock when the PLL stop signal is in a stop state. 4. A reference clock is input to a system LSI, and the reference clock is frequency-multiplied to a predetermined multiple by a clock multiplication PLL (phase locked loop), or the multiplied clock is divided into a predetermined number. A clock supply method for supplying the divided clock as an operation clock, comprising: a clock selection unit that selects and outputs any one of the multiplied clock or the divided clock and the reference clock as an operation clock; A clock supply method. 5. The clock supply method according to claim 4, wherein the clock selection unit is configured to, when the system LSI is operating normally, output the multiplied clock or the divided clock to the system LSI.
And selecting and outputting the reference clock during a predetermined period when the power is turned on. 6. The clock supply method according to claim 4, wherein the clock selection unit is configured to save the multiplied clock or the divided clock when the system LSI is operating normally. When operating in a mode, selecting and outputting the reference clock.