JPH0720964A - Electric power saving circuit and its control method - Google Patents

Abstract

PURPOSE:To provide an electric power saving circuit and its control method which are improved in the saving efficiency of electric power. CONSTITUTION:In the electric power saving circuit and its control method, when an event control circuit 5 which receives a power saving mode start instruction from a CPU 1 controls the entirety to enter power saving mode, only a timer counter 2' and a low-frequency crystal oscillation circuit 6 which supplies a clock are made to operate and a high-frequency crystal oscillation circuit 3 which supplies a high frequency clock to the CPU 1 in normal mode and a multi-stage frequency dividing circuit 4 which supplies a low-frequency clock to the timer counter 2' by sequential frequency division are stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power consumption saving circuit used in a wireless terminal device, and more particularly to a power consumption saving circuit capable of significantly reducing power consumption and a control method thereof.

[0002]

2. Description of the Related Art First, a conventional power saving circuit will be described with reference to FIG. FIG. 5 is a configuration block diagram of a conventional power consumption saving circuit. As shown in FIG. 5, a conventional power consumption saving circuit (power saving circuit) includes a CPU 1 having a power save mode,
Timer counter 2 that counts power save mode time and interrupts CPU 1 to cancel power save mode
, A high-frequency crystal oscillation circuit 3 for generating a high-frequency clock (CPU clock) to be supplied to the CPU 1, and a high-frequency clock generated from the high-frequency crystal oscillation circuit 3 are sequentially divided and dropped into a low-frequency clock, which is then stored in the timer counter 2. And a multi-stage frequency dividing circuit 4 for supplying.

Next, each component will be specifically described. The CPU 1 is a CPU that operates with a high-frequency (for example, MHz order) clock and has a power save mode (low power consumption state). When the power save mode is entered, it is not necessary to supply the clock, and the timer counter 2 The power save mode is canceled by the interruption of 1) and the CPU clock is applied from the high frequency crystal oscillation circuit 3 to return to the normal mode.

The timer counter 2 operates with a low-frequency (for example, KHz order) clock supplied from the multi-stage frequency dividing circuit 4, and when the power save mode is entered, it counts the time from the CPU 1 to the preset cancellation, The CPU 1 interrupts the power save mode release.

The high frequency crystal oscillator circuit 3 supplies a high frequency (eg, MHz order) clock (CP) to the CPU 1.
It is an oscillator circuit that generates a U clock).

The multi-stage frequency dividing circuit 4 is a high frequency crystal oscillating circuit 3
Is sequentially divided to generate a low frequency clock (KHz order), and the low frequency clock (KHz order) is supplied to the timer counter 2.

Here, the multi-stage frequency dividing circuit 4 will be described in detail with reference to the example of FIG. FIG. 6 is a schematic explanatory diagram of a multi-stage frequency dividing circuit. The multi-stage frequency dividing circuit 4 connects a plurality of frequency dividing circuits in series and creates a low frequency from a high frequency.
For example, when a clock of 19.2 MHz to 200 Hz is generated, as shown in FIG. 6, a plurality of 1/2 divider circuits, 1/3 divider circuits, and 1/5 divider circuits are combined to make a total of 1
The frequency dividing circuits are connected in series so as to be / 96000.

Here, the multi-stage frequency dividing circuit 4 is composed of many flip-flops (counters), and if the frequency to be handled is a high frequency such as the order of MHz, the flip-flop circuit near the first stage of the multi-stage frequency dividing circuit. It is necessary to operate the flash at high speed, and the power consumption is also large.

Next, a conventional method for controlling the power saving circuit will be described. In the conventional power saving circuit control method, as shown in FIG. 5, when the CPU 1 shifts to the power save mode, the timer counter 2 counts until the preset power save mode time ends, and When it reaches, the timer counter 2 interrupts the CPU 1 to cancel the power save mode, and C
PU1 is designed to return to the normal mode.

Therefore, the CPU supplied from the high-frequency crystal oscillator circuit 3 to the CPU 1 in the power save mode.
The clock for use is unnecessary and the high frequency crystal oscillation circuit 3 can be stopped. However, in order to keep the timer counter 2 operating at all times, the high frequency crystal oscillation circuit 3 and the high frequency clock generated from the high frequency crystal oscillation circuit 3 are required. Timer counter 2
Multi-stage frequency divider circuit 4 that supplies frequency-divided low-frequency clocks for
Must be constantly operated, and the power supply voltage Vcc to the high frequency crystal oscillation circuit 3 and the multi-stage frequency dividing circuit 4 must be constantly supplied.

[0011]

Therefore, in the above conventional power saving circuit and its control method, the low frequency clock is sufficient although the high frequency CPU clock can be stopped during the power save mode. In order to operate such a timer clock, the high-frequency crystal oscillator circuit 3 and the multi-stage frequency dividing circuit 4 must be operated, which causes a problem of low power saving efficiency.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a power consumption saving circuit and a control method thereof in which the efficiency of saving the power consumption is improved.

[0013]

The invention according to claim 1 for solving the above-mentioned problems of the prior art is a CPU having a power save mode, a timer counter for counting the power save mode time, and the CPU. A power consumption saving circuit having a high-frequency oscillating circuit for supplying a high-frequency clock and a multi-stage frequency dividing circuit for sequentially dividing a high-frequency clock generated from the high-frequency oscillating circuit to generate a low-frequency clock A low-frequency oscillation circuit that supplies a low-frequency clock to the timer counter, a clock selection switch that selects a clock input to the timer counter, an output control circuit that controls the output of the high-frequency oscillation circuit, and the high-frequency oscillation circuit. It gives instructions to start / stop the oscillator circuit and the low-frequency oscillator circuit, and Switch instruction, output control circuit control instruction, power save mode start instruction from the CPU at power save mode transition, timer counter start instruction, and power save mode release timer counter The CPU is provided with an event control circuit for receiving a timer count completion signal from the CPU and making an interrupt for canceling the power save mode.

According to a second aspect of the present invention for solving the above-mentioned problems of the conventional example, in the control method of the power consumption saving circuit according to the first aspect, when shifting to the power save mode, the CPU saves power. Upon receiving the mode start command, the event control circuit activates the low frequency oscillation circuit, switches the clock selection switch to output the clock from the low frequency oscillation circuit to the timer counter, and activates the timer counter. The output control circuit is controlled to stop the clocks to the CPU and the multi-stage frequency dividing circuit, and to stop the high frequency oscillation circuit.

According to a third aspect of the present invention for solving the above-mentioned problems of the conventional example, in the control method of the power consumption saving circuit according to the first aspect, when the power save mode is released, the timer counter is operated by the timer. The event control circuit that receives the count completion signal activates the high frequency oscillation circuit, controls the output control circuit after the oscillation stabilization wait time has elapsed, and outputs the clock from the high frequency oscillation circuit to the CPU and the multi-stage frequency dividing circuit. The clock from the multistage divider circuit is output to the timer counter, and an interrupt for canceling the power save mode is performed to the CPU to output the clock to the CPU.
It is characterized in that the power save mode of the PU is released and the low frequency oscillation circuit is stopped.

[0016]

According to the first aspect of the present invention, the event control circuit receives the power save mode start command from the CPU at the time of transition to the power save mode, starts the timer counter, and starts the low frequency oscillator circuit to start the clock selection switch. To output the clock from the low-frequency oscillation circuit to the timer counter, stop the high-frequency oscillation circuit, and receive the timer count completion signal from the timer counter when the power save mode is released, and activate the high-frequency oscillation circuit to control the output. The circuit is controlled to output the clock from the high-frequency oscillator circuit to the CPU and the multi-stage frequency divider circuit, and the clock selection switch is switched to output the clock from the multi-stage frequency divider circuit to the timer counter. Power saving that interrupts and stops the low-frequency oscillation circuit Since the road, when a transition to the power save mode can be stopped and a high-frequency oscillation circuit and a multi-stage divider, the power consumption during the power save mode can be significantly reduced.

According to the second aspect of the present invention, when the event control circuit receives the power save mode start command from the CPU, the low frequency oscillation circuit is activated, and the clock selection switch is switched to change the clock from the low frequency oscillation circuit. 2. The control of the power consumption saving circuit according to claim 1, wherein the power consumption saving circuit is output to a timer counter, starts the timer counter, controls the output control circuit to stop the clock to the CPU and the multi-stage frequency dividing circuit, and stops the high frequency oscillation circuit. Since it is a method,
When shifting to the power save mode, the high frequency oscillator circuit and the multi-stage frequency dividing circuit can be stopped, and the power consumption during the power save mode can be significantly reduced.

According to the third aspect of the invention, when the event control circuit receives the timer count completion signal from the timer counter, the high frequency oscillation circuit is activated, and after the oscillation stabilization wait time has elapsed, the output control circuit is controlled to control the high frequency oscillation. The clock from the circuit is output to the CPU and the multi-stage frequency dividing circuit, and the clock selection switch is switched to output the clock from the multi-stage frequency dividing circuit to the timer counter, and an interrupt for canceling the power save mode is issued to the CPU. Since the power saving mode of the CPU is released and the low frequency oscillation circuit is stopped, the control method of the power consumption saving circuit according to claim 1 is adopted. Therefore, it is easy to switch from the low frequency oscillation circuit to the high frequency oscillation circuit when the power save mode is released. Can be done.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a configuration block diagram of a power consumption saving circuit used in a wireless device according to an embodiment of the present invention. It should be noted that parts having the same configuration as in FIG.

As shown in FIG. 1, the power consumption saving circuit (power saving circuit) of the present embodiment has a configuration similar to that of the conventional power consumption saving circuit, and includes a CPU 1 having a power save mode and a power save mode time. A timer counter 2'for counting, a high-frequency crystal oscillation circuit 3 for generating a high-frequency clock (CPU clock) to be supplied to the CPU 1, and a high-frequency clock generated by the high-frequency crystal oscillation circuit 3 are sequentially divided to generate a low-frequency clock. And a multi-stage frequency dividing circuit 4 for reducing the frequency, and as a characteristic part of this embodiment, an event control circuit 5 for controlling the entire power saving circuit and a low frequency clock dedicated to the timer counter 2'in the power save mode are generated. Low frequency crystal oscillator circuit 6 and a clock for selecting the clock to the timer counter 2 '. And-click selection switch (SEL) 7,
Output control circuit 8 for controlling the output of the high-frequency crystal oscillation circuit 3
And the power switch SW (1) 9 of the high-frequency crystal oscillation circuit 3
And the power switch SW (2) 10 of the low frequency crystal oscillation circuit 6
And are provided.

Next, each component of the power consumption saving circuit of this embodiment will be specifically described. CPU1
It is a CPU that operates with a high-frequency (for example, MHz order) clock as in the conventional case and has a power save mode (low power consumption state). It is not necessary to supply a clock when shifting to the power save mode, and the event control circuit 5 Power save mode release NMI interrupt from (Non
Maskable Interrupt: The highest priority interrupt) a cancels the power save mode and returns to the normal mode.

The timer counter 2'operates under the control of the event control circuit 5, and when the power save mode is entered, the timer count start signal b from the event control circuit 5 starts counting the time until the power save mode is released. When the power save mode time set by the CPU 1 is reached, the event control circuit 5 is notified of the completion of counting by the timer count completion signal c.

In the normal mode, the timer counter 2'operates with a clock obtained by dropping the high frequency clock (for example, MHz order) generated from the high frequency crystal oscillation circuit 3 to a low frequency (for example, KHz order) by the multistage frequency dividing circuit 4. In the power save mode, the low-frequency crystal oscillation circuit 6 operates with a low-frequency clock (for example, KHz order), and these two clocks are switched by the clock selection switch 7.

The high-frequency crystal oscillator circuit 3 has the same C
The event control circuit 5 is an oscillation circuit that generates a high-frequency (eg, MHz order) clock supplied to the PU 1.
ON / O of power switch SW (1) 9 controlled by
Start / stop is controlled by FF, and event control circuit 5
The output is controlled by the output control circuit 8 controlled by.

Since the high-frequency crystal oscillation circuit 3 normally generates a high frequency of the order of MHz, the oscillation frequency is not stable immediately after the power is turned on, and an unstable output is sent to the CPU 1 and the multi-stage frequency dividing circuit 4. In order not to give it, the output control circuit 8 controls it.

The multi-stage frequency dividing circuit 4 is a conventional low frequency clock (KHz order) by sequentially dividing the high frequency clock (MHz order) oscillated by the high frequency crystal oscillator circuit 3 as in the conventional case.
In order to supply a clock to the timer counter 2'in the normal mode. A plurality of divider circuits as shown in FIG. 6 are combined and connected in series so as to obtain a desired frequency. is there.

The event control circuit 5 controls the entire power saving circuit of this embodiment, is composed of a logic circuit, and sequentially controls each constituent element.
Specifically, in response to the power save mode start command from the CPU 1, the timer counter 2'is activated by the timer count activation signal b, the clock selection switch 7 is controlled by the clock selection signal d, and the output control circuit control signal e. Control of the output control circuit 8 and the power switch SW (1) 9 of the high frequency crystal oscillation circuit 3 by the high frequency crystal oscillation circuit power control signal g and the power of the low frequency crystal oscillation circuit 6 by the low frequency crystal oscillation circuit power control signal f The switch SW (2) 10 is controlled, and the power saving mode canceling NMI interrupt (highest priority interrupt) a is issued to the CPU 1 upon receiving the timer count completion signal c from the timer counter 2 '.

The low-frequency crystal oscillator circuit 6 is an oscillator circuit for generating a low-frequency (for example, KHz order) clock supplied to the timer counter 2'in the power save mode, and a power switch controlled by the event control circuit 5. The start / stop is controlled by turning on / off the SW (2) 10.

The clock selection switch (SEL) 7 is a switch for switching the clock of the timer counter 2'under the control of the event control circuit 5. In the normal mode, the high frequency clock generated from the high frequency crystal oscillation circuit 3 is multistage. A clock dropped to a low frequency by the frequency dividing circuit 4 is selected, and in the power save mode, a clock generated from the low frequency crystal oscillation circuit 6 is selected.

The output control circuit 8 controls the output of the high-frequency crystal oscillation circuit 3 under the control of the event control circuit 5.
It is an ND circuit. The output of the high-frequency crystal oscillator circuit 3 and the output control circuit control signal e from the event control circuit 5 are AN
It is input to the D circuit, the logical product is taken, and the output is the CPU
It is input to the 1 and multi-stage frequency dividing circuit 4.

Power switch SW of high-frequency crystal oscillator circuit 3
(1) 9 is a switch for turning on / off the power of the high-frequency crystal oscillation circuit 3 under the control of the event control circuit 5. Specifically, in the normal mode, the power switch SW (1) 9 is turned on by the high frequency crystal oscillation circuit power supply control signal g from the event control circuit 5 so that the high frequency crystal oscillation circuit 3 is supplied with the power supply voltage Vcc. Has become.

The detailed structure of the power switch SW (1) 9 is as follows.
It is composed of npn type transistor, the power supply voltage Vcc is applied to the collector (C), the high frequency crystal oscillator power supply control signal g from the event control circuit 5 is input to the base (B), and the emitter (E) output. Serves as a power source for the high-frequency crystal oscillator circuit 3. High frequency crystal oscillation circuit from the event control circuit 5 Only when the power supply control signal g is turned on and a positive voltage is applied to the base (B), current flows from the collector (C) to the emitter (E), and the high frequency crystal oscillation is generated. Circuit 3 power is O
It becomes N.

Power switch SW of the low frequency crystal oscillation circuit 6
(2) 10 is a switch for turning on / off the power supply of the low-frequency crystal oscillation circuit 6 under the control of the event control circuit 5. Specifically, in the power save mode, the power switch SW (2) 10 is turned on by the low frequency crystal oscillation circuit power supply control signal f from the event control circuit 5, and the power supply voltage Vcc is supplied to the low frequency crystal oscillation circuit 6. It is supposed to do.

Like the power switch SW (1) 9, the power switch SW (2) 10 is also composed of an npn-type transistor, and the collector (C) is supplied with the power supply voltage Vcc,
The low frequency crystal oscillation circuit power supply control signal f from the event control circuit 5 is input to (B), and the emitter (E) output serves as the power supply of the low frequency crystal oscillation circuit 6. The low frequency crystal oscillator circuit power supply control signal f from the event control circuit 5 is turned on.
Only when a positive voltage is applied to the base (B), a current flows from the collector (C) to the emitter (E), and the low frequency crystal oscillation circuit 6 is powered on.

Next, a method of controlling the power consumption saving circuit of this embodiment will be described. In the control method of the power consumption saving circuit of the present embodiment, when the CPU 1 shifts to the power save mode, first, the CPU 1 transfers the data bus 11 to the data bus 11.
The power save mode time is set to the timer counter 2'through the power save mode start command to the event control circuit 5, and the CPU 1 executes a command to shift to the power save mode by executing the power save mode. Transition to. The event control circuit 5 consumes all power until the event control circuit 5 issues a power save mode canceling interrupt a to the CPU 1 after the power save time set in the timer counter 2'has elapsed. It controls the entire power saving circuit.

Upon receiving the power save mode start command from the CPU 1, the event control circuit 5 first turns on the low frequency crystal oscillation circuit power supply control signal f to turn on the power switch SW (2) 10 of the low frequency crystal oscillation circuit 6. The low frequency crystal oscillation circuit 6 is turned on to start up, and then the clock selection signal d of the clock selection switch (SEL) 7 switches the clock of the timer counter 2 ′ to the clock output from the low frequency crystal oscillation circuit 6.

Next, the timer counter 2'is activated by the timer count activation signal b to start counting. Then, the output control circuit control signal e of the output control circuit 8 of the high-frequency crystal oscillation circuit 3 is turned off, and the clocks to the CPU 1 and the multi-stage frequency dividing circuit 4 are stopped. Next, the high frequency crystal oscillation circuit power supply control signal g is turned off to turn off the power switch SW (1) 9 of the high frequency crystal oscillation circuit 3 to stop the high frequency crystal oscillation circuit 3.

By the above operation, the CPU 1 enters the power save mode, the high frequency crystal oscillator circuit 3 and the multi-stage frequency dividing circuit 4 are stopped, the entire system is completely in the power saving state, and the timer counter 2'and the event control are performed. Only the circuit 5 and the low-frequency crystal oscillator circuit 6 that supplies the clock are operating.

During the power save mode, the timer counter 2'continues counting with the clock from the low frequency crystal oscillator circuit 6, and if the timer reaches the power save time set by the CPU 1, the timer counter 2 ' Is a timer count completion signal c to the event control circuit 5.
give.

Upon receiving the timer count completion signal c from the timer counter 2 ', the event control circuit 5 first
The high frequency crystal oscillation circuit power control signal g is turned on, and the power switch SW (1) 9 of the high frequency crystal oscillation circuit 3 is turned on.
The high frequency crystal oscillator circuit 3 is started. However, since the oscillation frequency of the high-frequency crystal oscillator circuit 3 is not stable immediately after the power is turned on, the output control circuit 8 does not operate after the oscillation stabilization wait time elapses.
The output control circuit control signal e is turned on to start the clock supply from the high-frequency crystal oscillation circuit 3 to the CPU 1 and the multi-stage frequency dividing circuit 4. The oscillation stabilization wait time is preset in the event control circuit 5.

After that, a clock selection switch (SEL)
According to the clock selection signal d of 7, the timer counter 2 '
Is switched from the clock from the low frequency crystal oscillation circuit 6 to the clock from the multi-stage frequency dividing circuit 4.

Then, the NMI interrupt a for canceling the power save mode is issued to the CPU 1 to cancel the power save mode of the CPU 1. Since the CPU 1 has already received a stable clock from the high frequency crystal oscillation circuit 3 through the output control circuit 8, the NM from the event control circuit 5 is already received.
The power save mode is canceled by the I interrupt a, and the normal operation mode is entered.

After that, the event control circuit 5 turns off the low frequency crystal oscillation circuit power supply control signal f and turns off the power switch SW (2) 10 of the low frequency crystal oscillation circuit 6 to turn on the low frequency crystal oscillation circuit 6. Stop.

By the above operation, the CPU 1 enters the normal operation mode, the high frequency crystal oscillation circuit 3 and the multi-stage frequency dividing circuit 4 are in the operation state, the entire system is in the normal operation state, and the low frequency crystal oscillation circuit is in operation. 6 will stop.

Next, the power saving processing operation of the CPU 1, the event control circuit 5, and the timer counter 2'in the method of controlling the power saving circuit of this embodiment will be described in more detail with reference to FIGS. 1 and 2 to 4. .
2 is a flowchart showing the processing operation of the CPU 1 of the power saving circuit of this embodiment, FIG. 3 is a flowchart showing the processing operation of the event control circuit 5, and FIG. 4 is a timer counter 2 '. It is a flowchart figure which shows a processing operation. The processing flows shown in FIGS. 2 to 4 are related and are continuous at points (A) to (F).

CPU of the power saving circuit of this embodiment
In the power saving processing of No. 1, as shown in FIG. 2, first, the power save mode time is set to the timer counter 2 '(100), and the power save mode start instruction is output to the event control circuit 5 (110). ), The CPU 1 itself executes a command for shifting to the power save mode (120), and shifts to the power save mode. here,
The setting of the power save mode time specifically indicates a counter value setting instruction, a counter starting instruction, and a counter stopping instruction in the timer counter 2 '.

Then, the power save mode release NMI interrupt a from the event control circuit 5 (process 270 in FIG. 3)
In response to this, the power save mode is canceled (130), the operation mode shifts to the normal operation mode, and the process is terminated.

As shown in FIG. 3, the power saving process of the event control circuit 5 of the power saving circuit of the present embodiment starts upon receiving a power save mode start command (process 110 of FIG. 2) from the CPU 1, and goes low. Frequency crystal oscillator circuit power supply control signal f is turned on (200), and as a result, the power switch SW (2) 10 of the low frequency crystal oscillator circuit 6 is turned on.
Is turned on to activate the low frequency crystal oscillation circuit 6, and then the clock of the timer counter 2'is switched to the clock from the low frequency crystal oscillation circuit 6 by the clock selection signal d of the clock selection switch (SEL) 7 (201 ),
Next, the timer counter 2'is generated by the timer count start signal b.
Is started (210) to start counting.

Then, the output control circuit control signal e of the output control circuit 8 of the high frequency crystal oscillation circuit 3 is turned off (22
0), the clocks to the CPU 1 and the multi-stage frequency dividing circuit 4 are stopped to apparently stop the operation of the multi-stage frequency dividing circuit 4. Next, the high frequency crystal oscillation circuit power supply control signal g is turned off (230), and as a result, the power supply switch SW (1) 9 of the high frequency crystal oscillation circuit 3 is turned off and the high frequency crystal oscillation circuit 3 is turned on.
Will stop.

After the power save time has elapsed, the timer counter 2'provides a timer count completion signal c (see FIG. 3).
Process 330), the high frequency crystal oscillation circuit power supply control signal g is turned ON (240), and as a result,
Power switch SW (1) 9 of high-frequency crystal oscillator circuit 3 is turned on
Then, after the high-frequency crystal oscillation circuit 3 is activated and the oscillation stabilization wait time has elapsed, the output control circuit control signal e to the output control circuit 8 is turned on (250), and the high-frequency crystal oscillation circuit 3 is switched to the CPU 1 and the multi-stage. The supply of the clock to the frequency dividing circuit 4 is restarted.

After that, a clock selection switch (SEL)
According to the clock selection signal d of 7, the timer counter 2 '
Is switched from the clock output from the low-frequency crystal oscillator circuit 6 to the clock output from the multi-stage frequency dividing circuit 4 (260), and the NMI interrupt a for canceling the power save mode is issued to the CPU 1 (270). The power save mode of the CPU 1 is released, the low frequency crystal oscillation circuit power supply control signal f is turned off (280), and the processing is ended. As a result, the power switch S of the low-frequency crystal oscillation circuit 6
W (2) 10 is turned off and the low frequency crystal oscillation circuit 6 is stopped.

In the power saving process of the timer counter 2'of the power saving circuit of this embodiment, as shown in FIG. 4, first, the power saving time is set in advance as an initial setting, and then the event control circuit 5 is set. The process is started by the timer count activation signal b (process 210 in FIG. 3) from the first counter, the counter is first cleared (300), then 1 is added to the counter (310), and the counter value is the CPU1.
It is judged whether or not it is smaller than the power save time set by (320), and if it is smaller, the process returns to step 310, and if it is not smaller (when the power save time is completed), the timer count completion signal c is output to the event control circuit 5. Then (330), the process ends.

According to the power consumption saving circuit and its control method of the present embodiment, when the power save mode is entered, the clock is supplied from the low frequency crystal oscillator circuit 6 dedicated to the timer counter 2 '. It is possible to stop the high-frequency crystal oscillator circuit 3 that outputs the clock for the CPU 1 and the multi-stage frequency dividing circuit 4 for obtaining the low frequency for the timer counter 2 ′ from the high-frequency crystal oscillator circuit 3 in the normal mode. This has the effect of significantly reducing power consumption. Further, when the power save mode is released, the supply destination of the clock can be easily switched from the low frequency oscillation circuit to the high frequency generation circuit, and the power save mode can be released smoothly.

[0054]

According to the first aspect of the present invention, the event control circuit receives the power save mode start command from the CPU at the time of transition to the power save mode, starts the timer counter, and starts the low frequency oscillation circuit to start the clock. Switch the selection switch to output the clock from the low-frequency oscillator circuit to the timer counter, stop the high-frequency oscillator circuit, and receive the timer count completion signal from the timer counter when the power save mode is released, and activate the high-frequency oscillator circuit. The output control circuit is controlled to output the clock from the high frequency oscillation circuit to the CPU and the multi-stage frequency divider circuit, and the clock selection switch is switched to output the clock from the multi-stage frequency divider circuit to the timer counter, and the CPU releases the power save mode. Power consumption to stop the low-frequency oscillation circuit Since the ring circuit, when a transition to the power save mode can be stopped and a high-frequency oscillation circuit and a multi-stage divider, the effect of the power consumption during the power save mode can be significantly reduced.

According to the second aspect of the present invention, when the event control circuit receives the power save mode start command from the CPU, it activates the low frequency oscillation circuit and switches the clock selection switch to switch the clock from the low frequency oscillation circuit. 2. The control of the power consumption saving circuit according to claim 1, wherein the power consumption saving circuit is output to a timer counter, starts the timer counter, controls the output control circuit to stop the clock to the CPU and the multi-stage frequency dividing circuit, and stops the high frequency oscillation circuit. Since it is a method,
When shifting to the power save mode, the high-frequency oscillator circuit and the multi-stage frequency dividing circuit can be stopped, and the power consumption during the power save mode can be significantly reduced.

According to the third aspect of the invention, when the event control circuit receives the timer count completion signal from the timer counter, the high frequency oscillation circuit is activated, and after the oscillation stabilization wait time has elapsed, the output control circuit is controlled to perform the high frequency oscillation. The clock from the circuit is output to the CPU and the multi-stage frequency dividing circuit, and the clock selection switch is switched to output the clock from the multi-stage frequency dividing circuit to the timer counter, and an interrupt for canceling the power save mode is issued to the CPU. Since the power saving mode of the CPU is released and the low frequency oscillation circuit is stopped, the control method of the power consumption saving circuit according to claim 1 is adopted. Therefore, it is easy to switch from the low frequency oscillation circuit to the high frequency oscillation circuit when the power save mode is released. There is an effect that can be done.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a power consumption saving circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart showing a processing operation of the CPU 1 of the power saving circuit of this embodiment.

FIG. 3 is a flowchart showing a processing operation of an event control circuit 5 of the power saving circuit of this embodiment.

FIG. 4 is a flowchart showing a processing operation of a timer counter 2 ′ of the power saving circuit of this embodiment.

FIG. 5 is a configuration block diagram of a conventional power consumption saving circuit.

FIG. 6 is a schematic explanatory diagram of a multi-stage frequency dividing circuit.

[Explanation of symbols]

1 ... CPU, 2, 2 '... Timer counter, 3 ... High frequency crystal oscillation circuit, 4 ... Multi-stage frequency dividing circuit, 5 ... Event control circuit, 6 ... Low frequency crystal oscillation circuit, 7 ... Clock selection switch, 8 ... Output control Circuits, 9, 10 ... Power switch, 11 ... Data bus, a ... Power save mode release interrupt, b ... Timer count start signal,
c ... Timer count completion signal, d ... Clock selection signal, e ... Output control circuit control signal, f ... Low frequency crystal oscillation circuit power supply control signal, g ... High frequency crystal oscillation circuit power supply control signal

Claims (3)

[Claims] 1. A CPU having a power save mode,
A timer counter that counts the power save mode time, a high-frequency oscillator circuit that supplies a high-frequency clock to the CPU, and a multi-stage divider circuit that sequentially divides a high-frequency clock generated from the high-frequency oscillator circuit to generate a low-frequency clock. And a high-frequency oscillation circuit that supplies a low-frequency clock to the timer counter when the power save mode is entered, a clock selection switch that selects a clock input to the timer counter, and the high-frequency oscillator. An output control circuit that controls the output of the oscillation circuit, gives instructions to start and stop the high-frequency oscillation circuit and the low-frequency oscillation circuit, gives instructions to switch the clock selection switch, and gives control instructions to the output control circuit, When entering the power save mode, the power save mode is opened from the CPU. An event control circuit that receives an instruction, issues an instruction to start the timer counter, receives a timer count completion signal from the timer counter when the power save mode is released, and provides the CPU with an interrupt for canceling the power save mode is provided. Characteristic power consumption saving circuit. 2. When transitioning to a power save mode, the event control circuit which has received a power save mode start command from the CPU activates the low frequency oscillation circuit and switches the clock selection switch to switch the low frequency. A clock from an oscillation circuit is output to the timer counter, the timer counter is activated, the output control circuit is controlled to stop the clocks to the CPU and the multi-stage frequency dividing circuit, and the high frequency oscillation circuit is stopped. The method of controlling the power consumption saving circuit according to claim 1, wherein 3. When the power save mode is released, the event control circuit which receives a timer count completion signal from the timer counter activates the high frequency oscillation circuit, and the output control circuit is activated after the oscillation stabilization wait time has elapsed. The CPU controls the clock from the high-frequency oscillator circuit.
And outputting to the multi-stage frequency dividing circuit, switching the clock selection switch to output the clock from the multi-stage frequency dividing circuit to the timer counter, interrupting the power save mode to the CPU, and executing the interrupt to the CPU. 2. The method for controlling a power consumption saving circuit according to claim 1, wherein the power save mode is canceled and the low frequency oscillation circuit is stopped.