JPH05258087A - Microcomputer - Google Patents

Abstract

PURPOSE:To improve the efficiency of a system control by starting the oscillation of a main system clock which is stopped during a low power consumption operation in an arbitrary timing. CONSTITUTION:In a program which controls a microcomputer, the command of the output of a signal for starting the oscillation of the main system clock is executed before more than a time required for stabilizing the oscillation of the main system clock since the low power consumption operation is ended, is executed at the time of a transition from the present low power consumption operation to a normal operation. Then, when the command of the output of the signal for starting the oscillation of the main system clock is executed by the program, a main system clock oscillation circuit 3 starts again the oscillation which is stopped due to the low power consumption operation, during the low power consumption operation. The oscillation of the clock can be stable in the timing in which low power consumption operation is ended, and a sub-system is switched to the main system clock by an operation mode control circuit 7 and a selector 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer, especially a clock for normal operation (hereinafter referred to as main system clock), and a low frequency clock for low power consumption operation (hereinafter referred to as subsystem clock). ), A technology that is effective when applied to control of a microcomputer during a state transition in which a clock is switched in a microcomputer that can also operate.

[0002]

2. Description of the Related Art In addition to a main system clock, a conventional microcomputer can operate at a subsystem clock of a low frequency compared to the main system clock for low power consumption operation. In particular, when the low power consumption operation is performed by the subsystem clock, it is common to suspend the oscillation of the main system clock in order to further reduce the power consumption.

Further, there is a method in which it is possible to select by software whether to stop or continue the oscillation of the main system clock during a low power consumption operation.

As an example of a document describing a technique relating to control of power consumption and a clock, Nikkei BP No. 527 (1991 5)
_13) P182 to P183 ”are available.

[0005]

In the microcomputer using the above-mentioned conventional technique, when the state transitions from the low power consumption operation to the normal operation, the main system clock oscillates only after the low power consumption operation ends. In order to start, it was necessary to secure a time for the main system clock oscillation to stabilize in the state transition. For this reason,
A great deal of time is spent on the state transition, and since the clock is not supplied to the microcomputer during this period, system control using the microcomputer is impossible.

Further, since the clock is not supplied to the built-in module of the microcomputer, there is a problem that the timer malfunctions, for example, and it is very difficult to create software for controlling this period. It was

In a method in which it is possible to select whether to stop or continue oscillation of the main system clock during low power consumption operation by software, the same problem as described above occurs when the case of stopping oscillation is selected. On the contrary, when the case of continuing the oscillation is selected, the state transition period is eliminated, but there is a problem that the power consumption during the low power consumption operation becomes large.

[0008]

The outline of typical ones of the present invention will be briefly described as follows. In other words, the microcomputer can operate with multiple clocks with different frequencies, and start or stop the oscillation of the clock that is not used during operation at any timing within the period when the clock is not used. It has the means to make it possible. This means is not particularly limited, but can be realized by, for example, control by CPU instructions, register settings, interrupt control, or the like.

[0009]

According to the prior art, as shown in FIG. 4, the microcomputer can start oscillating the main system clock only after the low power consumption operation is completed, so that the state transition from the low power consumption operation to the normal operation is performed. It took time for the main system clock to stabilize.

However, according to the means of the present invention, it becomes possible to start the oscillation of the main system clock stopped during the low power consumption operation at an arbitrary timing. As shown in FIG. 5, if the timing for starting this oscillation is set to be before the time required for the oscillation of the main system clock to stabilize before the end of the low power consumption operation, the time for state transition will be It becomes unnecessary. As a result, the microcomputer can always control the system, so that the efficiency of system control can be improved.

Further, since there is no state in which the clock supplied to the built-in module of the microcomputer is stopped, it becomes much easier to create software for controlling the period of the state transition, which contributes to improvement of software efficiency.

[0012]

Embodiment 1 An embodiment of the present invention will be described in detail with reference to FIG. FIG. 1 is a system configuration diagram according to the first and second embodiments.

In the figure, 1 indicates a microcomputer. Reference numeral 2 is a main system clock oscillator used for normal operation, and 3 is a main system clock oscillator circuit. Reference numeral 4 is a subsystem clock oscillator used for low power consumption operation at a low frequency compared to the main system clock, and 5 is a subsystem clock oscillation circuit. Reference numeral 6 is a selector for selecting the clock used in the system from the main system clock and the subsystem clock, and 7 is an operation mode control circuit for controlling the operation of the system. Reference numeral 8 denotes a built-in CPU, which has an instruction to output a signal for starting oscillation of the main system clock. Reference numeral 9 indicates a plurality of built-in modules.

Next, the operation of this embodiment will be described.

(1) Now, the microcomputer 1 is normally operating, and the main system clock from the main system clock oscillator 2 and the main system clock oscillator circuit 3 is selected by the selector 6 and supplied to the CPU 8 and the built-in module 9. Has been done.

(2) Next, the microcomputer 1 shifts to the low power consumption operation by the operation mode control circuit 7. At this time, the selector 6 selects the subsystem clock from the subsystem clock oscillator 2 or the subsystem clock oscillation circuit 3 by the control signal from the operation mode control circuit 7.
It is supplied to the CPU 8 and the built-in module 9. The subsystem clock has a lower frequency than the main system clock, and the power consumed at this time is significantly reduced.

The operation mode control circuit 7 simultaneously outputs a stop signal to the main system clock oscillation circuit 3. The main system clock oscillator circuit 3 stops oscillation by this stop signal. This makes it possible to further reduce the power consumed in the low power consumption operation.

(3) In the program for controlling the microcomputer 1, when the current low power consumption operation transits to the normal operation, the oscillation of the main system clock becomes stable from the time when the low power consumption operation ends. More than the time required to
An instruction to output a signal for starting oscillation of the main system clock is executed.

When the program executes an instruction to output a signal for starting the oscillation of the main system clock, the main system clock oscillation circuit 3 restarts the oscillation stopped for the low power consumption operation. To start again during. At the timing when the low power consumption operation is completed and the subsystem clock is switched to the main system clock by the operation mode control circuit 7 and the selector 6, the main system clock oscillation is sufficiently stable. Therefore, the normal operation should be immediately performed. You can

Since the present invention is particularly effective in controlling the oscillation of the main system clock during the operation with low power consumption, the above description has shown only the control of the oscillation of the main system clock during the operation with low power consumption. However, control of the subsystem clock during normal operation is just as effective. The clock used by the microcomputer 1 is
The number is not limited to two and may be two or more. These are the same in all the following explanations.

Embodiment 2 By providing an oscillation control register instead of the instruction for outputting the signal for starting the oscillation of the main system clock in Embodiment 1, it is possible to realize the same operation as in Embodiment 1. is there.

FIG. 2 is a system configuration diagram according to the third embodiment of the present invention. In the figure, 10 is an oscillation control register for controlling the main system clock oscillation circuit 3. Reference numeral 11 indicates an internal data bus.

The value of the oscillation control register 10 is set by the CPU 8 via the internal data bus 11 at the same timing as the timing of executing the instruction to output the signal for starting the oscillation of the main system clock in the first embodiment. .. The output signal from the oscillation control register 10 can perform the same operation as in the first embodiment.

Further, since the main system clock oscillation circuit 3 can be controlled only by the oscillation control register 10, the main system clock oscillation circuit 3 can be controlled independently of the operation mode control circuit 7. If the signal from the oscillation control register 10 is, for example, "High" to start oscillation and "Low" to stop oscillation, one control signal is sufficient. These combinations are not particularly limited.

Embodiment 3 The oscillation control signal of the main system clock oscillation circuit 3 is
It can also be generated by interrupt control.

FIG. 3 is a system configuration diagram according to the embodiments of claim 4, claim 5, and claim 6. In the figure, 12 is a built-in timer built in the microcomputer 1.

The built-in timer 12 is a presettable timer. The internal timer 12 has a value set by the CPU 8 so that the timer overflows at the same timing as the timing at which the instruction for outputting the signal for starting the oscillation of the main system clock is executed in the internal timer 12. Is set via. The built-in timer 12 starts counting up from this preset value and generates an interrupt signal when the timer overflows. If this interrupt signal is used as an oscillation start signal for the main system clock oscillator circuit 3, the same operation as in the first and second embodiments can be performed using interrupt control.

If an external interrupt pin is used for interrupt control instead of the built-in timer 12 and the system is designed so that an interrupt from the external interrupt pin is input at the same timing as the timer overflows, the same operation is performed. Is possible.

[0029]

The effects obtained by the present invention will be briefly described as follows. That is, in the microcomputer, the time for the state transition from the low power consumption operation to the normal operation is unnecessary, and since the microcomputer can always control the system, the efficiency of system control can be improved. In addition, it is much easier to create software that controls the period of state transition, which can contribute to improving the efficiency of software.

[Brief description of drawings]

FIG. 1 is a block diagram of a microcomputer according to an embodiment of claims 1 and 2 that controls oscillation of a clock that is not used during operation according to a command from a CPU.

FIG. 2 is a block diagram of a microcomputer according to an embodiment of claim 3 that controls oscillation of a clock not used during operation by setting a register.

FIG. 3 is a block diagram of a microcomputer according to an embodiment of claim 4, claim 5, and claim 6 for controlling oscillation of a clock not used during operation by interrupt control.

FIG. 4 is a timing diagram for state transition from low power consumption operation to normal operation according to the prior art.

FIG. 5 is a timing diagram for state transition from low power consumption operation to normal operation according to the present invention.

[Explanation of symbols]

1 ... Microcomputer, 2 ... Main system clock oscillator, 3
... Main system clock oscillator circuit, 4 ... Subsystem clock oscillator, 5 ... Subsystem clock oscillator circuit,
6 ... Selector, 7 ... Operation mode control circuit, 8 ... CPU,
9 ... Built-in module, 10 ... Oscillation control register, 11 ...
Internal data bus, 12 ... Built-in timer.

Claims (6)

[Claims] 1. It is possible to operate with a plurality of clocks having different frequencies, and control oscillation of a clock that is not used during operation at any timing within a period when the clock is not used. Microcomputer featuring. 2. A microcomputer according to claim 1, wherein oscillation control of a clock not used during operation is controlled by a command from a CPU. 3. The microcomputer according to claim 1, wherein oscillation control of a clock not used during operation is controlled by setting a register or a flag. 4. The microcomputer according to claim 1, wherein oscillation control of a clock not used during operation is performed by interrupt control. 5. The microcomputer according to claim 4, wherein interrupt control is performed by interrupt control using a timer. 6. The microcomputer according to claim 4, wherein interrupt control is performed by interrupt control using an external pin.