JP2962087B2 - Power control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power control circuit,
In particular, in an integrated circuit such as a portable communication device that has a power-down function and operates by internally oscillating a system clock internally by a phase control circuit or the like, clock oscillation is unstable immediately after the power-down is released. The present invention relates to a circuit for preventing a malfunction of an integrated circuit.

[0002]

2. Description of the Related Art In recent years, it has been desired to reduce power consumption in various devices, reflecting effective utilization of energy.
Therefore, naturally, an integrated circuit is also provided with a power control circuit in order to suppress power consumption when not in use or during standby.

Hereinafter, with reference to FIGS. 9, 10 and 11,
A conventional power control circuit of an integrated circuit incorporating a phase control circuit will be described. 9, in the conventional integrated circuit 100, an external power control signal 110 is "1".
The level input performs a normal operation, and the power-down operation operates when the “0” level is input. The external frame signal 120 is 8 kHz, and the master clock 250 is 1
The clock and frequency dividing circuit 300 of about 024 kHz is a circuit that divides the master clock 250 by 128 to generate an internal frame signal 350 of about 8 kHz. The phase control circuit 200 also controls the oscillation frequency of the master clock so that the external frame signal 120 and the internal frame signal 350 are synchronized.
When the rise of the internal frame signal 350 is advanced from the rise of the internal frame signal 350, the oscillation frequency of the master clock 250 is controlled to a frequency lower than 1024 kHz (according to the phase difference). Then, the rising of the next internal frame signal 350 is delayed, and the phase difference between the external frame signal 120 and the internal frame signal 350 is reduced. Similarly, when the rise of the internal frame signal 350 is delayed with respect to the rise of the external frame signal 120, the master clock 250
Is controlled to a frequency higher than 1024 kHz (according to the phase difference), the oscillation period of the internal frame signal 350 is reduced, the rising of the next internal frame signal 350 is accelerated, and the external frame signal 120 and the internal frame signal 350 are increased. Is reduced.

[0004] By the above phase control operation, the internal frame signal 350 and the external frame signal 120 are synchronized, and the system clock 75 synchronized with the external frame signal 120 is synchronized.
0 (= master clock), other functional circuits 800
To work. Therefore, the circuit 800 can receive a data signal or the like synchronized with the external frame signal 120 without error.

Here, the power control operation of the conventional example will be described with reference to FIG.
0 and FIG. As shown in FIG.
At this point, when the power control signal 110 changes from “1” to “0” level and enters the power down mode from the normal operation mode, the phase control circuit immediately stops the oscillation of the master clock 250 and the output thereof becomes “0”. Level, whereby the system clock 750 naturally goes to the “0” level. Therefore, all operations of the circuit 800 by the system clock 750 in the integrated circuit are stopped, and power consumption in the circuit 800 can be suppressed.

Next, as shown in FIG. 11, when the power control signal 110 is set to "1" again and the power down is released, the phase control circuit 200 starts oscillating the master clock 250 and again receives the external frame signal 120 and the external frame signal 120. The internal frame signal 350 operates to be synchronized. However,
In the conventional example, since the master clock 250 is used as the system clock 750 as it is, immediately after the power-down is released, an unstable system clock such as the clock 250 in FIG. 750, other internal circuits 80
Since it operates at 0, there is a disadvantage that the integrated circuit 100 malfunctions immediately after the power down is released.

Further, since there is no means for knowing whether the clock is stable or unstable, when the integrated circuit 100 is externally controlled by a microcomputer or the like, the microcomputer guarantees that the integrated circuit 100 operates completely immediately after the power is released. It is necessary to wait for an arbitrary period of time (data output and the like during this period are treated as invalid).

[0008]

In the configuration of the conventional power control circuit, if the master clock 250 output from the phase control circuit is unstable immediately after the power down is released, the master clock 250 is used as it is as the system clock 750. Therefore, there is a disadvantage that the operation of the integrated circuit 100 is not guaranteed because the system clock 750 becomes unstable. Further, whether the integrated circuit 100 or an external microcomputer or the like controlling the integrated circuit 100 has no way of knowing whether the clock is stable or not. The disadvantage is that you have to wait for an arbitrary time, which is guaranteed to work.

An object of the present invention is to provide a power control circuit which solves the above-mentioned drawbacks and prevents generation of an unstable system clock.

[0010]

According to the present invention, there is provided a power control circuit having a power-down function and a phase control circuit, and operating on a system clock derived from the phase control circuit. A frequency dividing circuit that generates an internal frame signal by dividing the frequency, and generates the master clock, and controls the oscillation of the master clock so that the external frame signal from the outside and the internal frame signal are synchronized. The phase control circuit that powers down according to a first power control signal from the outside or the inside, performs a count operation with the master clock, and outputs a count value at any timing of the external frame,
A counter that repeats a count operation by resetting or presetting immediately after the output of the count value, a decoder that decodes the count value, determines whether the master clock is stable or unstable, and outputs a clock stability detection signal; A power control signal generating circuit that outputs a second power control signal from a power control signal and the clock stability detection signal; and a system clock generating circuit that generates the system clock from the second power control signal and the master clock. Wherein the counter and the decoder detect the stability of the master clock, and after detecting the stability of the master clock, generate the system clock.

[0011]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a power control circuit according to a first embodiment of the present invention.

In FIG. 1, the configuration of the present embodiment is such that a power down function and a phase control circuit 200 are built in an integrated circuit 100 which operates on a system clock using the phase control circuit 200 as a source. 250
A frequency dividing circuit 300 for generating an internal frame signal 350 by dividing the frequency of the external frame signal 1 from the outside of the integrated circuit 100 while generating the master clock 250
A circuit for controlling the oscillation of the master clock 250 so that the internal frame signal 350 and the internal frame signal 350 are synchronized, and the power down is performed according to a first power control signal 110 from outside or inside the integrated circuit 100. A phase control circuit 200, a counter 400 that counts with the master clock 250, outputs a count value at each arbitrary timing of the external frame signal 120, and resets or presets immediately after the count value is output to repeat the count operation. Decoder 500 that decodes the count value, determines whether the master clock 250 is stable or unstable, and outputs a clock stability detection signal 550.
A power control signal generating circuit 600 for outputting a second power control signal 650 from the power control signal 110 and the clock stability detection signal 550; and a system clock from the second power control signal 650 and the master clock 250. 750, and a counter 400 and the decoder 500 detect the stability of the master clock 250,
By generating the system clock 750 after detecting the stability of the master clock 250, the stable operation of the integrated circuit 100 after the power-down is released is guaranteed.

The first power control signal 110 input from the outside into the integrated circuit 100 performs a normal operation when inputting a "1" level and performs a power-down operation when inputting a "0" level. The external frame signal 120 is 8 kHz, the master clock 25
0 is a clock of about 1024 kHz oscillated by the phase control circuit 200, and the frequency divider 300 is a master clock 25
0 divided by 128 and internal frame signal 3 around 8 kHz
50 is a circuit for generating 50. The phase control circuit 200 adjusts the oscillation frequency of the master clock 250 so that the external frame signal 120 and the internal frame signal 350 are synchronized.
This is a circuit that controls exactly the same as in the conventional example. The counter 400 is reset when the external frame signal 120 is at the “1” level, and when the external signal is at the “0” level,
The count operation is continued by the master clock 250, and the count value 450 immediately before the rising of the external frame signal 120 rises.
Is output to the decoder 500. The decoder 500 is a circuit that decodes the count value 450 and outputs the clock stability detection signal 550 in synchronization with the rising of the external frame signal 120. Each of the count values 450 corresponds to the one shown in FIG. A clock stabilization detection signal 550 is output in response to the input. The power control signal generation circuit 600 is a circuit that outputs a second power control signal 650 from the first power control signal 110 and the clock stability detection signal 550. FIG.
It is shown in (A).

In FIG. 4A, a power control signal generating circuit 600 includes an AND circuit 610 to which a first power control signal 110 and a clock stability detection signal 550 are input.
And an inverter 620 to which the first power control signal 110 is input, and an SR flip-flop 630, and outputs a second power control signal 650.

The system clock generation circuit 700 is a circuit that outputs a logical product (AND) of the second power control signal 650 and the master clock 250 as a system clock 750. As described above, the internal functional circuit 800 operates with the system clock 750 synchronized with the generated external frame signal.

Next, FIGS. 1 (A) and 3 (A), (B) and FIG.
A power control operation according to the first embodiment of the present invention will be described with reference to FIG.

FIGS. 5 and 6 are timing charts showing a first portion and a second portion of the circuit operation of the first embodiment of FIG. 1, respectively. Following the first part of FIG. 5, the second part of FIG. 6 is shown. The first and second parts together show the entire circuit operation.

In the power down mode in which the first power control signal 110 becomes "0" level, in this embodiment, the phase control circuit 200 immediately stops the oscillation of the master clock 250 and outputs the same as in the conventional example. Becomes “0” level,
Accordingly, the system clock 750 is always at the “0” level (the second power control signal 650 and the master clock 25).
Therefore, the operation of the internal function circuit 800 by the system clock 750 in the integrated circuit 100 is stopped, and power consumption in the circuit 800 can be suppressed.

Next, as shown in FIGS. 5 and 6, at a point a, the first power control signal 110 changes from "0" to "1" level, and the first power down mode is released. When,
The phase control circuit 200 starts oscillating the master clock 250 and starts operating again so that the external frame signal 120 and the internal frame signal 350 are synchronized. Here, the counter 400 counts the interval (62.5 μSEC) of the “0” level of the external frame signal 120 (8 kHz) with the master clock 250 (1024 kHz if stable) generated by the phase control circuit 200. The count data immediately before the rising edge of the external frame signal 120 is output to the decoder 500 at the rising edge of the external frame signal 120 as a count value output 450. Here, if the master clock 250 is stable,
Naturally, the count value is 62.5 μSEC / (1/10
24 kHz) = 64 counts, which is in the range of 63 to 65 in consideration of phase shift and jitter. If the master clock 250 is unstable, the count value becomes 62
Below and above 66. Therefore, this count value is
By decoding in accordance with (A), it is possible to determine whether the clock is stable or unstable. B in FIGS. 5 and 6
Since the count value output is 58 between the point and the point c, the decoder 500 determines that the clock is unstable, and sets the output of the clock stability detection signal 550 to “0”. From the point c, the count value becomes 63 and the clock is stabilized, so that the output of the clock stability detection signal 550 is set to “1”. The power control signal generating circuit 600, that is, the circuit of FIG. 4A is a power down priority circuit in which when the first power control signal 110 becomes "0", the second power control signal 650 also becomes "0" immediately. The reason why the second power control signal 650 becomes "1" (power down release) is that the first power control signal 110 becomes "1" and the power down release is canceled, and then the clock stability detection signal 550 is output for the first time. Is "1", and in FIG. 6, the second power control signal 650 is released and becomes "1" at the point c. System clock generation circuit 700
Is the master clock 250 and the second power control signal 65
Since the system clock 750 is generated by the logical product with 0, the stabilized master clock is output as the system clock 750 after the point c in FIG.
Move 0.

That is, the power control circuit of the present embodiment
The fixed time (62.5 μSEC) when the external frame signal 120 is at the “0” level is determined by the master clock 250 (1024 kHz if stabilized) generated by the phase control circuit 200.
, And the decoder 500 detects the stability and instability of the clock based on the count value, that is, the number of master clocks 250 generated in a certain period of time. 650, and the function circuit 800 in the integrated circuit 100 immediately after the power control is released to generate the system clock 750.
Normal operation can be guaranteed.

If the configuration of the decoder 500 is the circuit shown in FIG.
The clock stability detection signal 550 is set to "1" only for values of ~ 65. That is, by detecting the stability of the clock a plurality of times in succession, a more reliable circuit operation is guaranteed.

Further, in the present embodiment, the master clock 250 generated by the phase control circuit 200 is used as the count clock of the counter 400, but it is realized by a clock generated at each frequency division stage of the frequency divider circuit 300. It is also possible.

FIG. 2 is a block diagram showing a power control circuit according to a second embodiment of the present invention. In FIG. 2, the power control circuit of the second embodiment of the present invention is different from the first embodiment of FIG. 1 in that the configuration of the power control signal generation circuit 600 differs from that of FIG. 4B, a point that a reset function is added to the frequency dividing circuit 300, and a point that the second power control signal 650 can be output to the outside at the output terminal 900.

First, differences between FIG. 4A and FIG. 4B will be described. The circuit shown in FIG. 4B is configured such that the output of the second power control signal 650 of the circuit shown in FIG.
0, an inverter 660, and an AND circuit 680 to add a function of outputting a reset signal 670 of the delay amount width of the delay circuit 640 when the second power control signal 650 rises. At 670, the frequency dividing circuit 300 is reset. Note that the timing at which the second power control signal 650 changes is the rising edge of the external frame signal 120, so that the reset signal 6
The output of 70 is also synchronized with the external frame signal 120.

Here, differences in operation will be described with reference to FIGS. 5 and 6 and FIGS. 7 and 8.

FIG. 7 is a timing chart showing a first part of the operation of the second embodiment of FIG. FIG. 8 is a timing chart showing a second part following the first part of FIG. FIG.
FIG. 8 is combined to form an overall timing diagram.

In the first embodiment, as shown in FIGS. 5 and 6, the oscillation of the master clock 250 is certainly stable at the point c, but the internal frame signal 350 obtained by dividing the master clock 250 has the following characteristics. The external frame signal 120 is not always synchronized. Therefore, it may take time for the phase control circuit 200 to control and synchronize the oscillation frequency of the master clock 250.

On the other hand, in the second embodiment, as shown in FIGS. 7 and 8, when the stability of the clock is detected at the point c ', as in the first embodiment, it is synchronized with the external frame signal 120. Then, since the second power control signal 650 becomes "1", a reset signal 670 is generated, and the external frame signal 120 is forcibly reset to divide the frequency dividing circuit 300.
Then, the synchronization of the internal frame signal 350 is executed, and the pull-in time is reduced.

The second power control signal 650 can be output to the outside of the integrated circuit 100 by the output terminal 900, so that the output terminal 900 can be monitored when an external microcomputer or the like controls the integrated circuit 100. And integrated circuit 1
00 can be confirmed whether it is operating stably.

[0030]

As described above, the power control circuit according to the present invention allows the section of the "0" level of the external frame signal to
Counting by the master clock generated by the phase control circuit, the decoder detects whether or not the master clock is stable based on the count value, and after the clock stability is detected, cancels the second power control signal, Since the system clock is generated and supplied, no malfunction occurs due to an unstable clock after the power down is released, and the functional circuit 80
0, the normal operation can be assured, and in particular, as shown in the second embodiment, by outputting the second control signal from the output terminal to the outside of the integrated circuit, However, it is possible to check whether this integrated circuit is operating with a stable clock, and when the clock after power-down release is stable, the frequency divider can be reset in synchronization with the external frame signal. In addition, there is an effect that it is possible to shorten the time for drawing the internal frame signal with respect to the external frame signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a power control circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a power control circuit according to a second embodiment of the present invention.

FIGS. 3A and 3B are diagrams showing the correspondence between the count value of the decoder of FIG. 1 and the clock stability detection signal, and the correspondence between the current count value, the past count value, and the clock stability detection signal, respectively. .

FIGS. 4A and 4B are block diagrams showing the power control signal generation circuit of FIG. 1 and the power control signal generation circuit of FIG. 2, respectively.

FIG. 5 is a timing chart showing a first part of the circuit operation of the first embodiment of FIG. 1;

FIG. 6 is a timing chart showing a second part following the first part in FIG. 5;

FIG. 7 is a timing chart showing a first part of the circuit operation of the second embodiment of FIG. 2;

FIG. 8 is a timing chart showing a second part following the first part of FIG. 7;

FIG. 9 is a block diagram showing a conventional power control circuit.

FIG. 10 is a timing chart when the power control circuit of FIG. 9 is turned on.

11 is a timing chart at the time of turning off the power control circuit of FIG. 9;

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 integrated circuit 110 first power control signal 120 external frame signal 200 phase control circuit 250 master clock 300 frequency divider 350 internal frame signal 400 counter 450 count value 500 decoder 550 clock stability detection signal 600 power control signal generation circuit 630 R- S type flip-flop 640 Delay circuit 650 Second power control signal 670 Frequency divider reset signal 700 System clock generation circuit 750 System clock 800 Circuit operated by system clock

Claims (4)

(57) [Claims] 1. A power control circuit having a power-down function and a phase control circuit, and operating on a system clock originating from the phase control circuit, generating a frame signal by dividing a master clock. A divider circuit,
While generating the master clock, controls the oscillation of the master clock so that the external frame signal from the outside and the internal frame signal are synchronized, and controls the power in response to the first external or internal power control signal. The phase control circuit that goes down, a counter that counts with the master clock, outputs a count value at any timing of the external frame, and resets or presets after the count value is output to repeat the count operation; and A decoder that decodes a value to determine whether the master clock is stable or unstable and outputs a clock stability detection signal; and outputs a second power control signal from the first power control signal and the clock stability detection signal. A power control signal generation circuit, the second power control signal and the master clock; And a system clock generating circuit for generating the system clock. The counter and the decoder detect the stability of the master clock, and generate the system clock after detecting the stability of the master clock. A power control circuit characterized by what has been done. 2. The power control circuit according to claim 1, wherein an arbitrary clock generated at each frequency division stage of said frequency divider circuit is selected and used as a count clock of said counter. 3. The power control circuit according to claim 1, wherein the decoder outputs the clock stability detection signal only when the stability detection of the master clock is detected a plurality of times in succession. . 4. The apparatus according to claim 1, wherein the frequency dividing circuit releases the power-down state by the second power control signal only immediately.
2. The power control circuit according to claim 1, wherein the power control circuit has a function of resetting in synchronization with the external clock, and shortens a synchronization time between the external frame signal and the internal frame signal.