KR19990019530A - PLL circuit achieves low current and low noise stabilization when locked - Google Patents

Abstract

A PLL circuit is disclosed that can reduce current consumption during locking and reinforce noise susceptibility.

The PLL circuit of the present invention includes a first m-divider, a first flip-flop, a first mux, a phase comparator, a charge pump and a filter, a VCO, a controller, an n-divider, a second m-divider, a second mux, and a second flip-flop.

The PLL circuit of the present invention divides the two signals for phase comparison at the time of locking by m and reduces the number of comparisons to 1 / m, thereby reducing the current consumed during comparison and enhancing immunity to instantaneous noise.

Description

PLL circuit realizes low current and low noise stabilization during locking

The present invention relates to a phase locked loop, and more particularly, to a phase locked loop circuit which realizes low current and low noise stabilization during locking.

Generally, a phase locked loop (PLL) is a circuit that detects a phase difference between an input signal and an oscillating output of a voltage controlled oscillator (VCO) to determine the frequency and phase of the VCO. I use it a lot to synchronize frequency.

1 is a block diagram of a conventional PLL circuit. The conventional phase locked loop (PLL) circuit includes a phase comparator 102 for phase comparing a reference signal (Ref) having a specific frequency input from the outside with a feedback signal generated therein, and Charge pump and filter unit 104 which detects a phase difference and maintains a constant power supply level, and a VCO 106 whose frequency varies according to the constant power supply level, and presets the frequencies of the VCO and the reference signal. And a control unit 108 for controlling the n-divider 110 so that it is always n-divided, and a flip-flop 112 for storing the VCO data.

Referring to FIG. 1, a conventional PLL circuit compares a phase of an internal signal generated from an internal reference signal Ref with an external signal. When the frequency of the VCO 106 has n times the reference signal, it is divided at the same frequency through the n-divider 110 and then compared through a phase comparator 102 to compare the results with the charge pump and filter. Transition to unit 104 and back to VCO 106 is controlled and oscillated. The controller 108 controls the n-divider to always divide n-by setting the frequencies of the VCO and the reference signal in advance.

In general, because the frequency oscillated in the VCO is higher than the reference signal input from the outside, it is n-divided to compare the phases or divide the two signals by an arbitrary m to compare the phases. The PLL circuit is always configured to be active at all times as the level of the charge pump is changed and delivered directly to the VCO.

When the phase locks due to constant phase, the VCO finds stability. When the frequency of the two signals to be compared is high, the PLL circuit is sensitive to the comparison and is fast in response, but vulnerable to instantaneous noise. In this case, the PLL circuit is less sensitive to comparisons, making the response rate somewhat slower but strong against instantaneous noise. By splitting the input signal by an arbitrary m times, it is possible to expand the selection of external input signals so that the system maker can synchronize with the desired system clock.

However, even when locked and the VCO operates stably, this phase comparison continues to operate at the same frequency, resulting in the same current consumption and noise vulnerabilities.

Accordingly, it is an object of the present invention to provide a PLL circuit that can reduce current consumption and reinforce noise susceptibility compared to before locking, by comparing the PLL circuit m by multiplying the signals in front of the phase comparator when locked.

1 is a block diagram of a conventional PLL circuit.

2 is a block diagram of a PLL circuit according to the present invention.

Fig. 3 is a timing diagram in which phases are compared by 4 (m = 4) times according to the present invention.

4 is a phase comparison timing diagram divided by four times according to the present invention and enhanced immunity to instantaneous noise.

The PLL circuit of the present invention for achieving the above object includes a first m-divider, a first flip-flop, a first mux, a phase comparator, a charge pump and a filter, a VCO, a controller, n A divider, a second m-divider, a second mux, and a second flip-flop.

The first m-divider divides the input signal by m when the locking signal drops from the controller.

The first flip-flop stores and transmits the m divided signals.

The first mux selects and transmits either an input signal or the m-divided signal by the controller.

The phase comparison unit phase compares an externally input reference signal with an internally generated feedback signal or phase compares an m-divided input signal with an m-divided internal feedback signal.

The charge pump and the filter unit detect a phase difference of the phase comparator and maintain a constant power level.

The VCO oscillates and outputs a frequency in accordance with the constant power level.

The control unit controls an n-divider to n-divide the oscillating output of the VCO, and controls the phase by controlling the first m-divider, the first mux, the second m-divider, and the second mux when locked. Allows two signals to be compared m divided.

The n-divider n-divides the oscillating output of the VCO according to the signal of the controller.

The second m-divider divides the internal signal m according to the signal of the controller.

The second mux selects and transmits either an internal signal or a m-divided signal by the controller.

The second flip-flop stores and transmits an internal signal or a m divided signal.

Therefore, according to the present invention, by dividing the two signals to be compared in phase when locking in the PLL circuit by m divided by 1 / m, the current consumed in comparison is reduced and the immunity to instantaneous noise is enhanced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a PLL circuit according to the present invention. Referring to FIG. 2, the noise immunity enhanced PLL circuit of the present invention includes a first m-divider 202, a first flip-flop 204, a first mux 206, and a phase comparator 208. The charge pump and filter unit 210, the VCO 212, the control unit 214, the n-divider 216, the second m-divider 218, the second mux 220, and A second flip flop 222 is provided.

The first m-divider 202 divides the input signal Ref by m when the locking signal drops from the controller 214. The first flip-flop 204 stores and transmits the m divided signals. The first mux 206 selects and transmits either the input signal Ref or the m-divided signal by the controller 214. The phase comparator 208 phase compares an externally input reference signal Ref with an internally generated feedback signal or phase compares an m-divided input signal with an m-divided internal feedback signal. The charge pump and filter unit 210 maintains a constant power level by detecting a phase difference of the phase comparator. The VCO 212 oscillates and outputs a frequency in accordance with the predetermined power level. The control unit 214 controls the n-divider to n-divide the oscillating output of the VCO, and controls the first m-divider, the first mux, the second m-divider, and the second mux when locked. Controls and divides the m signals for phase comparison. The n-divider 216 n-divides the oscillating output of the VCO according to the signal of the controller. The second m-divider 218 divides the internal signal m according to the signal of the controller. The second mux 220 selectively transmits either an internal signal or a m-divided signal by the controller. The second flip-flop 222 stores and transmits an internal signal or a m-divided signal.

The PLL circuit according to the present invention operates in the same manner as the conventional PLL circuit of FIG. 1 before locking, wherein the controller 214 is an A, C control signal of the first m-divider 202 and the second m-divider. A reset is performed to disable the operation, and the first mux 206 and the second mux 220 are controlled as B and D control signals to compare signals not passed through the m-dividers 202 and 218. To help.

When the VCO becomes stable and the locking signal drops from the control unit 214, each new control signal is added to the first and second m-dividers 202 and 218 and the first and second muxes 206 and 220, thereby initially locking. Compared to the signal divided by m times than the previous signal, the comparison is reduced by 1 / m to reduce the current consumed in comparison, and it can react insensitively to the reference signal delayed or accelerated by external noise as much as 1 / m. This results in a stable PLL circuit.

Fig. 3 is a timing diagram in which phases are compared by 4 (m = 4) times according to the present invention. Referring to FIG. 3, (A) is a phase comparison timing diagram of the reference signal Ref and the internal signal Int by the PLL circuit of FIG. 1, and (B) is a reference signal Ref by the PLL circuit of FIG. 2. ) Is a timing comparison timing chart of the internal signal Int. (A) shows the comparison at every rising edge, and (B) shows that the number of comparison is reduced to 1/4 when m is 4 during locking. Accordingly, it can be seen that the present invention can reduce the current consumed during comparison by reducing the comparison by 1/4.

4 is a phase comparison timing diagram divided by four times according to the present invention and enhanced immunity to instantaneous noise. Referring to FIG. 4, (A) is a phase comparison timing diagram of the reference signal Ref and the internal signal Int by the PLL circuit of FIG. 1, and (B) is a reference signal Ref by the PLL circuit of FIG. 2. ) Is a timing comparison timing chart of the internal signal Int. The phase delay shown in (A) directly affects the VCO. However, it can be seen that the present invention is a stable PLL circuit because the comparison is made less by 1/4 to react insensitively to the reference signal Ref delayed or accelerated by external noise.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

As described above, the PLL circuit of the present invention divides the two signals for phase comparison at the time of locking by m to reduce the number of comparisons to 1 / m, thereby reducing the current consumed during comparison and enhancing immunity to instantaneous noise.

Claims (2)

A first m-divider for dividing the input signal by m when the locking signal drops from the controller; A first flip-flop for storing and transmitting the m-divided signal; A first mux for selectively transmitting either an input signal or the m-divided signal by a control unit; A phase comparison unit configured to phase compare a reference signal input from an external source and a feedback signal generated internally or phase compare an m-divided input signal and an m-divided internal feedback signal; A charge pump and filter unit for detecting a phase difference of the phase comparison unit to maintain a constant power level; A VCO oscillating and outputting a frequency in accordance with the predetermined power supply level; Controlling the n-divider to n-divide the oscillating output of the VCO, and controlling and comparing the phase by controlling the first m-divider, the first mux, the second m-divider, and the second mux during locking. A control unit for dividing the signal by m, An n-divider for n-dividing the oscillating output of the VCO according to the signal of the controller; A second m-divider for dividing the internal signal by m according to the signal of the controller; A second mux for selectively transmitting either the internal signal or the m-divided internal signal by the controller, and And a second flip-flop for storing and transmitting the internal signal and the m divided internal signal. PLL circuit, characterized in that the PLL circuit characterized in that the reference signal to compare the phase compared to the internal signal at the time of locking and m to reduce the number of comparison to 1 / m to reduce the current consumed during comparison and to increase the immunity to instantaneous noise How it works.